Otn device single board, fec operation method and device, dsp chip and otn device

Abstract

The application discloses an OTN device single board, an FEC operation method and device, a DSP chip and an OTN device, and relates to the technical field of communication. The OTN device single board comprises at least two optical interfaces, each optical interface is used for receiving an optical signal, and performing photoelectric conversion on the optical signal to obtain an electrical signal; a digital signal processing (DSP) module, the DSP module is electrically connected with the at least two optical interfaces respectively, the DSP module comprises K forward error correction (FEC) operation units, and K is a positive integer; the DSP module is used for performing FEC processing on each electrical signal based on the K FEC operation units in the case that at least one electrical signal sent by the at least two optical interfaces is received; and at least two framing units, the at least two framing units are electrically connected with the DSP module respectively, and each framing unit is used for performing framing processing on the electrical signal sent by the DSP module. The application improves the use efficiency of FEC operation resources and reduces power consumption.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to an OTN device board, an FEC calculation method, a device, a DSP chip, and an OTN device. Background Technology

[0002] Optical Transport Network (OTN) equipment is widely deployed in backbone and metropolitan area networks. As the capacity of OTN equipment continues to increase, its rated power consumption also rises. In terms of power consumption percentage, the line-side Digital Signal Processing (DSP) chip, as the foundation for OTN to achieve long-distance, high-capacity transmission, accounts for a significant portion of the power consumption.

[0003] Currently, to ensure transmission performance, the required number of forward error correction (FEC) decoding stages for each DSP chip is typically pre-designed. However, in practical applications, due to differences in core components such as lasers and modulators, the required number of FEC decoding stages for different channels can vary. A fixed number of decoding stages can lead to redundant computation and corresponding power consumption issues. Summary of the Invention

[0004] This invention provides an OTN device board, an FEC calculation method, a device, a DSP chip, and an OTN device to solve the problems of high power consumption and redundant calculations when performing FEC calculations on OTN devices.

[0005] To solve the above-mentioned technical problems, the present invention is implemented as follows:

[0006] In a first aspect, embodiments of the present invention provide a single board for an optical transport network (OTN) device, comprising:

[0007] At least two optical interfaces, each of which is used to receive optical signals and perform photoelectric conversion on the optical signals to obtain electrical signals;

[0008] A digital signal processing (DSP) module is electrically connected to the at least two optical interfaces. The DSP module includes K forward error correction (FEC) operation units, where K is a positive integer. The DSP module is used to perform FEC processing on each of the electrical signals based on the K FEC operation units when receiving at least one of the electrical signals transmitted by the at least two optical interfaces.

[0009] At least two framing units are provided, each of which is electrically connected to the DSP module. Each framing unit is used to perform framing processing on the electrical signals sent by the DSP module.

[0010] Optionally, at least one of the electrical signals includes a first electrical signal; the DSP module is used for:

[0011] Receive the first electrical signal;

[0012] In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units, where N is a positive integer and N≤K.

[0013] Optionally, the DSP module is used for:

[0014] In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal;

[0015] The operation order of the N first FEC operation units is determined, and the first electrical signal is sequentially input into the N first FEC operation units for processing according to the operation order;

[0016] N is determined based on the signal characteristic information of the first electrical signal.

[0017] Optionally, the DSP module is used for:

[0018] In response to the first electrical signal, the number N1 of the currently available FEC operation units among the K FEC operation units is obtained, where N1 is a positive integer;

[0019] If N1 < N, release the computing resources of the FEC computing units that have been allocated and whose operations have ended, and update the number of currently available FEC computing units to N2 based on the number of FEC computing units released, where N2 is a positive integer.

[0020] When N2≥N, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal.

[0021] Optionally, N is determined based on at least one of the pre-correction bit error rate and signal-to-noise ratio of the first electrical signal.

[0022] Optionally, the DSP module is used for:

[0023] In response to the first electrical signal, a first target FEC operation unit is determined from the K FEC operation units, and the first target FEC operation unit is assigned to the first electrical signal;

[0024] The first electrical signal is input into the first target FEC processing unit for processing;

[0025] When the first target FEC operation unit finishes its operation, a second target FEC operation unit is determined from the currently available FEC operation units, and the second target FEC operation unit is assigned to the first electrical signal;

[0026] The first electrical signal, after being processed by the first target FEC processing unit, is input into the second target FEC processing unit for further processing, and the processing resources of the first target FEC processing unit are released.

[0027] Optionally, the DSP module is used for:

[0028] In response to the first electrical signal, the priority information of the first electrical signal is obtained;

[0029] Based on the priority information, N first FEC operation units are determined among the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units.

[0030] Optionally, the DSP module further includes a control unit, which is electrically connected to the K FEC operation units respectively. The control unit is used to respond to the first electrical signal, determine N first FEC operation units among the K FEC operation units, and process the first electrical signal based on the N first FEC operation units.

[0031] Optionally, the device board is communicatively connected to the network management device; the DSP module is also used for:

[0032] In response to the first electrical signal, a first request is sent to the network management device. The first request carries the first electrical signal and is used to request the network management device to determine N first FEC operation units among the K FEC operation units, and to send first indication information to the device board to indicate the N first FEC operation units.

[0033] Receive the first instruction information and determine the N first FEC operation units based on the first instruction information;

[0034] The first electrical signal is processed based on the N first FEC operation units.

[0035] Secondly, embodiments of the present invention also provide a forward error correction (FEC) operation method, the method being applied to a DSP module in an OTN equipment board, the DSP module comprising K FEC operation units, where K is a positive integer, and the DSP module being electrically connected to at least two optical interfaces respectively.

[0036] The method includes:

[0037] Receive at least one electrical signal, which is obtained by photoelectric conversion of the received optical signal by the optical interface;

[0038] Based on the K FEC operation units, FEC processing is performed on each of the electrical signals.

[0039] Optionally, the at least one electrical signal includes a first electrical signal; the step of performing FEC processing on each of the electrical signals based on the K FEC operation units includes:

[0040] In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units, where N is a positive integer and N≤K.

[0041] Optionally, the step of determining N first FEC operation units among the K FEC operation units in response to the first electrical signal, and processing the first electrical signal based on the N first FEC operation units, includes:

[0042] In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal;

[0043] The operation order of the N first FEC operation units is determined, and the first electrical signal is sequentially input into the N first FEC operation units for processing according to the operation order;

[0044] N is determined based on the signal characteristic information of the first electrical signal.

[0045] Optionally, the step of determining N first FEC operation units from the K FEC operation units in response to the first electrical signal, and allocating the N first FEC operation units to the first electrical signal, includes:

[0046] In response to the first electrical signal, the number N1 of the currently available FEC operation units among the K FEC operation units is obtained, where N1 is a positive integer;

[0047] If N1 < N, release the computing resources of the FEC computing units that have been allocated and whose operations have ended, and update the number of currently available FEC computing units to N2 based on the number of FEC computing units released, where N2 is a positive integer.

[0048] When N2≥N, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal.

[0049] Optionally, N is determined based on at least one of the pre-correction bit error rate and signal-to-noise ratio of the first electrical signal.

[0050] Optionally, the step of determining N first FEC operation units among the K FEC operation units in response to the first electrical signal, and processing the first electrical signal based on the N first FEC operation units, includes:

[0051] In response to the first electrical signal, a first target FEC operation unit is determined from the K FEC operation units, and the first target FEC operation unit is assigned to the first electrical signal;

[0052] The first electrical signal is input into the first target FEC processing unit for processing;

[0053] When the first target FEC operation unit finishes its operation, a second target FEC operation unit is determined from the available FEC operation units, and the second target FEC operation unit is assigned to the first electrical signal;

[0054] The first electrical signal, after being processed by the first target FEC processing unit, is input into the second target FEC processing unit for further processing, and the processing resources of the first target FEC processing unit are released.

[0055] Optionally, the step of determining N first FEC operation units among the K FEC operation units in response to the first electrical signal, and processing the first electrical signal based on the N first FEC operation units, includes:

[0056] In response to the first electrical signal, the priority information of the first electrical signal is obtained;

[0057] Based on the priority information, N first FEC operation units are determined among the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units.

[0058] Optionally, the device board is communicatively connected to the network management device; after receiving at least one electrical signal, the method further includes:

[0059] In response to the first electrical signal, a first request is sent to the network management device. The first request carries the first electrical signal and is used to request the network management device to determine N first FEC operation units among the K FEC operation units, and to send first indication information to the device board to indicate the N first FEC operation units.

[0060] Receive the first instruction information and determine the N first FEC operation units based on the first instruction information;

[0061] The first electrical signal is processed based on the N first FEC operation units.

[0062] Thirdly, embodiments of the present invention also provide a forward error correction (FEC) computing device, the device comprising K FEC computing units, where K is a positive integer, and the device is electrically connected to at least two optical interfaces respectively;

[0063] The device further includes:

[0064] The first receiving module is used to receive at least one electrical signal, which is obtained by photoelectric conversion of the received optical signal by the optical interface.

[0065] The first processing module is used to perform FEC processing on each of the electrical signals based on the K FEC operation units.

[0066] Optionally, the at least one electrical signal includes a first electrical signal; the first processing module is used to:

[0067] In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units, where N is a positive integer and N≤K.

[0068] Optionally, the first processing module includes:

[0069] A first allocation unit is configured to, in response to the first electrical signal, determine N first FEC operation units from the K FEC operation units and allocate the N first FEC operation units to the first electrical signal;

[0070] The first processing unit is used to determine the operation order of the N first FEC operation units, and to input the first electrical signal into the N first FEC operation units for processing according to the operation order.

[0071] N is determined based on the signal characteristic information of the first electrical signal.

[0072] Optionally, the first allocation unit is used to:

[0073] In response to the first electrical signal, the number N1 of the currently available FEC operation units among the K FEC operation units is obtained, where N1 is a positive integer;

[0074] If N1 < N, release the computing resources of the FEC computing units that have been allocated and whose operations have ended, and update the number of currently available FEC computing units to N2 based on the number of FEC computing units released, where N2 is a positive integer.

[0075] When N2≥N, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal.

[0076] Optionally, N is determined based on at least one of the pre-correction bit error rate and signal-to-noise ratio of the first electrical signal.

[0077] Optionally, the first processing module includes:

[0078] The second allocation unit is configured to, in response to the first electrical signal, determine a first target FEC operation unit among the K FEC operation units and allocate the first target FEC operation unit to the first electrical signal;

[0079] The second processing unit is used to input the first electrical signal into the first target FEC arithmetic unit for processing.

[0080] The third allocation unit is used to determine the second target FEC operation unit among the available FEC operation units when the first target FEC operation unit has finished its operation, and to allocate the second target FEC operation unit to the first electrical signal.

[0081] The third processing unit is used to input the first electrical signal processed by the first target FEC processing unit into the second target FEC processing unit for processing, and to release the processing resources of the first target FEC processing unit.

[0082] Optionally, the first processing module includes:

[0083] The acquisition unit is used to acquire the priority information of the first electrical signal in response to the first electrical signal;

[0084] The fourth processing unit is configured to determine N first FEC operation units among the K FEC operation units according to the priority information, and process the first electrical signal based on the N first FEC operation units.

[0085] Optionally, the device board is communicatively connected to the network management device; the FEC processing unit further includes:

[0086] The sending module is configured to respond to the first electrical signal and send a first request to the network management device. The first request carries the first electrical signal and is configured to request the network management device to determine N first FEC operation units among the K FEC operation units and send first indication information to the device board to indicate the N first FEC operation units.

[0087] The second receiving module is used to receive the first indication information and determine the N first FEC operation units based on the first indication information;

[0088] The second processing module is used to process the first electrical signal based on the N first FEC operation units.

[0089] Fourthly, embodiments of the present invention also provide a digital signal processing (DSP) chip that performs the steps in the forward error correction (FEC) operation method described above.

[0090] Fifthly, embodiments of the present invention also provide an optical transport network (OTN) device, including a transceiver and a processor.

[0091] The transceiver is used to: receive optical signals;

[0092] The processor is used for:

[0093] The optical signal is converted into an electrical signal by photoelectric conversion.

[0094] Based on K FEC operation units, FEC processing is performed on each of the aforementioned electrical signals;

[0095] The electrical signals obtained after FEC processing are framed.

[0096] Optionally, the at least one electrical signal includes a first electrical signal; the processor is used to:

[0097] In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units, where N is a positive integer and N≤K.

[0098] Optionally, the processor is used to:

[0099] In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal;

[0100] The operation order of the N first FEC operation units is determined, and the first electrical signal is sequentially input into the N first FEC operation units for processing according to the operation order;

[0101] N is determined based on the signal characteristic information of the first electrical signal.

[0102] Optionally, the processor is used to:

[0103] In response to the first electrical signal, the number N1 of the currently available FEC operation units among the K FEC operation units is obtained, where N1 is a positive integer;

[0104] If N1 < N, release the computing resources of the FEC computing units that have been allocated and whose operations have ended, and update the number of currently available FEC computing units to N2 based on the number of FEC computing units released, where N2 is a positive integer.

[0105] When N2≥N, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal.

[0106] Optionally, N is determined based on at least one of the pre-correction bit error rate and signal-to-noise ratio of the first electrical signal.

[0107] Optionally, the processor is used to:

[0108] In response to the first electrical signal, a first target FEC operation unit is determined from the K FEC operation units, and the first target FEC operation unit is assigned to the first electrical signal;

[0109] The first electrical signal is input into the first target FEC processing unit for processing;

[0110] When the first target FEC operation unit finishes its operation, a second target FEC operation unit is determined from the available FEC operation units, and the second target FEC operation unit is assigned to the first electrical signal;

[0111] The first electrical signal, after being processed by the first target FEC processing unit, is input into the second target FEC processing unit for further processing, and the processing resources of the first target FEC processing unit are released.

[0112] Optionally, the processor is used to:

[0113] In response to the first electrical signal, the priority information of the first electrical signal is obtained;

[0114] Based on the priority information, N first FEC operation units are determined among the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units.

[0115] Optionally, the device board is communicatively connected to the network management device; the transceiver is also used for:

[0116] In response to the first electrical signal, a first request is sent to the network management device. The first request carries the first electrical signal and is used to request the network management device to determine N first FEC operation units among the K FEC operation units, and to send first indication information to the device board to indicate the N first FEC operation units.

[0117] Receive the first instruction information and determine the N first FEC operation units based on the first instruction information;

[0118] The processor is used for:

[0119] The first electrical signal is processed based on the N first FEC operation units.

[0120] In a sixth aspect, embodiments of the present invention also provide an optical transport network (OTN) device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the forward error correction (FEC) operation method as described above.

[0121] In a seventh aspect, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in the forward error correction (FEC) operation method as described above.

[0122] In this embodiment of the invention, the FEC computing resources of multiple DSP modules in related technologies are integrated together, meaning that only one DSP module is set on a single OTN device, and this DSP module integrates an FEC computing resource pool. By pooling the FEC computing resources, different line channels can share the computing resources in the FEC computing resource pool, and one or more FEC computing units in the FEC computing resource pool can be used according to actual needs, thereby reducing the redundancy of FEC computing resources on the OTN device board, and thus reducing the power consumption caused by computing resource redundancy. Attached Figure Description

[0123] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0124] Figure 1 This is a structural diagram of an OTN device board in related technologies;

[0125] Figure 2 This is a schematic diagram illustrating the allocation principle of FEC computing units in related technologies;

[0126] Figure 3 This is a schematic diagram of the structure of an OTN device board provided in an embodiment of the present invention;

[0127] Figure 4 This is a schematic diagram illustrating the allocation principle of the FEC operation unit provided in an embodiment of the present invention;

[0128] Figure 5 This is a flowchart illustrating the multi-level FEC operation provided in an embodiment of the present invention;

[0129] Figure 6 This is a flowchart illustrating the FEC calculation method provided in an embodiment of the present invention;

[0130] Figure 7 This is a schematic diagram of the structure of the FEC computing device provided in an embodiment of the present invention;

[0131] Figure 8 This is a schematic diagram of the structure of the OTN device provided in an embodiment of the present invention. Detailed Implementation

[0132] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0133] In related technologies, a typical OTN device board has multiple line ports, and each line port has a corresponding line channel with a DSP module. Each line channel independently uses the FEC computing resources in its corresponding DSP module for FEC processing, such as... Figure 1As shown. To ensure transmission performance, the FEC decoding level capability of each DSP module is usually pre-designed. For example, if the FEC decoding level of each DSP module is pre-determined to be 7, then each line channel can use 7 FEC operation units, such as... Figure 2 As shown. Considering the extreme cases of low optical signal-to-noise ratio (OSNR) margin and high bit error rate before correction at the end of each line channel, the FEC decoding level of each DSP module is usually set to the maximum value. However, in practical applications, most scenarios do not require the maximum FEC decoding level. Furthermore, considering the differences between different lasers, modulators, and other devices, the actual number of FEC decoding levels required for different line channels varies. A predetermined number of FEC decoding levels will cause resource redundancy and corresponding power consumption issues for some line channels.

[0134] This invention provides an OTN device board, such as... Figure 3 As shown, it includes:

[0135] At least two optical interfaces, each used to receive optical signals and perform photoelectric conversion on the optical signals to obtain electrical signals;

[0136] The DSP module is electrically connected to at least two optical interfaces. The DSP module includes K FEC (Flexible Encoding and Computation) units, where K is a positive integer. Specifically, the DSP module performs FEC processing on each electrical signal based on the K FEC units upon receiving at least one electrical signal from at least two optical interfaces.

[0137] At least two framing units are electrically connected to the DSP module, and each framing unit is used to perform framing processing on the electrical signals sent by the DSP module.

[0138] In practice, one optical interface corresponds to one line channel. After receiving the optical signal from the corresponding line channel, the optical interface performs photoelectric conversion to obtain an electrical signal, which is then input into the DSP module. The framing unit is used to encapsulate or decapsulate OTN frame formats. The number of framing units can be the same as the number of optical interfaces, or multiple line channels can share one framing unit. The specific number can be determined according to the actual situation and is not limited here.

[0139] The DSP module integrates the functions and capabilities of multiple DSP chips in related technologies. In other words, in this embodiment of the invention, the FEC computing resources on multiple DSP chips are integrated to form an FEC computing resource pool, which can be specifically divided into K FEC computing units and integrated into the DSP module. The DSP module can arbitrarily use one or more of the K FEC computing units for FEC processing. The DSP module can be electrically connected in parallel to at least two optical interfaces and at least two framing units to process multiple electrical signals in parallel. Electrical signals in different line channels can share the aforementioned K FEC computing units. When the DSP module receives multiple electrical signals, it can determine the one or more FEC computing units actually needed for each electrical signal, such as... Figure 4 As shown, this enables flexible allocation of FEC computing resources, especially redundant computing resources, thereby improving the utilization efficiency of FEC computing resources.

[0140] In this embodiment of the invention, the FEC computing resources of multiple DSP modules in related technologies are integrated together, meaning that only one DSP module is set up on a single OTN device, and this DSP module integrates an FEC computing resource pool. By pooling the FEC computing resources, different line channels can share the computing resources in the FEC computing resource pool, and one or more FEC computing units in the FEC computing resource pool can be used according to actual needs, thereby reducing the redundancy of FEC computing resources on the OTN device board, and thus reducing the power consumption caused by computing resource redundancy.

[0141] Optionally, at least one electrical signal includes a first electrical signal; the DSP module is specifically used for:

[0142] Receive a first electrical signal; in response to the first electrical signal, determine N first FEC operation units among K FEC operation units, and process the first electrical signal based on the N first FEC operation units, where N is a positive integer and N≤K.

[0143] In this embodiment, the first electrical signal can be understood as any electrical signal received by the DSP module. When the DSP module receives the first electrical signal, it can obtain a preset allocation rule and determine the N FEC operation units actually needed for the first electrical signal from among the K FEC operation units based on the preset allocation rule, so as to use these N first FEC operation units to process the first electrical signal.

[0144] In specific implementation, the aforementioned preset allocation rules may include rules for determining the FEC decoding level, i.e., how to determine the value of N. In an optional embodiment, N is determined based on the signal characteristic information of the first electrical signal. For example, it can be determined based on the parameter values ​​of parameters such as the bit error rate and signal-to-noise ratio of the first electrical signal. The DSP module can pre-store the correspondence between the feature values ​​of the target features of the first electrical signal and the FEC decoding level. When the first electrical signal is received, the corresponding decoding level can be found by obtaining the feature values ​​of the target features of the first electrical signal, and the value of N can be determined.

[0145] The aforementioned preset allocation rule may also include an allocation rule for N first FEC operation units, that is, selecting which N FEC operation units to use as first FEC operation units from among K FEC operation units. In an optional embodiment, N first FEC operation units can be determined from among K FEC operation units based on the priority information of the first electrical signal. It should be noted that the allocation rule for the N first FEC operation resources can be determined according to the actual situation, and is not limited here.

[0146] The aforementioned preset allocation rules may also include path rules for the N first FEC operation units, i.e., how to determine the processing order of the N first FEC operation units. The DSP module can process the first electrical signal step by step based on the above processing order. In an optional embodiment, the path rules for the N first FEC operation units may include the identification information of each level of the first FEC operation unit. The identification information may be the sequence number information, position information, etc. of the FEC operation unit at that level, which is not limited here. For example, K FEC operation units may be arranged in the DSP module in the form of an array. The DSP module can control the path rules of the N first FEC operation units based on the position of each FEC operation unit in the array. For example, each FEC operation unit in the array is numbered in the order from top to bottom and from left to right. If the N first FEC operation units are the first N FEC operation units in the first row of the array, then the path rules may be: the first-level FEC operation unit is the first FEC operation unit in the first row of the array, the second-level FEC operation unit is the second FEC operation unit in the first row of the array, and so on.

[0147] The two optional implementation methods of this embodiment are described in detail below:

[0148] Implementation Method 1

[0149] Optionally, the DSP module is used for:

[0150] In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are allocated to the first electrical signal;

[0151] Determine the operation order of the N first FEC operation units, and input the first electrical signal into the N first FEC operation units for processing according to the operation order;

[0152] N is determined based on the signal characteristic information of the first electrical signal.

[0153] In this embodiment, the DSP module reserves computing resources for N first FEC (First-Order Evolution) processing units for the first electrical signal. Once the DSP module responds to the first electrical signal and determines the N first FEC processing units, these N units are occupied by the first electrical signal. Before the FEC processing of the first electrical signal is completed, the computing resources of these N first FEC processing units cannot be allocated to other electrical signals. This ensures that each electrical signal has sufficient computing resources, reducing the impact on system transmission performance.

[0154] In specific implementation, such as Figure 5 As shown, when the first electrical signal is input into the first-level FEC operation unit among the N first FEC operation units, the first-level FEC operation unit needs to determine whether the first electrical signal meets the FEC processing conditions. For example, it can determine whether the parameter values ​​of the first electrical signal, such as the bit error rate before correction and the signal-to-noise ratio, meet the system performance requirements. If the system performance requirements are met, it indicates that the first electrical signal does not need to undergo FEC processing, and the first electrical signal can be configured to be output. If the system performance requirements are not met, it indicates that the first electrical signal needs to undergo FEC processing. In this case, the first-level FEC operation unit performs first-level FEC processing on the first electrical signal, and inputs the processed first electrical signal into the second-level FEC operation unit among the N first FEC operation units. The second-level FEC operation unit then performs second-level FEC processing on the first electrical signal, and so on.

[0155] In this embodiment, optionally, the DSP module is used for:

[0156] In response to the first electrical signal, obtain the number N1 of the currently available FEC operation units among the K FEC operation units, where N1 is a positive integer;

[0157] If N1 < N, release the computing resources of the FEC computing units that have been allocated and whose operations have ended, and update the number of currently available FEC computing units to N2 based on the number of FEC computing units released, where N2 is a positive integer.

[0158] When N2≥N, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal.

[0159] In practical implementation, upon receiving the first electrical signal, if the DSP module is already processing other electrical signals in parallel, and the currently available FEC (Functional EC Programming) units are insufficient to meet the needs of the first electrical signal, the first electrical signal can wait for processing. For example, when the DSP module receives the maximum number of electrical signals, the available FEC units may be insufficient for one or more subsequent received electrical signals. In this case, the DSP module can monitor the status of the currently allocated FEC units and promptly release the computing resources of FEC units that have finished processing. For instance, if an allocated FEC unit has finished processing other electrical signals, the DSP module can release its computing resources and update the status of that FEC unit to available. The DSP module continuously monitors, and only processes the first electrical signal when the currently available FEC units can meet its needs.

[0160] It should be noted that if there are two or more electrical signals waiting to be processed, they can be sorted according to the order in which they were received; alternatively, they can be sorted according to their priority information. Subsequently, reserved FEC processing units can be obtained sequentially for each of the multiple electrical signals waiting to be processed.

[0161] Implementation Method 2

[0162] Optionally, the DSP module is used for:

[0163] In response to the first electrical signal, a first target FEC operation unit is determined from among the K FEC operation units, and the first target FEC operation unit is assigned to the first electrical signal;

[0164] The first electrical signal is input into the first target FEC processing unit for processing;

[0165] When the first target FEC operation unit finishes its operation, a second target FEC operation unit is determined from the currently available FEC operation units, and the second target FEC operation unit is assigned to the first electrical signal.

[0166] The first electrical signal, after being processed by the first target FEC processing unit, is input into the second target FEC processing unit for further processing, and the processing resources of the first target FEC processing unit are released.

[0167] In this embodiment, after receiving the first electrical signal, the DSP module first preempts the first target FEC operation unit among the K FEC operation units to perform the first-level FEC operation. After the first-level FEC operation is completed, it then preempts the second target FEC operation unit among the remaining available FEC operation units to perform the second-level FEC operation, and so on. The DSP module promptly releases the FEC operation units that have finished their operations for use by other electrical signals. In other words, the FEC operation units allocated to the first electrical signal are preempted step by step, rather than reserved. In this way, each electrical signal can preempt computing resources in real time based on its needs, which not only releases more redundant resources for flexible allocation to other electrical signals, but also avoids queuing due to reserved computing resources.

[0168] In specific implementation, such as Figure 5 As shown, when the first electrical signal is input into the first target FEC operation unit (first-level FEC operation unit), the first target FEC operation unit needs to determine whether the first electrical signal meets the FEC processing conditions. For example, it can determine whether the parameter values ​​of the first electrical signal, such as the pre-correction bit error rate and signal-to-noise ratio, meet the system performance requirements. If the system performance requirements are met, it indicates that the first electrical signal does not need to undergo FEC processing, and the first electrical signal can be configured to be output. If the system performance requirements are not met, it indicates that the first electrical signal needs to undergo FEC processing, and the first target FEC operation unit performs first-level FEC processing on the first electrical signal. After the first target FEC operation unit completes its processing, it then searches for the second target FEC operation unit (second-level FEC operation unit) and inputs the processed first electrical signal into the second target FEC operation unit, which then performs second-level FEC processing on the first electrical signal, and so on.

[0169] It should be noted that if two or more electrical signals preempt the same FEC operation unit, the electrical signal to be used in the FEC operation unit can be determined based on the order in which the electrical signals are received, the order in which the previous FEC operation ends, or the priority information of the electrical signals. The specific determination can be made according to the actual situation and is not limited here.

[0170] In this embodiment of the invention, for an OTN device board, the DSP module can determine a preset allocation rule and, upon receiving a first electrical signal, acquire the preset allocation rule to allocate, configure, and release FEC computing resources. Optionally, the DSP module further includes a control unit, which is electrically connected to K FEC computing units. The control unit can, in response to the first electrical signal, determine N first FEC computing units from among the K FEC computing units. That is, the DSP module can determine the preset allocation rule through the control unit to allocate, configure, and release FEC computing resources.

[0171] Alternatively, in a communication system, the OTN device board is typically connected to a network management device, which manages the OTN device board. Based on this, the DSP module can also interact with the network management device to obtain preset allocation rules to allocate, configure, and release FEC computing resources. Optionally, after receiving the first electrical signal, the DSP module further performs the following: in response to the first electrical signal, it sends a first request to the network management device, the first request carrying the first electrical signal, requesting the network management device to determine N first FEC computing units out of K FEC computing units, and sends first indication information to the device board to indicate the N first FEC computing units. Upon receiving the first indication information, the DSP module determines the N first FEC computing units according to the first indication information.

[0172] This invention also provides an FEC (Forward Error Correction) calculation method, which is applied to a digital signal processing (DSP) module on an OTN (Optical Network Telecommunications) equipment board. The OTN equipment board can be the same as the one provided in the above embodiments. The DSP module includes K forward error correction (FEC) calculation units, where K is a positive integer, and the DSP module is electrically connected to at least two optical interfaces.

[0173] See Figure 6 , Figure 6 This is a flowchart of an FEC calculation method provided in an embodiment of the present invention, such as... Figure 6 As shown, it includes the following steps:

[0174] Step 601: Receive at least one electrical signal, which is obtained by photoelectric conversion of the received optical signal by the optical interface.

[0175] Step 602: Based on K FEC operation units, perform FEC processing on each electrical signal.

[0176] Optionally, at least one electrical signal includes a first electrical signal; based on K FEC operation units, FEC processing is performed on each of the first electrical signals, including:

[0177] In response to the first electrical signal, N first FEC operation units are determined among the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units, where N is a positive integer and N≤K.

[0178] Optionally, in response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units, including:

[0179] In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are allocated to the first electrical signal;

[0180] Determine the operation order of the N first FEC operation units, and input the first electrical signal into the N first FEC operation units for processing according to the operation order;

[0181] N is determined based on the signal characteristic information of the first electrical signal.

[0182] Optionally, in response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are allocated to the first electrical signal, including:

[0183] In response to the first electrical signal, obtain the number N1 of the currently available FEC operation units among the K FEC operation units, where N1 is a positive integer;

[0184] If N1 < N, release the computing resources of the FEC computing units that have been allocated and whose operations have ended, and update the number of currently available FEC computing units to N2 based on the number of FEC computing units released, where N2 is a positive integer.

[0185] When N2≥N, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal.

[0186] Optionally, N is determined based on at least one of the pre-correction bit error rate and signal-to-noise ratio of the first electrical signal.

[0187] Optionally, in response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units, including:

[0188] In response to the first electrical signal, a first target FEC operation unit is determined among the K FEC operation units, and the first target FEC operation unit is assigned to the first electrical signal;

[0189] The first electrical signal is input into the first target FEC processing unit for processing;

[0190] When the first target FEC operation unit finishes its operation, a second target FEC operation unit is determined from the available FEC operation units, and the second target FEC operation unit is assigned to the first electrical signal.

[0191] The first electrical signal, after being processed by the first target FEC processing unit, is input into the second target FEC processing unit for further processing, and the processing resources of the first target FEC processing unit are released.

[0192] Optionally, in response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units, including:

[0193] In response to the first electrical signal, the priority information of the first electrical signal is obtained;

[0194] Based on priority information, N first FEC operation units are determined from among the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units.

[0195] Optionally, the device board is communicatively connected to the network management device; after receiving at least one electrical signal, the method further includes:

[0196] In response to the first electrical signal, a first request is sent to the network management device. The first request carries the first electrical signal and is used to request the network management device to determine N first FEC operation units among K FEC operation units, and to send first indication information to the device board to indicate the N first FEC operation units.

[0197] Receive the first instruction information and determine N first FEC operation units based on the first instruction information;

[0198] The first electrical signal is processed based on N first FEC operation units.

[0199] It should be noted that this embodiment is an implementation method corresponding to the DSP module in the above-mentioned OTN device single board embodiment. For the specific implementation method, please refer to the relevant description in the above-mentioned OTN device single board embodiment. To avoid repeated description, this embodiment will not repeat it.

[0200] Please see Figure 7 , Figure 7 This is an FEC processing device provided in an embodiment of the present invention.

[0201] like Figure 7 As shown, the FEC processing device 700 includes K FEC operation units, where K is a positive integer, and the FEC processing device 700 is electrically connected to at least two optical interfaces respectively.

[0202] The FEC processing unit 700 also includes:

[0203] The first receiving module 701 is used to receive at least one electrical signal, which is obtained by photoelectric conversion of the received optical signal by the optical interface.

[0204] The first processing module 702 is used to perform FEC processing on each of the first electrical signals based on the K FEC operation units.

[0205] Optionally, the at least one electrical signal includes a first electrical signal; the first processing module 702 is used for:

[0206] In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units, where N is a positive integer and N≤K.

[0207] Optionally, the first processing module 702 includes:

[0208] A first allocation unit is configured to, in response to the first electrical signal, determine N first FEC operation units from the K FEC operation units and allocate the N first FEC operation units to the first electrical signal;

[0209] The first processing unit is used to determine the operation order of the N first FEC operation units, and to input the first electrical signal into the N first FEC operation units for processing according to the operation order.

[0210] N is determined based on the signal characteristic information of the first electrical signal.

[0211] Optionally, the first allocation unit is used to:

[0212] In response to the first electrical signal, the number N1 of the currently available FEC operation units among the K FEC operation units is obtained, where N1 is a positive integer;

[0213] If N1 < N, release the computing resources of the FEC computing units that have been allocated and whose operations have ended, and update the number of currently available FEC computing units to N2 based on the number of FEC computing units released, where N2 is a positive integer.

[0214] When N2≥N, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal.

[0215] Optionally, N is determined based on at least one of the pre-correction bit error rate and signal-to-noise ratio of the first electrical signal.

[0216] Optionally, the first processing module 702 includes:

[0217] The second allocation unit is configured to, in response to the first electrical signal, determine a first target FEC operation unit among the K FEC operation units and allocate the first target FEC operation unit to the first electrical signal;

[0218] The second processing unit is used to input the first electrical signal into the first target FEC arithmetic unit for processing.

[0219] The third allocation unit is used to determine the second target FEC operation unit among the available FEC operation units when the first target FEC operation unit has finished its operation, and to allocate the second target FEC operation unit to the first electrical signal.

[0220] The third processing unit is used to input the first electrical signal processed by the first target FEC processing unit into the second target FEC processing unit for processing, and to release the processing resources of the first target FEC processing unit.

[0221] Optionally, the first processing module 702 includes:

[0222] The acquisition unit is used to acquire the priority information of the first electrical signal in response to the first electrical signal;

[0223] The fourth processing unit is configured to determine N first FEC operation units among the K FEC operation units according to the priority information, and process the first electrical signal based on the N first FEC operation units.

[0224] Optionally, the device board is communicatively connected to the network management device; the FEC processing unit 700 further includes:

[0225] The sending module is configured to respond to the first electrical signal and send a first request to the network management device. The first request carries the first electrical signal and is configured to request the network management device to determine N first FEC operation units among the K FEC operation units and send first indication information to the device board to indicate the N first FEC operation units.

[0226] The second receiving module is used to receive the first indication information and determine the N first FEC operation units based on the first indication information;

[0227] The second processing module is used to process the first electrical signal based on the N first FEC operation units.

[0228] The FEC processing unit 700 can achieve Figure 6 The various processes implemented in the method embodiments shown can achieve the same beneficial effects, and will not be described again here to avoid repetition.

[0229] This invention also provides a DSP chip that executes the various processes of the FEC operation method described above and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0230] This invention also provides an OTN device, including: a processor, a memory, and a program stored in the memory and executable on the processor. When the program is executed by the processor, it implements each process of the above-described FEC operation method and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0231] For details, see Figure 8 As shown, this embodiment of the invention also provides an OTN device, including a bus 801, a transceiver 802, an antenna 803, a bus interface 804, a processor 805, and a memory 806.

[0232] The transceiver 802 is used to: receive optical signals;

[0233] The processor 805 is used for:

[0234] The optical signal is converted into an electrical signal by photoelectric conversion.

[0235] Based on K FEC operation units, FEC processing is performed on each of the aforementioned electrical signals;

[0236] The electrical signals obtained after FEC processing are framed.

[0237] Optionally, the at least one electrical signal includes a first electrical signal; the processor 805 is used to:

[0238] In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units, where N is a positive integer and N≤K.

[0239] Optionally, the processor 805 is used for:

[0240] In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal;

[0241] The operation order of the N first FEC operation units is determined, and the first electrical signal is sequentially input into the N first FEC operation units for processing according to the operation order;

[0242] N is determined based on the signal characteristic information of the first electrical signal.

[0243] Optionally, the processor 805 is used for:

[0244] In response to the first electrical signal, the number N1 of the currently available FEC operation units among the K FEC operation units is obtained, where N1 is a positive integer;

[0245] If N1 < N, release the computing resources of the FEC computing units that have been allocated and whose operations have ended, and update the number of currently available FEC computing units to N2 based on the number of FEC computing units released, where N2 is a positive integer.

[0246] When N2≥N, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal.

[0247] Optionally, N is determined based on at least one of the pre-correction bit error rate and signal-to-noise ratio of the first electrical signal.

[0248] Optionally, the processor 805 is used for:

[0249] In response to the first electrical signal, a first target FEC operation unit is determined from the K FEC operation units, and the first target FEC operation unit is assigned to the first electrical signal;

[0250] The first electrical signal is input into the first target FEC processing unit for processing;

[0251] When the first target FEC operation unit finishes its operation, a second target FEC operation unit is determined from the available FEC operation units, and the second target FEC operation unit is assigned to the first electrical signal;

[0252] The first electrical signal, after being processed by the first target FEC processing unit, is input into the second target FEC processing unit for further processing, and the processing resources of the first target FEC processing unit are released.

[0253] Optionally, the processor 805 is used for:

[0254] In response to the first electrical signal, the priority information of the first electrical signal is obtained;

[0255] Based on the priority information, N first FEC operation units are determined among the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units.

[0256] Optionally, the device board is communicatively connected to the network management device; the transceiver 802 is further used for:

[0257] In response to the first electrical signal, a first request is sent to the network management device. The first request carries the first electrical signal and is used to request the network management device to determine N first FEC operation units among the K FEC operation units, and to send first indication information to the device board to indicate the N first FEC operation units.

[0258] Receive the first instruction information and determine the N first FEC operation units based on the first instruction information;

[0259] The processor 805 is used for:

[0260] The first electrical signal is processed based on the N first FEC operation units.

[0261] exist Figure 8 In this document, a bus architecture (represented by bus 801) is used. Bus 801 can include any number of interconnected buses and bridges, linking various circuits including one or more processors 805 (represented by processor 805) and memory 806 (represented by memory 806). Bus 801 can also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. Bus interface 804 provides an interface between bus 801 and transceiver 802. Transceiver 802 can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by processor 805 is transmitted over a wireless medium via antenna 803, which further receives data and transmits it to processor 805.

[0262] The processor 805 manages the bus 801 and handles general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. The memory 806 can be used to store data used by the processor 805 during operation.

[0263] Optionally, the processor 805 can be a CPU, ASIC, FPGA, or CPLD.

[0264] This invention also provides a computer-readable storage medium storing a computer program. When executed by a processor, this computer program implements the various processes of the above-described FEC operation method embodiments and achieves the same technical effects. To avoid repetition, it will not be described again here. The computer-readable storage medium may be, for example, ROM, RAM, a magnetic disk, or an optical disk.

[0265] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0266] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0267] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. A single board for an optical transport network (OTN) device, characterized in that, The device board includes: At least two optical interfaces, each of which is used to receive optical signals and perform photoelectric conversion on the optical signals to obtain electrical signals; A digital signal processing (DSP) module is electrically connected to the at least two optical interfaces respectively. The DSP module includes K forward error correction (FEC) operation units, where K is a positive integer, and the K FEC operation units form an FEC operation resource pool. The DSP module is used to perform FEC processing on each of the electrical signals based on the K FEC operation units when receiving at least one of the electrical signals transmitted by the at least two optical interfaces. At least two framing units are provided, each of which is electrically connected to the DSP module. Each framing unit is used to perform framing processing on the electrical signals sent by the DSP module. At least one of the electrical signals includes a first electrical signal; the DSP module is used for: Receive the first electrical signal; In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units, where N is a positive integer and N≤K.

2. The equipment board according to claim 1, characterized in that, The DSP module is used for: In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal; The operation order of the N first FEC operation units is determined, and the first electrical signal is sequentially input into the N first FEC operation units for processing according to the operation order; N is determined based on the signal characteristic information of the first electrical signal.

3. The equipment board according to claim 2, characterized in that, The DSP module is used for: In response to the first electrical signal, the number N1 of the currently available FEC operation units among the K FEC operation units is obtained, where N1 is a positive integer; If N1 < N, release the computing resources of the FEC computing units that have been allocated and whose operations have ended, and update the number of currently available FEC computing units to N2 based on the number of FEC computing units released, where N2 is a positive integer. When N2≥N, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal.

4. The equipment board according to claim 2 or 3, characterized in that, N is determined based on at least one of the pre-correction bit error rate and signal-to-noise ratio of the first electrical signal.

5. The equipment board according to claim 1, characterized in that, The DSP module is used for: In response to the first electrical signal, a first target FEC operation unit is determined from the K FEC operation units, and the first target FEC operation unit is assigned to the first electrical signal; The first electrical signal is input into the first target FEC processing unit for processing; When the first target FEC operation unit finishes its operation, a second target FEC operation unit is determined from the currently available FEC operation units, and the second target FEC operation unit is assigned to the first electrical signal; The first electrical signal, after being processed by the first target FEC processing unit, is input into the second target FEC processing unit for further processing, and the processing resources of the first target FEC processing unit are released.

6. The equipment board according to claim 1, characterized in that, The DSP module is used for: In response to the first electrical signal, the priority information of the first electrical signal is obtained; Based on the priority information, N first FEC operation units are determined among the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units.

7. The equipment board according to claim 1, characterized in that, The DSP module further includes a control unit, which is electrically connected to the K FEC operation units respectively. The control unit is used to respond to the first electrical signal, determine N first FEC operation units among the K FEC operation units, and process the first electrical signal based on the N first FEC operation units.

8. The equipment board according to claim 1, characterized in that, The device board is communicatively connected to the network management device; the DSP module is also used for: In response to the first electrical signal, a first request is sent to the network management device. The first request carries the first electrical signal and is used to request the network management device to determine N first FEC operation units among the K FEC operation units, and to send first indication information to the device board to indicate the N first FEC operation units. Receive the first instruction information and determine the N first FEC operation units based on the first instruction information; The first electrical signal is processed based on the N first FEC operation units.

9. A forward error correction (FEC) operation method, characterized in that, The method is applied to a DSP module on a single board of an OTN (Optical Transport Network) device. The DSP module includes K FEC (Flexible Encoding and Computation) units, where K is a positive integer. The K FEC units form an FEC computing resource pool. The DSP module is electrically connected to at least two optical interfaces. The method includes: Receive at least one electrical signal, which is obtained by photoelectric conversion of the received optical signal by the optical interface; Based on the K FEC operation units, FEC processing is performed on each of the electrical signals; The at least one electrical signal includes a first electrical signal; the step of performing FEC processing on each of the K FEC operation units includes: In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units, where N is a positive integer and N≤K.

10. The method according to claim 9, characterized in that, In response to the first electrical signal, determining N first FEC operation units from the K FEC operation units and processing the first electrical signal based on the N first FEC operation units includes: In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal; The operation order of the N first FEC operation units is determined, and the first electrical signal is sequentially input into the N first FEC operation units for processing according to the operation order; N is determined based on the signal characteristic information of the first electrical signal.

11. The method according to claim 10, characterized in that, The step of determining N first FEC operation units from the K FEC operation units in response to the first electrical signal and allocating the N first FEC operation units to the first electrical signal includes: In response to the first electrical signal, the number N1 of the currently available FEC operation units among the K FEC operation units is obtained, where N1 is a positive integer; If N1 < N, release the computing resources of the FEC computing units that have been allocated and whose operations have ended, and update the number of currently available FEC computing units to N2 based on the number of FEC computing units released, where N2 is a positive integer. When N2≥N, N first FEC operation units are determined from the K FEC operation units, and the N first FEC operation units are assigned to the first electrical signal.

12. The method according to claim 10 or 11, characterized in that, N is determined based on at least one of the pre-correction bit error rate and signal-to-noise ratio of the first electrical signal.

13. The method according to claim 9, characterized in that, In response to the first electrical signal, determining N first FEC operation units from the K FEC operation units and processing the first electrical signal based on the N first FEC operation units includes: In response to the first electrical signal, a first target FEC operation unit is determined from the K FEC operation units, and the first target FEC operation unit is assigned to the first electrical signal; The first electrical signal is input into the first target FEC processing unit for processing; When the first target FEC operation unit finishes its operation, a second target FEC operation unit is determined from the available FEC operation units, and the second target FEC operation unit is assigned to the first electrical signal; The first electrical signal, after being processed by the first target FEC processing unit, is input into the second target FEC processing unit for further processing, and the processing resources of the first target FEC processing unit are released.

14. The method according to claim 9, characterized in that, In response to the first electrical signal, determining N first FEC operation units from the K FEC operation units and processing the first electrical signal based on the N first FEC operation units includes: In response to the first electrical signal, the priority information of the first electrical signal is obtained; Based on the priority information, N first FEC operation units are determined among the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units.

15. The method according to claim 9, characterized in that, The device board is communicatively connected to the network management device; after receiving at least one electrical signal, the method further includes: In response to the first electrical signal, a first request is sent to the network management device. The first request carries the first electrical signal and is used to request the network management device to determine N first FEC operation units among the K FEC operation units, and to send first indication information to the device board to indicate the N first FEC operation units. Receive the first instruction information and determine the N first FEC operation units based on the first instruction information; The first electrical signal is processed based on the N first FEC operation units.

16. A forward error correction (FEC) computing device, characterized in that, The device includes K FEC operation units, where K is a positive integer. The K FEC operation units are integrated on a DSP module, and the K FEC operation units form an FEC operation resource pool. The device is electrically connected to at least two optical interfaces respectively; The device further includes: The first receiving module is used to receive at least one electrical signal, which is obtained by photoelectric conversion of the received optical signal by the optical interface. The first processing module is used to perform FEC processing on each of the electrical signals based on the K FEC operation units; The at least one electrical signal includes a first electrical signal; the first processing module is further configured to: In response to the first electrical signal, N first FEC operation units are determined from the K FEC operation units, and the first electrical signal is processed based on the N first FEC operation units, where N is a positive integer and N≤K.

17. A digital signal processing (DSP) chip, characterized in that, Perform the steps of the forward error correction (FEC) operation method as described in any one of claims 9-15.

18. An optical transport network (OTN) device, characterized in that, include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the forward error correction (FEC) operation method as described in any one of claims 9-15.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the forward error correction (FEC) operation method as described in any one of claims 9-15.

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