A hybrid lossless transmission method and device based on video fiber seat

Abstract

The application discloses a hybrid lossless transmission method and device based on a video optical fiber seat, wherein first video source signals or second video source information are received, separated and losslessly encoded, and then sent to first video exchange cards, so that the first video exchange cards or second video exchange cards are subjected to serial-to-parallel conversion and parallel-to-serial conversion processing, high-speed serial data is sent to a switching chip, the switching chip sends the high-speed serial data to any one of the first video exchange cards or any one of the second video exchange cards, the first video exchange cards or the second video exchange cards send the high-speed serial data to first video receiving boxes or second video receiving boxes for decoding, and then video display is realized. Through the above method, hybrid lossless and uncompressed transmission is realized under different video formats, and the quality of the video is ensured.

Description

Technical Field

[0001] This invention relates to the field of video fiber optic workstation technology, and in particular to a hybrid lossless transmission method and apparatus based on video fiber optic workstations. Background Technology

[0002] In video fiber optic console technology, video signals are transmitted via optical fiber to ensure signal quality and transmission distance. The high bandwidth of optical fiber supports high-definition video transmission. Simultaneously, the low latency and stability of optical fiber communication meet the needs of real-time video communication. A video fiber optic console system consists of multiple video transmitter boxes, multiple video receiver boxes, multiple video switching cards, and a switching host. The video transmitter boxes connect to the video source, encode and decode the input video signal, and then send it through optical fiber to the video switching card. The video switching card sends the received fiber optic video signal to the switching chip in the switching host. Simultaneously, the switching chip can forward video signals from any video switching card to any other video switching card. The video switching card then sends the received video signal through optical fiber to the video receiver box. The video receiver box decodes the fiber optic video signal and sends the video stream to the display device. Video fiber optic console technology is widely used in security monitoring, command and dispatch centers, video conferencing, remote transmission, and other video-related fields. Most modern video fiber optic consoles support various common video interfaces, such as HDMI, DVI, and VGA, enabling them to receive various types of video signals.

[0003] With societal advancements, traditional fiber optic video workstations, which only support RGB 24-bit (8 bits for R, 8 bits for G, and 8 bits for B in RGB color components) transmission, can no longer meet the demands for video quality. A common video resolution is 1920x1080@60. When the input video format is RGB 24-bit (8 bits for R, 8 bits for G, and 8 bits for B in RGB color components), the video bandwidth is 1920 * 1080 * 60 * 24 bits = 2.98 Gbit / s. A single-channel 3.125 Gbps switching chip can meet this bandwidth requirement. However, if a higher video format is desired, the current single-channel switching chip cannot meet the bandwidth demands. Replacing it with a single-channel switching chip supporting higher speeds would significantly increase costs. Summary of the Invention

[0004] To address the aforementioned technical problems, embodiments of the present invention provide a hybrid lossless transmission method and apparatus based on video fiber optic seats, which enables hybrid lossless and uncompressed transmission under different video formats, ensuring video quality.

[0005] A first aspect of this invention provides a hybrid lossless transmission method based on video fiber optic workstations, the method comprising:

[0006] The system receives a first video source signal, separates and losslessly encodes it, and then sends it to a first video switching card at a first preset high-speed serial rate. The first video switching card performs serial-to-parallel and parallel-to-serial conversions to split one high-speed serial data stream at the first preset high-speed serial rate into two high-speed serial data streams at the second preset high-speed serial rate. These two high-speed serial data streams are then sent to a switching chip. The switching chip can then send either the two high-speed serial data streams at the second preset high-speed serial rate to any one of the first video switching cards, or send either the first high-speed serial data stream at the second preset high-speed serial rate to any one of the second video switching cards. The first video switching card then sends the high-speed serial data to the first video receiving box for decoding, thereby enabling video display.

[0007] The system receives a second video source signal, separates and losslessly encodes it, and then sends it to a second video switching card at a second preset high-speed serial rate. This causes the second video switching card to send high-speed serial data at the second preset high-speed serial rate to a switching chip. The switching chip then sends this high-speed serial data at the second preset high-speed serial rate to any second video switching card, or to the first channel of high-speed serial data at the second preset high-speed serial rate in any first video switching card. Finally, the second video switching card sends the high-speed serial data to a second video receiving box for decoding, thus enabling video display.

[0008] In one possible implementation of the first aspect, separating the first video source signal includes:

[0009] The first video source signal is separated into RGB components, each of which is one-third the bit depth of the first video source signal.

[0010] In one possible implementation of the first aspect, lossless encoding of the first video source signal includes:

[0011] Using the 32-bit register in the field programmable gate array, represented by REG[31:0], the high 8 bits of R[11:4], G[11:4], and B[11:4] of each pair of pixels in the first video source signal are stored in the low 16 bits of REG for three clock cycles.

[0012] Store the lower 4 bits of the RGB components of each pair of pixels (R[3:0], G[3:0], B[3:0]) using REG[23:16] for three clock cycles, and set the remaining bits of the pixel REG[31:24] to zero.

[0013] In one possible implementation of the first aspect, the method of enabling the first video switching card to send high-speed serial data to the first video receiving box for decoding and then displaying the video includes:

[0014] If the first video switching card receives two channels of high-speed serial data at the second preset high-speed serial rate, then the first video switching card merges the two channels of high-speed serial data at the second preset high-speed serial rate into one channel of high-speed serial data at the first preset high-speed serial rate and sends it to the first video receiving box, so that the first video receiving box decodes the high-speed serial data and sends it to the first video display device to realize video display.

[0015] If the first video switching card receives high-speed serial data at a first preset high-speed serial rate, then the first video switching card sends the high-speed serial data at the first preset high-speed serial rate to the first video receiving box, so that the first video receiving box decodes the high-speed serial data and sends it to the first video display device to realize video display.

[0016] In one possible implementation of the first aspect, separating the second video source signal includes:

[0017] The second video source signal is separated into RGB components, each with one-third the bit depth of the second video source signal.

[0018] In one possible implementation of the first aspect, the second video source signal is losslessly encoded, including:

[0019] Using a 36-bit register in a field-programmable gate array (FPGA) and represented by REG[15:0], the R[7:0], G[7:0], and B[7:0] of each pair of pixels in the second video source signal are stored in a 16-bit REG for three clock cycles.

[0020] A second aspect of the present invention provides a hybrid lossless transmission device based on a video fiber optic workstation, the device comprising:

[0021] The first processing module is used to receive the first video source signal, separate and losslessly encode the first video source signal, and send it to the first video switching card at a first preset high-speed serial rate. The first video switching card performs serial-to-parallel and parallel-to-serial conversion processes to split one high-speed serial data at the first preset high-speed serial rate into two high-speed serial data at the second preset high-speed serial rate, and send them to the switching chip. The switching chip can then send the two high-speed serial data at the second preset high-speed serial rate to any one of the first video switching cards, or send the first of the two high-speed serial data at the second preset high-speed serial rate to any one of the second video switching cards. The first video switching card then sends the high-speed serial data to the first video receiving box for decoding to achieve video display.

[0022] The second processing module receives the second video source signal, separates and losslessly encodes it, and then sends it to the second video switching card at a second preset high-speed serial rate. This causes the second video switching card to send high-speed serial data at the second preset high-speed serial rate to the switching chip. The switching chip then sends the high-speed serial data at the second preset high-speed serial rate to any one of the second video switching cards, or to the first channel of high-speed serial data at the second preset high-speed serial rate in any one of the first video switching cards. Finally, the second video switching card sends the high-speed serial data to the second video receiving box for decoding, thereby enabling video display.

[0023] In one possible implementation of the second aspect, separating the first video source signal includes:

[0024] The first video source signal is separated into RGB components, each of which is one-third the bit depth of the first video source signal.

[0025] A third aspect of the present invention provides a computing device, comprising:

[0026] Memory, used to store computer programs;

[0027] A processor is configured to implement the hybrid lossless transmission method based on video fiber optic seats as described in the first aspect when executing the computer program.

[0028] A fourth aspect of the present invention provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the hybrid lossless transmission method based on video fiber optic seats as described in the first aspect.

[0029] The present invention provides a method for receiving a first video source signal, separating and losslessly encoding the first video source signal, and then sending it to a first video switching card at a first preset high-speed serial rate. The first video switching card performs serial-to-parallel and parallel-to-serial conversion processes, splitting one channel of high-speed serial data at the first preset high-speed serial rate into two channels of high-speed serial data at a second preset high-speed serial rate, and sending them to a switching chip. The switching chip can then send either the two channels of high-speed serial data at the second preset high-speed serial rate to any one of the first video switching cards, or send the first channel of high-speed serial data at the second preset high-speed serial rate to any one of the second video switching cards. The first video switching card then sends the high-speed serial data to a first video receiving box for decoding, thereby achieving video display. The system receives a second video source signal, separates and losslessly encodes it, and then sends it to a second video switching card at a second preset high-speed serial rate. This causes the second video switching card to send high-speed serial data at the second preset high-speed serial rate to a switching chip. The switching chip then sends this high-speed serial data at the second preset high-speed serial rate to any second video switching card, or to the first channel of high-speed serial data at the second preset high-speed serial rate in any first video switching card. The second video switching card then sends the high-speed serial data to a second video receiving box for decoding, thus enabling video display. This method achieves lossless and uncompressed transmission of different video formats, ensuring video quality. Attached Figure Description

[0030] Figure 1 : A schematic diagram of the overall hardware device connection relationship of an embodiment of the hybrid lossless transmission method based on video fiber optic seats provided by the present invention;

[0031] Figure 2 : A video switching processing device diagram of an embodiment of the hybrid lossless transmission method based on video fiber optic seats provided by the present invention;

[0032] Figure 3 : A structural diagram of a 36-bit video transmitter box according to an embodiment of the hybrid lossless transmission method based on video fiber optic seats provided by the present invention;

[0033] Figure 4 : A structural diagram of a 36-bit video switching card according to an embodiment of the hybrid lossless transmission method based on video fiber optic seats provided by the present invention;

[0034] Figure 5 : A structural diagram of a 36-bit video receiver box according to an embodiment of the hybrid lossless transmission method based on video fiber optic seats provided by the present invention;

[0035] Figure 6: A structural diagram of a 36-bit video transmitter box according to an embodiment of the hybrid lossless transmission method based on video fiber optic seats provided by the present invention;

[0036] Figure 7 : A structural diagram of a 24-bit video transmitter box according to an embodiment of the hybrid lossless transmission method based on video fiber optic seats provided by the present invention;

[0037] Figure 8 : A structural diagram of a 24-bit video receiver box according to an embodiment of the hybrid lossless transmission method based on video fiber optic seats provided by the present invention;

[0038] Figure 9 : A structural diagram of a 24-bit video switching card according to an embodiment of the hybrid lossless transmission method based on video fiber optic seats provided by the present invention;

[0039] Figure 10 : A device structure block diagram of an embodiment of the hybrid lossless transmission method based on video fiber optic seats provided by the present invention. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0042] Please refer to Figure 1 This is a flowchart illustrating an embodiment of the hybrid lossless transmission method based on video fiber optic seats provided by the present invention, including steps S101 to S102.

[0043] S101. Receive the first video source signal, separate and losslessly encode the first video source signal, and send it to the first video switching card at a first preset high-speed serial rate. The first video switching card performs serial-to-parallel and parallel-to-serial conversion processes to split one channel of high-speed serial data at the first preset high-speed serial rate into two channels of high-speed serial data at the second preset high-speed serial rate, and send them to the switching chip. The switching chip then sends the two channels of high-speed serial data at the second preset high-speed serial rate to any one of the first video switching cards, or sends the first channel of the two channels at the second preset high-speed serial rate to any one of the second video switching cards. The first video switching card then sends the high-speed serial data to the first video receiving box for decoding to achieve video display, or the second video switching card sends the high-speed serial data to the second video receiving box for decoding to achieve video display.

[0044] It is worth noting that the first video source signal refers to a high-bit video signal source, such as a 36-bit video source signal; the first preset high-speed serial rate is a high-speed serial rate, such as 6.25Gb / s; the first video switching card is a video switching card with the corresponding bit depth of the first video source signal, such as a 36-bit video switching card; the second preset high-speed serial rate is a low-speed serial rate, such as 3.125Gb / s; the second video switching card is a video switching card with the corresponding bit depth of the second video source signal, such as a 24-bit video switching card; and the second video source signal is a low-bit video signal source, such as a 24-bit video source signal.

[0045] It is worth noting that the first video source signal and the second video source signal include, but are not limited to, 8-bit, 16-bit, 24-bit, and 32-bit video source signals.

[0046] In this embodiment, as Figure 2 As shown, Figure 2The diagram shows the overall device connection. During data transmission, the 36-bit video transmitter receives a 36-bit video source signal, performs lossless encoding on the 36-bit video signal, and then transmits the data to the 36-bit video switching card via an optical module and fiber optic cable at a high-speed serial rate of 6.25Gb / s. The 36-bit video switching card splits the 6.25Gb / s high-speed serial data from one channel into two 3.125Gb / s high-speed serial data channels to the switching chip after serial-to-parallel and parallel-to-serial conversion. The first channel transmits the high 8 bits of each RGB component, totaling 24 bits; the second channel transmits the 4th bit of each RGB component, totaling 12 bits. The specific processing of serial-to-parallel and parallel-to-serial conversion is as follows: After encoding the 36-bit itRGB video data into 32-bit data REG[31:0], REG[31:0] is sent to the high-speed transceiver built into the FPGA. The high-speed transceiver will send the 32-bit REG[31:0] parallel data from low bit to high bit in order to the optical module at a rate of 6.25Gb / s, that is, first send REG[0], REG[1]... and finally send REG

[31] , realizing the 32-bit parallel to 6.25Gb / s serial differential data transmission. The parallel to serial conversion is the opposite. The high-speed transceiver built into the field programmable gate array receives 6.25Gb / s serial differential data, registers the first received serial data to REG[0], the second received serial data to REG[1], and the last serial data to REG

[31] . After receiving 32 serial data, the 32-bit parallel data REG[31:0] is obtained.

[0047] Then, the switching chip forwards the two 3.125Gb / s high-speed serial data streams to any 36-bit video switching card, or forwards the first of the two 3.125Gb / s high-speed serial data streams (containing the high 8 bits of each RGB component, for a total of 24 bits) to any 24-bit video switching card. The 36-bit switching card sends the high-speed serial data to the 36-bit video receiving box via an optical module and fiber optic cable. The 36-bit video receiving box decodes the high-speed serial data and sends the video data to a 36-bit video display device for video display.

[0048] It should be noted that the 36-bit video switching card can receive two channels of 3.125Gb / s high-speed serial data from other 36-bit video switching cards through the switching chip, or receive one channel of 3.125Gb / s high-speed serial data from other 24-bit video switching cards through the switching chip.

[0049] like Figure 3As shown, the switching chip in the video switching equipment uses the MACOM M21170 chip. This chip supports a 288x288 switching matrix with a maximum speed of 3.125Gb / s. Since each video switching card in this system has four 3.125Gb / s high-speed signals connected to the switching chip, the system can connect up to 72 video switching cards. Through the transceiver connection between the video switching cards and the switching chip, up to 72 switching cards can communicate with each other, enabling a total of 288 high-speed signals.

[0050] like Figure 4 As shown, the field-programmable gate array (FPGA) chip in the 36-bit video transmitter box uses Xilinx's XC7A50T, which supports high-speed serial transceivers up to 6.25Gb / s. After the transmitter box is powered on, the FPGA loads the FPGA program through the flash (used to store the FPGA program) chip: After receiving the video data output from the 36-bit video source, the FPGA separates and losslessly encodes each RGB 36-bit (R occupies 12 bits, G occupies 12 bits, and B occupies 12 bits) pixel of the video data.

[0051] In some embodiments, step S101, "separating the first video source signal", includes, but is not limited to, the following steps:

[0052] The first video source signal is separated into RGB components, each of which is one-third the bit depth of the first video source signal.

[0053] Specifically, the RGB36bit is separated into 12-bit components of each RGB, which are represented by R[11:0], G[11:0], and B[11:0] respectively. If RGB36bit = 0x012_345_678, then R[11:0] = 0x012, G[11:0] = 0x345, and B[11:0] = 0x678.

[0054] In some embodiments, step S101, "performing lossless encoding of the first video source signal," includes, but is not limited to, the following steps:

[0055] Using the 32-bit register in the field programmable gate array, represented by REG[31:0], the high 8 bits of R[11:4], G[11:4], and B[11:4] of each pair of pixels in the first video source signal are stored in the low 16 bits of REG for three clock cycles.

[0056] Store the lower 4 bits of the RGB components of each pair of pixels (R[3:0], G[3:0], B[3:0]) using REG[23:16] for three clock cycles, and set the remaining bits of the pixel REG[31:24] to zero.

[0057] Specifically, the field-programmable gate array (FPGA) internally generates a 32-bit register, represented by REG[31:0]. The high 8 bits (R[11:4], G[11:4], B[11:4]) of each pair of pixel RGB components are stored in the low 16 bits (REG[15:0]) over three clock cycles; the low 4 bits (R[3:0], G[3:0], B[3:0]) of each pair of pixel RGB components are stored in REG[23:16] over three clock cycles; the remaining bits (31:24) of REG are set to zero. For example, if the first 36-bit pixel value is 0x012_345_678 and the second 36-bit pixel value is 0x9ab_cde_f01, then the REG[31:0] encoding values ​​for the three cycles are 0x002b019a, 0x005e34cd, and 0x008167f0, respectively. Finally, this 32-bit encoded data is sent to the FPGA's built-in high-speed transceiver. This high-speed transceiver converts parallel data into 6.25Gb / s serial data and sends it to the optical module. The purpose of this encoding sorting method is to place the high 8 bits of each 12-bit component of the RGB 36-bit system (i.e., the RGB 24-bit system) in the low 16 bits of the encoded data, and the low 4 bits of each 12-bit component in the high 16 bits of the encoded data, thus making the 36-bit system compatible with 24-bit video switching cards.

[0058] It should be noted that FPGA stands for Field Programmable Gate Array.

[0059] In some embodiments, step S101, "the first video switching card sends high-speed serial data to the first video receiving box for decoding," includes, but is not limited to, the following steps:

[0060] If the first video switching card receives two channels of high-speed serial data at the second preset high-speed serial rate, then the first video switching card merges the two channels of high-speed serial data at the second preset high-speed serial rate into one channel of high-speed serial data at the first preset high-speed serial rate and sends it to the first video receiving box, so that the first video receiving box decodes the high-speed serial data and sends it to the first video display device to realize video display.

[0061] If the first video switching card receives high-speed serial data at a first preset high-speed serial rate, then the first video switching card sends the high-speed serial data at the first preset high-speed serial rate to the first video receiving box, so that the first video receiving box decodes the high-speed serial data and sends it to the first video display device to realize video display.

[0062] Specifically, the 36-bit switching card merges two 3.125Gb / s high-speed serial data streams into one 6.25Gb / s high-speed serial data stream, which is then transmitted to the 36-bit video receiving box via an optical module and fiber optic cable. The 36-bit video receiving box decodes the 6.25Gb / s high-speed serial data and sends the video data to the 36-bit video display device for video display.

[0063] It should be noted that, as Figure 5 As shown, the 36-bit video switching card uses Xilinx's XC7A200T field-programmable gate array chip, which supports high-speed serial transceivers up to 6.25Gb / s. After the transmitter box is powered on, the FPGA loads the FPGA program through the flash (used to store the FPGA program) chip: The FPGA receives the 6.25Gb / s signal from the optical module and obtains 32-bit encoded data REG[31:0]. The 32-bit encoded data is divided into two 16-bit data channels and registered using REG1[15:0] and REG2[15:0]. REG1[15:0] registers the lower 16 bits of REG, i.e., REG[15:0] (containing the higher 8 bits of each component of REG36, i.e., RGB24bit), which is the first data channel. REG2[15:0] registers the higher 16 bits of REG, i.e., REG[31:16] (containing the lower 4 bits of each component of REG36), which is the second data channel. The two 16-bit parallel data streams are converted into two 3.125Gb / s serial data streams and transmitted to the switching chip, realizing the conversion of one 6.25Gb / s stream to two 3.125Gb / s streams to the switching chip.

[0064] The 36-bit video switching card simultaneously receives two 3.125Gb / s high-speed serial signals from the switching chip. These can be two 3.125Gb / s data signals from other RGB 36-bit video switching cards, or one 3.125Gb / s data signal from other RGB 24-bit video switching cards, achieving RGB 24-bit and RGB 36-bit transmission compatibility. It converts the two 3.125Gb / s high-speed serial signals (from other RGB 36-bit switching cards) into two 16-bit parallel data signals, or converts one 3.125Gb / s high-speed serial signal (from other RGB 24-bit switching cards) into one 16-bit parallel data signal and generates a 16-bit all-zero data signal as the second parallel data signal. After obtaining two 16-bit parallel data streams, the first 16-bit parallel data stream is concatenated in REG3[15:0], and the second 16-bit parallel data stream is concatenated in REG3[31:16]. The two 16-bit parallel data streams are concatenated into a single 32-bit REG3[31:0] stream, which is then converted into a single 6.25Gb / s serial data stream and sent to the optical module.

[0065] like Figure 6 As shown, the 36-bit video receiver uses Xilinx's XC7A50T field-programmable gate array chip, which supports high-speed serial transceivers up to 6.25Gb / s. After the transmitter box is powered on, the FPGA loads the FPGA program through the flash (used to store the FPGA program) chip: The FPGA receives the 6.25Gb / s signal from the optical module, and after serial-to-parallel conversion, obtains 32-bit REG[31:0]. The REG[31:0] is decoded: every three REG cycles of data can yield two RGB 36-bit pixel data. For example, if the three REG cycles are 0x002b019a, 0x005e34cd, 0x008167f0, then the first 36-bit pixel value can be decoded as 0x012_345_678, and the second 36-bit pixel value as 0x9ab_cde_f01. After decoding, the data is finally output to a 36-bit display device.

[0066] S102. Receive the second video source signal, separate and losslessly encode the second video source signal, and send it to the second video switching card at a second preset high-speed serial rate. This causes the second video switching card to send high-speed serial data at the second preset high-speed serial rate to the switching chip. The switching chip then sends the high-speed serial data at the second preset high-speed serial rate to any one of the second video switching cards, or sends the high-speed serial data at the second preset high-speed serial rate to the first channel of high-speed serial data at the second preset high-speed serial rate in any one of the first video switching cards. This allows the second video switching card to send the high-speed serial data to the second video receiving box for decoding, thereby achieving video display.

[0067] In this embodiment, the 24-bit video transmitter receives a 24-bit video source signal, performs lossless encoding on the 24-bit video signal, and then transmits the data at a high-speed serial rate of 3.125Gb / s through an optical module and optical fiber to the 24-bit video switching card. The 24-bit video switching card then forwards the 3.125Gb / s high-speed serial data received by the optical module to the switching chip.

[0068] The switching chip can forward the 3.125Gb / s high-speed serial data to any 24-bit video switching card, or forward the first channel of 3.125Gb / s high-speed serial data to any 36-bit video switching card. The 24-bit video switching card can receive 3.125Gb / s high-speed serial data from other 24-bit video switching cards via the switching chip, or receive the first channel of 3.125Gb / s high-speed serial data from other 36-bit video switching cards via the switching chip. The 24-bit switching card transparently transmits the 3.125Gb / s high-speed serial data from the switching chip through the optical module and fiber optic cable to the 24-bit video receiving box. The 24-bit video receiving box decodes the 3.125Gb / s high-speed serial data and sends the video data to the 24-bit video display device for video display.

[0069] It should be noted that, as Figure 7 As shown, the field-programmable gate array (FPGA) chip in the 24-bit video transmitter box uses Xilinx's XC7A50T, which supports a high-speed serial transceiver of 3.125Gb / s. After the transmitter box is powered on, the FPGA loads the FPGA program through the flash (used to store the FPGA program) chip: After the FPGA receives the video data output from the 24-bit video source, it separates and performs lossless encoding on each RGB24-bit (8 bits for R, 8 bits for G, and 8 bits for B) pixel of the video data.

[0070] like Figure 8 As shown, the 24-bit video receiver uses Xilinx's XC7A50T field-programmable gate array (FPGA) chip, which supports a high-speed serial transceiver of 3.125Gb / s. After the receiver is powered on, the FPGA loads the FPGA program through the flash (used to store the FPGA program) chip. The FPGA receives the 3.125Gb / s signal from the optical module, and after serial-to-parallel conversion, obtains 16-bit REG[15:0]. The REG[15:0] is decoded: every three REG cycles yield two RGB 24-bit pixel data. For example, if the three REG cycles are 0x019a, 0x34cd, and 0x67f0, the first 24-bit pixel value can be decoded as 0x01_34_67, and the second 24-bit pixel value as 0x9a_cd_f0. After decoding, the data is finally output to a 24-bit display device.

[0071] In some embodiments, step S102, "separating the second video source signal," includes, but is not limited to, the following steps:

[0072] The second video source signal is separated into RGB components, each with one-third the bit depth of the second video source signal.

[0073] Specifically, the RGB24-bit is separated into 8-bit components for each of the RGB values, represented by R[7:0], G[7:0], and B[7:0] respectively. If RGB24-bit = 0x01_34_67, then R[7:0] = 0x01, G[7:0] = 0x34, and B[7:0] = 0x67.

[0074] In some embodiments, step S102, "performing lossless encoding of the second video source signal", includes, but is not limited to, the following steps:

[0075] Using a 36-bit register in a field-programmable gate array (FPGA) and represented by REG[15:0], the R[7:0], G[7:0], and B[7:0] of each pair of pixels in the second video source signal are stored in a 16-bit REG for three clock cycles.

[0076] Specifically, the field-programmable gate array (FPGA) internally generates a 16-bit register, represented by REG[15:0]. The R[7:0], G[7:0], and B[7:0] components of each pair of pixels' RGB elements are stored in a 16-bit REG array, i.e., REG[15:0], over three clock cycles. For example, if the first 24-bit pixel value is 0x01_34_67 and the second 24-bit pixel value is 0x9a_cd_f0, then the REG[15:0] encoded values ​​for the three cycles are 0x019a, 0x34cd, and 0x67f0, respectively. Finally, this 16-bit encoded data is sent to the FPGA's built-in high-speed transceiver, which converts the parallel data into 3.125Gb / s serial data and sends it to the optical module. This encoding and sorting method aims to allow 8 bits of each RGB 24-bit component to be transmitted via a single 3.125Gb / s stream, ensuring compatibility between 36-bit and 24-bit video switching cards.

[0077] The 24-bit video switching card uses Xilinx's XC7A200T field-programmable gate array chip, which supports a high-speed serial transceiver of 3.125Gb / s. After the 24-bit video transmitter box is powered on, the FPGA in the 24-bit video transmitter box loads the FPGA program through the flash (used to store the FPGA program) chip. The FPGA receives the 3.125Gb / s signal from the optical module and directly transmits the 3.125Gb / s high-speed serial data to the switching chip.

[0078] like Figure 9As shown, the 24-bit video switching card simultaneously receives a 3.125Gb / s high-speed serial signal sent by the switching chip. This signal can be 3.125Gb / s data from other RGB24-bit video switching cards, or it can be the first 3.125Gb / s data from other RGB36-bit video switching cards. Since the first 3.125Gb / s link of other RGB36-bit video switching cards transmits the high 8 bits of each component (i.e., RGB24-bit), RGB24-bit and RGB36-bit transmission compatibility is achieved. The signal is then transparently transmitted and forwarded to the optical module.

[0079] The above method achieves support for both RGB24-bit video format transmission at resolutions of 1920x1080@60 or lower, and RGB36-bit video format transmission at resolutions of 1920x1080@60 or lower. Furthermore, it utilizes a lower-cost 3.125Gb / s single-link switching chip for host switching, and employs two 3.125Gb / s links to achieve lossless, uncompressed transmission while supporting RGB32-bit video format at 1920x1080@60 resolution, ensuring video quality. This eliminates the need for a more expensive 6.25Gb / s switching chip. It also supports mixed pairings, mixed transmission, and mixed interconnection systems for RGB36-bit and RGB24-bit video input and output. That is, an RGB24-bit receiver box can connect to both RGB24-bit and RGB32-bit transmitter boxes; similarly, an RGB36-bit receiver box can connect to both RGB36-bit and RGB24-bit transmitter boxes.

[0080] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0081] In one embodiment, such as Figure 10 The diagram illustrates a block diagram of a hybrid lossless transmission device 1000 based on a video fiber optic workstation, according to an embodiment of this application. The device includes a first processing module 1001 and a second processing module 1002, wherein:

[0082] The first processing module 1001 is used to receive the first video source signal, separate and losslessly encode the first video source signal, and send it to the first video switching card at a first preset high-speed serial rate. The first video switching card performs serial-to-parallel and parallel-to-serial conversion processes to split one high-speed serial data at the first preset high-speed serial rate into two high-speed serial data at the second preset high-speed serial rate and send them to the switching chip. The switching chip can then send the two high-speed serial data at the second preset high-speed serial rate to any one of the first video switching cards, or send the first of the two high-speed serial data at the second preset high-speed serial rate to any one of the second video switching cards. The first video switching card then sends the high-speed serial data to the first video receiving box for decoding to achieve video display.

[0083] The second processing module 1002 is used to receive the second video source signal, separate and losslessly encode the second video source signal, and send it to the second video switching card at a second preset high-speed serial rate. This causes the second video switching card to send high-speed serial data at the second preset high-speed serial rate to the switching chip. The switching chip then sends the high-speed serial data at the second preset high-speed serial rate to any one of the second video switching cards, or sends the high-speed serial data at the second preset high-speed serial rate to the first channel of high-speed serial data at the second preset high-speed serial rate in any one of the first video switching cards. This allows the second video switching card to send the high-speed serial data to the second video receiving box for decoding, thereby achieving video display.

[0084] In some embodiments, separating the first video source signal includes:

[0085] The first video source signal is separated into RGB components, each of which is one-third the bit depth of the first video source signal.

[0086] In one embodiment of this application, a computing device is provided, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above steps. The computing device provided in this application embodiment has a similar implementation principle and technical effect to the above method embodiment, and will not be described again here.

[0087] In one embodiment of this application, a non-transitory computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, it also performs the above steps; the implementation principle and technical effects of the computer-readable storage medium provided in this embodiment are similar to those of the above method embodiments, and will not be repeated here.

[0088] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0089] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A hybrid lossless transmission method based on video fiber optic workstations, characterized in that, include: The system receives a first video source signal, separates and losslessly encodes it, and then sends it to a first video switching card at a first preset high-speed serial rate. The first video switching card performs serial-to-parallel and parallel-to-serial conversion, splitting one channel of high-speed serial data at the first preset high-speed serial rate into two channels of high-speed serial data at a second preset high-speed serial rate. These channels are then sent to a switching chip, which in turn sends the two channels of high-speed serial data at the second preset high-speed serial rate to any one of the first video switching cards. The first video switching card then sends the high-speed serial data to a first video receiving box for decoding, thus enabling video display. Alternatively, the system sends the first channel of high-speed serial data at the second preset high-speed serial rate to any one of the second video switching cards, which then sends the high-speed serial data to a second video receiving box for decoding, thus enabling video display. The system receives a second video source signal, separates and losslessly encodes it, and then sends it to a second video switching card at a second preset high-speed serial rate. The second video switching card then sends the high-speed serial data at the second preset high-speed serial rate to the switching chip, which in turn sends the high-speed serial data at the second preset high-speed serial rate to any one of the second video switching cards. The second video switching card then sends the high-speed serial data to a second video receiving box for decoding, thus achieving video display. Alternatively, the system sends the high-speed serial data at the second preset high-speed serial rate to the first channel corresponding to the first high-speed serial data at the second preset high-speed serial rate in any one of the first video switching cards. The first video switching card then sends the high-speed serial data at the second preset high-speed serial rate to a first video receiving box for decoding, thus achieving video display. Wherein, the first video source signal and the second video source signal are both video signal sources with a preset bit depth, the second video source signal having a smaller bit depth than the first video source signal, the first preset high-speed serial rate being a high-speed serial rate of 6.25Gb / s; the first video switching card being a video switching card with a bit depth corresponding to the first video source signal; the second preset high-speed serial rate being a high-speed serial rate of 3.125Gb / s; and the second video switching card being a video switching card with a bit depth corresponding to the second video source signal.

2. The hybrid lossless transmission method based on video fiber optic seats as described in claim 1, characterized in that, The step of separating the first video source signal includes: The first video source signal is separated into RGB components, each of which is one-third the number of bits of the first video source signal.

3. The hybrid lossless transmission method based on video fiber optic seats as described in claim 1, characterized in that, The lossless encoding of the first video source signal includes: Using the 32-bit register in the field programmable gate array, represented by REG[31:0], the high 8 bits of R[11:4], G[11:4], and B[11:4] of each pair of pixels in the first video source signal are stored in the low 16 bits of REG for three clock cycles. Store the lower 4 bits of the RGB components of each pair of pixels (R[3:0], G[3:0], B[3:0]) using REG[23:16] for three clock cycles, and set the remaining bits of the pixel REG[31:24] to zero.

4. The hybrid lossless transmission method based on video fiber optic seats as described in claim 1, characterized in that, The step of enabling the first video switching card to send the high-speed serial data to the first video receiving box for decoding, and then realizing video display, includes: If the first video switching card receives two channels of high-speed serial data at a second preset high-speed serial rate, then the first video switching card merges the two channels of high-speed serial data at the second preset high-speed serial rate into one channel of high-speed serial data at a first preset high-speed serial rate, and sends it to the first video receiving box, so that the first video receiving box decodes the high-speed serial data and sends it to the first video display device to realize video display.

5. The hybrid lossless transmission method based on video fiber optic seats as described in claim 1, characterized in that, The step of separating the second video source signal includes: The second video source signal is separated into RGB components, each of which is one-third the bit depth of the second video source signal.

6. The hybrid lossless transmission method based on video fiber optic seats as described in claim 1, characterized in that, The lossless encoding of the second video source signal includes: Using a 16-bit register in a field-programmable gate array (FPGA) and represented by REG[15:0], the R[7:0], G[7:0], and B[7:0] of each pair of RGB components in the second video source signal are stored in a 16-bit REG for three clock cycles.

7. A hybrid lossless transmission device based on video fiber optic workstations, characterized in that, include: A first processing module is configured to receive a first video source signal, separate and losslessly encode the first video source signal, and then send it to a first video switching card at a first preset high-speed serial rate. The first video switching card performs serial-to-parallel and parallel-to-serial conversions to split one channel of high-speed serial data at the first preset high-speed serial rate into two channels of high-speed serial data at a second preset high-speed serial rate, and send them to a switching chip. The switching chip then sends the two channels of high-speed serial data at the second preset high-speed serial rate to any one of the first video switching cards, allowing the first video switching card to send the high-speed serial data to a first video receiving box for decoding and video display. Alternatively, the first channel of high-speed serial data at the second preset high-speed serial rate can be sent to any one of the second video switching cards, allowing the second video switching card to send the high-speed serial data to a second video receiving box for decoding and video display. The second processing module is used to receive the second video source signal, separate and losslessly encode the second video source signal, and send it to the second video switching card at a second preset high-speed serial rate. This causes the second video switching card to send high-speed serial data at the second preset high-speed serial rate to a switching chip, which in turn sends the high-speed serial data at the second preset high-speed serial rate to any one of the second video switching cards. The second video switching card then sends the high-speed serial data to a second video receiving box for decoding, thus enabling video display. Alternatively, the module can send the high-speed serial data at the second preset high-speed serial rate to a first channel in any one of the first video switching cards, causing the first video switching card to send the high-speed serial data at the second preset high-speed serial rate to a first video receiving box for decoding, thus enabling video display. Wherein, the first video source signal and the second video source signal are both video signal sources with a preset bit depth, the second video source signal having a smaller bit depth than the first video source signal, the first preset high-speed serial rate being a high-speed serial rate of 6.25Gb / s; the first video switching card being a video switching card with a bit depth corresponding to the first video source signal; the second preset high-speed serial rate being a high-speed serial rate of 3.125Gb / s; and the second video switching card being a video switching card with a bit depth corresponding to the second video source signal.

8. The hybrid lossless transmission device based on video fiber optic seats as described in claim 7, characterized in that, The step of separating the first video source signal includes: The first video source signal is separated into RGB components, each of which is one-third the number of bits of the first video source signal.

9. A computing device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the hybrid lossless transmission method based on video fiber optic seats as described in any one of claims 1 to 6 when executing the computer program.

10. A non-transitory computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the hybrid lossless transmission method based on video fiber optic seats as described in any one of claims 1 to 6.

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