Display panel, source driving chip and electronic device

Abstract

The application provides a display panel, a source driving chip and an electronic device, comprising: a plurality of first sub-pixels, a plurality of second sub-pixels, a first source driving chip comprising a first delay module with a first delay load, a second source driving chip comprising a second delay module with a second delay load, the first delay module being electrically connected to the plurality of first sub-pixels, the second delay module being electrically connected to the plurality of second sub-pixels, and the second source driving chip further comprising a first compensation module electrically connected to the plurality of second sub-pixels and the second delay module, the first compensation module being used for compensating for a difference between equivalent resistances of the second delay load and the first delay load according to parameters of the second delay module and parameters of the first delay module, so as to improve display unevenness of a picture.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to the manufacture of display devices, specifically to display panels, source driver chips, and electronic devices. Background Technology

[0002] As the most widely used display currently available, LCDs have been developed with consideration for the cost of data driver chips. These include DLS architecture (where adjacent sub-pixels share a single data line) and Tri-gate architecture (where the number of gate lines is increased by 3 times to reduce the number of data lines to 1 / 3).

[0003] While the above architecture reduces the number of source driver chips by half or more compared to the 1G1D architecture, the load driven by these chips is also significantly larger. This can be addressed using ODDC (Output Data Delay Compensation) technology to ensure that all output channels within the source driver chip have the same voltage after charging. However, for different display areas corresponding to different levels in ODDC, the different connections between components within the ODDC module lead to variations in the equivalent load, resulting in differences in the output data signals and causing screen splitting.

[0004] Therefore, existing display panels using ODDC technology have the above-mentioned defects and urgently need improvement. Summary of the Invention

[0005] The purpose of this invention is to provide a display panel, a source driver chip, and an electronic device to improve the screen splitting phenomenon that occurs in existing display panels using ODDC technology.

[0006] This invention provides a display panel, comprising:

[0007] Multiple first sub-pixels;

[0008] Multiple second sub-pixels;

[0009] The first source driver chip includes a first delay module, which is electrically connected to a plurality of the first sub-pixels and includes a first delay load.

[0010] The second source driver chip includes a second delay module, which is electrically connected to a plurality of second sub-pixels and includes a second delay load;

[0011] The second source driver chip further includes a first compensation module electrically connected to the plurality of second sub-pixels and the second delay module. The first compensation module is used to compensate for the difference in equivalent resistance between the second delay load and the first delay load based on the parameters of the second delay module and the parameters of the first delay module.

[0012] In one embodiment, the first delay module has a first delay interval, the second delay module has a second delay interval, and the first compensation module is used to compensate for the difference between the equivalent resistances of the second delay load and the first delay load based on the difference between the second delay interval and the first delay interval.

[0013] And / or, the first delay module has a first delay level, the second delay module has a second delay level, and the first compensation module is used to compensate for the difference between the equivalent resistance of the second delay load and the first delay load based on the difference between the second delay level and the first delay level.

[0014] In one embodiment, the first delay module has a first delay interval, and the second delay module has a second delay interval;

[0015] The first delay module is used to sequentially output a plurality of first voltages corresponding to a plurality of first sub-pixels at a first delay interval, and the second delay module is used to sequentially output a plurality of second voltages corresponding to a plurality of second sub-pixels at a second delay interval.

[0016] In one embodiment, the first delay module has a first delay interval, the second delay module has a second delay interval, the second delay interval is smaller than the first delay interval, and the equivalent resistance of the second delay load is smaller than the equivalent resistance of the first delay load;

[0017] The first compensation module includes a compensation load, and the absolute value of the difference between the sum of the equivalent resistance values ​​of the compensation load and the second delay load and the equivalent resistance value of the first delay load is less than the absolute value of the difference between the equivalent resistance values ​​of the second delay load and the first delay load.

[0018] In one embodiment, the compensation load includes a plurality of sub-compensation modules arranged in parallel, and / or includes a plurality of sub-compensation modules arranged in series;

[0019] Each of the sub-compensation modules includes at least one corresponding sub-compensation load, and the multiple sub-compensation loads in the multiple sub-compensation modules constitute the compensation load.

[0020] In one embodiment, the sub-compensation load includes at least one of a load resistor and a load capacitor, wherein the load resistor is connected in series with the second delay module, and the load capacitor is connected to the second delay module and ground;

[0021] The sub-compensation module further includes a sub-selection module connected to the sub-compensation load. The sub-selection module is used to control the corresponding sub-compensation load to be electrically connected or disconnected from multiple second sub-pixels.

[0022] In one embodiment, the sub-compensation module includes an input terminal and an output terminal, and the sub-selection module includes:

[0023] The first switch connects the load capacitor to ground;

[0024] The second switch connects the load resistor and the output terminal;

[0025] The third switch connects the input terminal and the output terminal;

[0026] The sub-compensation module further includes a sub-control module electrically connected to the first switch, the second switch, and the third switch. The sub-control module is used to control the first switch and the second switch to turn on, and to control the third switch to turn off, so that the corresponding sub-compensation load is electrically connected to a plurality of second sub-pixels. It is also used to control the third switch to turn on, and to control the first switch and the second switch to turn off, so that the corresponding sub-compensation load is disconnected from a plurality of second sub-pixels.

[0027] In one embodiment, it further includes:

[0028] Multiple third sub-pixels;

[0029] The third source driver chip includes a third delay module, which is electrically connected to a plurality of the third sub-pixels and includes a third delay load.

[0030] The third source driver chip further includes a second compensation module electrically connected to the plurality of third sub-pixels and the third delay module. The second compensation module is used to compensate for the difference in equivalent resistance between the third delay load and the first delay load based on the parameters of the third delay module and the parameters of the first delay module.

[0031] Wherein, the absolute value of the difference between the parameters of the third delay module and the parameters of the first delay module is greater than the absolute value of the difference between the parameters of the second delay module and the parameters of the first delay module, and the compensation value of the second compensation module is greater than the compensation value of the first compensation module.

[0032] The present invention also provides a source driver chip, comprising:

[0033] A delay module, having delay parameters, is used to electrically connect to multiple sub-pixels of the display panel and includes a delay load;

[0034] A compensation module is electrically connected to the plurality of sub-pixels and the delay module, and the compensation module is used to compensate for the delay load according to the delay parameters.

[0035] In one embodiment, the compensation module includes:

[0036] The compensation load includes at least one of a load resistor connected in series with the delay module and a load capacitor connecting the delay module and ground;

[0037] The selection module, connected to the compensation load, is used to control the electrical connection or disconnection of the corresponding compensation load with the multiple sub-pixels.

[0038] The present invention also provides an electronic device comprising a display panel as described in any of the above descriptions, or a source driver chip as described in any of the above descriptions.

[0039] This invention provides a display panel, a source driver chip, and an electronic device, comprising: a plurality of first sub-pixels; a plurality of second sub-pixels; a first source driver chip including a first delay module electrically connected to the plurality of first sub-pixels and including a first delay load; a second source driver chip including a second delay module electrically connected to the plurality of second sub-pixels and including a second delay load; wherein the second source driver chip further includes a first compensation module electrically connected to the plurality of second sub-pixels and the second delay module, the first compensation module being used to compensate for the difference in equivalent resistance between the second delay load and the first delay load based on parameters of the second delay module and parameters of the first delay module, thereby improving the uneven display of the image caused by the difference in equivalent resistance between the second delay load and the first delay load. Attached Figure Description

[0040] The present invention will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for illustrating some embodiments of the present invention. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0041] Figure 1 This is a top-view structural diagram of the display panel provided in an embodiment of the present invention.

[0042] Figure 2 and Figure 5A block diagram of a display panel provided in an embodiment of the present invention.

[0043] Figure 3 and Figure 4 These are waveform diagrams of some signals in the display panel provided in the embodiments of the present invention.

[0044] Figure 6 A block diagram and a partial circuit diagram of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0046] In the description of this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" or "second" may explicitly or implicitly include one or more of the stated features. Furthermore, it should be noted that the accompanying drawings only provide structures closely related to the invention, omitting some details less relevant to the invention. The purpose is to simplify the drawings and make the inventive points clear at a glance, not to indicate that the actual device is identical to the accompanying drawings. Figure 1 It is identical, but this is not a limitation of the actual device.

[0047] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase at various points in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0048] The present invention provides a display panel, which may include, but is not limited to, the following embodiments and combinations thereof.

[0049] In one embodiment, such as Figure 1As shown, the display panel 100 includes: a plurality of first sub-pixels 101; a plurality of second sub-pixels 102; a first source driver chip 201, including a first delay module 301, the first delay module 301 including a first delay load 01 and electrically connected to the plurality of first sub-pixels 101; a second source driver chip 202, including a second delay module 302, the second delay module 302 including a second delay load 02 and electrically connected to the plurality of second sub-pixels 102; wherein, the second source driver chip 202 further includes a first compensation module 40 electrically connected to the plurality of second sub-pixels 102 and the second delay module 302, the first compensation module 40 being used to compensate for the difference in equivalent resistance between the second delay load 02 and the first delay load 01 according to the parameters of the second delay module and the parameters of the first delay module.

[0050] The display area A can be provided with multiple gate lines and multiple data lines. Each gate line can be electrically connected to multiple corresponding sub-pixels, and each data line can be electrically connected to multiple corresponding sub-pixels. When one of the gate lines controls the multiple corresponding sub-pixels to turn on, each data line can apply the data voltage transmitted at this time to the corresponding turned-on sub-pixel. Multiple gate lines operate in the same way in sequence, thereby realizing the turn-on of all sub-pixels in sequence. Each time multiple sub-pixels are turned on, multiple data lines operate in the same way, thereby realizing the light emission of the corresponding multiple sub-pixels, and finally realizing the light emission of all sub-pixels.

[0051] Furthermore, such as Figure 1 As shown, the display panel 100 may include multiple source driver chips located in the non-display area. Each source driver chip can be electrically connected to multiple corresponding sub-pixels in the display area A. For multiple sub-pixels connected to any of the same gate lines, at least two sub-pixels can be electrically connected to the same source driver chip through corresponding data lines, and receive at least two corresponding data voltages respectively. Furthermore, the multiple source driver chips can be electrically connected to at least one power supply chip to receive the original data voltage for generating subsequent data voltages. It should be noted that at least one of the following—the impedance difference within different source driver chips, the impedance difference between different source driver chips and the corresponding multiple sub-pixels, and the impedance difference between different source driver chips and the corresponding power supply chip—can lead to uneven charging of different sub-pixels connected to different source driver chips. Therefore, a corresponding delay module can be set in the source driver chip to delay the time of the signals output by different connections corresponding to different sub-pixels, and to differentiate the charging time settings to compensate for the difference in total charging amount caused by impedance differences.

[0052] It is important to note that since the delay module itself also has a corresponding delay load, while compensating for the difference in total charging amount caused by impedance differences, the difference in the equivalent resistance of the two delay loads corresponding to the two delay modules with different delay intervals will lead to differences in the attenuation of the data voltage loaded on the two sub-pixels electrically connected to different source driver chips, resulting in uneven display of the image. Specifically, for ease of description, this example only considers multiple sub-pixels arranged in an array along the row and column directions, with multiple source driver chips electrically connected to multiple sub-pixel groups arranged in the horizontal direction. That is, multiple first sub-pixels 101 and multiple second sub-pixels 102 can be considered to be located in two areas arranged in the horizontal direction in the display area A. As discussed above, due to the difference in the equivalent resistance between the second delay load 02 and the first delay load 01, the data voltage loaded on the multiple first sub-pixels 101 and multiple second sub-pixels 102 has different attenuations.

[0053] Specifically, the first delay module 301 has a first delay interval, the second delay module 302 has a second delay interval, and the first compensation module 40 is used to compensate for the difference in equivalent resistance between the second delay load 02 and the first delay load 01 based on the difference between the second delay interval and the first delay interval; and / or, the first delay module 301 has a first delay level, the second delay module 302 has a second delay level, and the first compensation module 40 is used to compensate for the difference in equivalent resistance between the second delay load 02 and the first delay load 01 based on the difference between the second delay level and the first delay level. This embodiment uses the former as an example for illustration.

[0054] Understandably, the second source driver chip 202 in this embodiment also includes a first compensation module 40 electrically connected to a plurality of second sub-pixels 102 and a second delay module 302. The first compensation module 40 is used to compensate for the difference in equivalent resistance between the second delay load 02 and the first delay load 01 based on the difference between the second delay interval and the first delay interval. While the first delay module 301 and the second delay module 302 compensate for the difference in total charging amount caused by impedance difference, the first compensation module 40 can also compensate for the difference in equivalent resistance between the second delay load 02 and the first delay load 01 caused by the difference in equivalent resistance, thereby improving the uneven display of the screen caused by the difference in equivalent resistance between the second delay load 02 and the first delay load 01.

[0055] In this embodiment, the specific manner in which the first compensation module 40 and the second delay module 302 are electrically connected to the plurality of second sub-pixels 102, and the specific structure of the first compensation module 40, are not limited. It is sufficient that the first compensation module 40 in the second source driver chip 202 can be used to compensate for the difference in equivalent resistance between the second delay load 02 and the first delay load 01 based on the difference between the second delay interval and the first delay interval. For example, the first compensation module 40 may include, but is not limited to, at least one of voltage source compensation, current source compensation, and load compensation.

[0056] In one embodiment, such as Figure 1 As shown, it also includes: multiple first connection lines 601 connected to the first delay module 301, the first delay module 301 being used to sequentially send multiple first voltages corresponding to multiple first sub-pixels 101 to the multiple first connection lines 601 at the first delay interval; and multiple second connection lines 602 connected to the second delay module 302, the second delay module 302 being used to sequentially send multiple second voltages corresponding to multiple second sub-pixels 102 to the multiple second connection lines 602 at the second delay interval. It should be noted that the first voltage and the second voltage here are not the two data voltages ultimately applied to the first sub-pixels 101 and the second sub-pixels 102 respectively, but should be understood as multiple first voltages and multiple second voltages output by the corresponding first delay module 301 and the corresponding second delay module 302 at the first delay interval and the second delay interval respectively. These multiple first voltages and multiple second voltages need to be processed to form different first data voltages applied to different first sub-pixels 101 and different second data voltages applied to different second sub-pixels 102. In this embodiment, the first connecting line 601 and the second connecting line 602 can be understood as connecting lines that connect to the output terminals of the first delay module 301 and the second delay module 302, respectively, and the signals transmitted can be equivalent to the signals output by the first delay module 301 and the second delay module 302.

[0057] Specifically, such as Figure 2As shown, the internal structure of the second source driver chip 202 is used as an example for illustration. The display panel 100 may also include a gamma generation module 701 and a timing control module 702 electrically connected to the second source driver chip 202. The gamma generation module 701 and the timing control module 702 transmit gamma signals and image signals to the second source driver chip 202, respectively. Considering that the transistors in the display panel 100 are of different types, the polarity of the turn-on voltage may be different. The gamma signal may include positive gamma signals and negative gamma signals. The second source driver chip 202 can process the image signal according to the gamma signal to generate multiple data voltages respectively loaded onto multiple sub-pixels.

[0058] Furthermore, in combination Figure 1 and Figure 2 As shown, the second source driver chip 202 may further include a digital-to-analog converter module 703 electrically connected to the first compensation module 40, and a buffer module 704 electrically connected to the digital-to-analog converter module 703 and multiple second sub-pixels 102; furthermore, the second source driver chip 202 may also include a register for receiving clock signals and a multi-level latch for receiving image signals. It can be assumed that the gamma signal generated by the gamma generation module 701 is processed by the second delay module 302 and the first compensation module 40 in sequence, and the resulting signal is transmitted to the digital-to-analog converter module 703. The image signal generated by the timing control module 702 is also transmitted to the digital-to-analog converter module 703 after passing through the multi-level latch in sequence. After processing, the digital-to-analog converter module 703 generates multiple second data voltages that correspond to multiple rows of second sub-pixels 102 in sequence, and then transmits them to the corresponding rows of second sub-pixels 102 in sequence through the buffer.

[0059] It should be noted that the second delay module 302 and the first compensation module 40 in the second source driver chip 202 of this invention can process at least one of gamma signals and image signals, or signals generated by processing gamma signals and image signals. It is sufficient that the first compensation module 40 corresponds to one second delay module 302 to achieve the corresponding compensation. Depending on the processing requirements, the second delay module 302 and the first compensation module 40 can be placed in a suitable signal flow path. Figure 2 The diagram only illustrates the connection method where both the second delay module 302 and the first compensation module 40 process gamma signals, and the first compensation module 40 processes the signal after the second delay module 302.

[0060] Specifically, assuming that two gamma generation modules 701 with different impedances theoretically produce the same two gamma signals, such as... Figure 3As shown, due to the difference in impedance between the two, the two gamma signals V1 and V2 are actually different, with different amplitudes (for example, the amplitude of V1 is smaller than the amplitude of V2). This means that the impedance corresponding to V1 is greater than the impedance corresponding to V2. Accordingly, for the output terminals of the two gamma generation modules 701, the peak value of V1 will appear later than the peak value of V2.

[0061] Correspondingly, such as Figure 4 As shown, V3 and V4 can be the signals output by the first delay module 301 and the second delay module 302 respectively, corresponding to the two gamma generation modules 701, and the difference between the first delay interval and the second delay interval can be t. Further, taking the example of the first compensation module 40, the digital-to-analog conversion module 703, and the buffer module 704 sequentially connected to the corresponding first delay module 301 or second delay module 302, the first compensation module 40 adjusts the second delay interval based on the difference between the second delay interval and the first delay interval. Since compensation has been made for the signal V5 output by the digital-to-analog converter 703 connected after the first compensation module 40 and the signal V6 output by the digital-to-analog converter 703 corresponding to the first delay module 301 can only have a difference in delay interval t, and their amplitudes can be the same. Similarly, the signal V6 output by the buffer module 704 connected after the first compensation module 40 and the signal V8 output by the buffer module 704 corresponding to the first delay module 301 can only have a difference in delay interval t, and their amplitudes can be the same.

[0062] In one embodiment, such as Figure 1 As shown, the display panel 100 further includes: a plurality of third sub-pixels 103; a third source driver chip 203, including a third delay module 303 having a third delay interval, the third delay module 303 being electrically connected to the plurality of third sub-pixels 103 and including a third delay load 03; wherein, the third source driver chip 203 further includes a second compensation module 50 electrically connected to the plurality of third sub-pixels 103 and the third delay module 303, the second compensation module 50 being used to compensate for the difference in equivalent resistance between the third delay load 03 and the first delay load 01 based on the difference between the third delay interval and the first delay interval; wherein, the absolute value of the difference between the third delay interval and the first delay interval is greater than the absolute value of the difference between the second delay interval and the first delay interval, and the compensation value of the second compensation module is greater than the compensation value of the first compensation module.

[0063] Understandably, this embodiment further illustrates that, based on the first delay load 01 in the first source driver chip 201 as the standard, the first compensation module 40 and the second compensation module 50 are set to two corresponding compensation values, respectively, to compensate the corresponding second delay load 02 and the corresponding third delay load 03. Therefore, it can be considered that the greater the difference from the first delay interval, that is, the greater the difference from the first delay load, the greater the absolute value of the compensation value to be set.

[0064] It is important to note that, as discussed above, gamma signals can include positive and negative gamma signals. If the absolute values ​​of the differences between the positive and negative gamma signals and the reference voltage are the same, and if the voltage values ​​corresponding to both the positive and negative gamma signals are greater than or less than 0, then the same compensation module can be used to compensate for both signals. If the voltage values ​​corresponding to the positive and negative gamma signals are greater than 0 and less than 0, respectively, then a NOT gate can be connected before the input and after the output of the compensation module used to process the positive gamma signal to create a new compensation module for compensating the negative gamma signal. If the absolute values ​​of the differences between the positive and negative gamma signals and the reference voltage are not the same, then two compensation modules with different compensation values ​​need to be set up to compensate for the corresponding amplitudes of the positive and negative gamma signals respectively.

[0065] For example, Figure 1 As shown, the first compensation module 40 includes a first compensation load 401, and the second compensation module 50 includes a second compensation load 501; wherein, the absolute value of the difference between the third delay interval and the first delay interval is greater than the absolute value of the difference between the second delay interval and the first delay interval, and the absolute value of the equivalent resistance of the second compensation load 501 is greater than the absolute value of the equivalent resistance of the first compensation load 401.

[0066] Understandable, combined Figure 1 and Figure 2 As shown, using the architecture of this embodiment, based on the one-to-one correspondence between the number and position of multiple first sub-pixels and multiple second sub-pixels, if the first compensation module 40 can "fully compensate" for the difference in equivalent resistance between the second delay load 02 and the first delay load 01 based on the difference between the second delay interval and the first delay interval, then it can be considered that when the same image signal and the same gamma signal are loaded onto the first source driver chip 201 and the second source driver chip 202, the first data voltage loaded on each first sub-pixel 101 can be equal to the second data voltage loaded on the second sub-pixel 102 at the corresponding position.

[0067] In one embodiment, such as Figure 1 As shown, the second delay interval is smaller than the first delay interval, and the equivalent resistance of the second delay load 02 is smaller than the equivalent resistance of the first delay load 01; wherein, the first compensation module 40 includes a compensation load (i.e., a first compensation load 401), and the absolute value of the difference between the sum of the equivalent resistance values ​​of the first compensation load 401 and the second delay load 02 and the equivalent resistance value of the first delay load 01 is smaller than the absolute value of the difference between the equivalent resistance values ​​of the second delay load 02 and the first delay load 01.

[0068] Specifically, based on the above discussion, the delay module itself also has a corresponding delay load. It can be assumed that the smaller the delay interval, the smaller the equivalent resistance of the delay load presented by the corresponding circuit connection method. In this embodiment, based on the fact that the equivalent resistance of the second delay load 02 is less than the equivalent resistance of the first delay load 01, the first compensation module 40 is set to include the first compensation load 401. That is, for the second source driver chip 202, the first compensation load 401 is superimposed on the second delay load 02 with a smaller equivalent resistance, which can reduce the difference with the first delay load 01, thereby improving the uneven display of the screen caused by the large difference in the equivalent resistance values ​​of the second delay load 02 and the first delay load 01.

[0069] In one embodiment, such as Figure 5 As shown, the compensation module 40 includes at least one of the following: multiple sub-compensation modules 402 arranged in parallel or multiple sub-compensation modules 402 arranged in series. Figure 5 (Taking a parallel configuration as an example only); wherein, each of the sub-compensation modules 402 includes at least one corresponding sub-compensation load 4025, and the multiple sub-compensation loads 4025 among the multiple sub-compensation modules 402 constitute the compensation load. Specifically, the series or parallel connection of multiple sub-compensation modules 402 can be set according to the required compensation value and the specific structure of the compensation module 40, thereby obtaining a compensation load with an equivalent resistance corresponding to a suitable compensation value.

[0070] In one embodiment, combined with Figure 1 and Figure 6As shown, the sub-compensation load 4025 includes at least one of a load resistor R and a load capacitor C. The load resistor R is connected in series with the second delay module 302, and the load capacitor C is connected to the second delay module 302 and ground. The sub-compensation module 402 further includes a sub-selection module 4021 connected to the sub-compensation load 4025. The sub-selection module 4021 is used to control the electrical connection or disconnection of the corresponding sub-compensation load 4025 with multiple second sub-pixels 102. The load capacitor C is connected to the second delay module 302 and ground, and it is not limited whether other components are provided between the load capacitor C and the second delay module 302, such as... Figure 6 As shown, a load resistor R can be set between the two.

[0071] In this embodiment, the load resistor R has a corresponding impedance value, and the load capacitor C has a corresponding capacitive reactance value. The "equivalent resistance" mentioned above can represent the sum of all impedance and capacitive reactance values ​​in the compensation module 40 or the sub-compensation module 402. Specifically, based on the signal flowing from the second delay module 302 to the digital-to-analog converter module 703, the load resistor R in this embodiment is connected in series with the second delay module 302, which has an attenuation effect on the signal. Similarly, the load capacitor C can be understood as acting on the signal during the process of the signal flowing from the second delay module 302 to the digital-to-analog converter module 703, which also has an attenuation effect on the signal. Furthermore, if the signal is close to a DC signal, the capacitive reactance of the load capacitor C will be huge.

[0072] It is understood that the sub-selection module 4021 included in each sub-compensation module 402 in this embodiment can control the electrical connection or disconnection of the corresponding sub-compensation load with multiple second sub-pixels 102, combined with Figure 5 and Figure 6 As shown, the number of sub-compensation modules 402 that are actually connected to the sub-compensation load 4025 (at least one of R and C) is determined, so as to determine the number of sub-compensation modules 402 that can play a compensation role, and thus have corresponding compensation values.

[0073] In one embodiment, combined with Figure 1 , Figure 5 and Figure 6As shown, the sub-compensation module 402 further includes an input terminal 4022 and an output terminal 4023. The sub-selection module 4021 includes: a first switch Q1, connected to the load capacitor C and ground; a second switch Q2, connected to the load resistor R and the output terminal 4023; and a third switch Q3, connected to the input terminal 4022 and the output terminal 4023. The sub-compensation module 402 also includes a sub-control module 4024 electrically connected to the first switch Q1, the second switch Q2, and the third switch Q3. The sub-control module 4024 controls the first switch Q1 and the second switch Q2 to open and controls the third switch Q3 to close, so that the corresponding sub-compensation load 4025 is electrically connected to multiple second sub-pixels 102. It also controls the third switch Q3 to open and controls the first switch Q1 and the second switch Q2 to close, so that the corresponding sub-compensation load 4025 is disconnected from multiple second sub-pixels 102.

[0074] Specifically, the first switch Q1 and the second switch Q2 can be considered to control the on / off state of the branches containing the load capacitor C and the load resistor R, respectively, while the third switch Q3 is used to control the electrical connection between the second delay module 302 and the digital-to-analog converter module 703 without any sub-compensation load 4025. Specifically, based on... Figure 1 and Figure 6 The structure shown below, where "UI" can represent the smallest unit of delay, can be referenced but is not limited to the following settings:

[0075] If the first delay interval and the second delay interval are 8UI and 2UI respectively, it can be assumed that the first delay load 01 corresponding to the first delay interval 8UI does not need to be compensated, and only the second delay load 02 corresponding to the second delay interval 2UI is compensated. For example, the corresponding sub-compensation load 4025 can be electrically connected to multiple second sub-pixels 102 by controlling the three sub-control modules 4024. That is, the first switch Q1 and the second switch Q2 corresponding to each of the three sub-control modules 4024 are turned on, and the corresponding third switch Q3 is turned off.

[0076] If the first delay interval and the second delay interval are 6UI and 2UI respectively, it can be assumed that the first delay load 01 corresponding to the first delay interval 6UI does not need to be compensated, and only the second delay load 02 corresponding to the second delay interval 2UI is compensated. For example, the corresponding sub-compensation load 4025 can be electrically connected to multiple second sub-pixels 102 by controlling the two sub-control modules 4024. That is, the first switch Q1 and the second switch Q2 corresponding to each of the two sub-control modules 4024 are turned on, and the corresponding third switch Q3 is turned off.

[0077] If the first delay interval and the second delay interval are 4UI and 2UI respectively, then the first delay load 01 corresponding to the first delay interval 4UI does not need to be compensated. Only the second delay load 02 corresponding to the second delay interval 2UI is compensated. For example, the corresponding sub-compensation load 4025 can be electrically connected to multiple second sub-pixels 102 by one sub-control module 4024. That is, the first switch Q1 and the second switch Q2 corresponding to the one sub-control module 4024 are turned on, and the corresponding third switch Q3 is turned off.

[0078] It should be noted that, considering that there may be source driver chips with a delay interval greater than the first delay interval, a corresponding compensation module can also be set in the first source driver chip 201 to perform corresponding compensation. In the above three cases, all sub-compensation loads 4025 can be disconnected from multiple second sub-pixels 102 by all sub-control modules 4024 in the first source driver chip 201. That is, the first switch Q1 and the second switch Q2 corresponding to each sub-control module 4024 are closed, and the corresponding third switch Q3 is turned on.

[0079] The present invention also provides a source driver chip, which may include, but is not limited to, the following embodiments and combinations thereof.

[0080] In one embodiment, the source driver chip includes: a delay module having delay parameters, electrically connected to a plurality of sub-pixels of the display panel, and including a delay load; and a compensation module electrically connected to the plurality of sub-pixels and the delay module, the compensation module being used to compensate the delay load according to the delay parameters. The specific structure and function of the "source driver chip," "delay module," and "compensation module" discussed in this embodiment can be referred to the above descriptions of the "second source driver chip," "second delay module," and "second compensation module." However, it should be noted that the above descriptions of the "second source driver chip" do not limit the source driver chip in this embodiment. The source driver chip can exist independently of the display panel and other structures.

[0081] Specifically, the delay parameter can be either a delay interval or a delay level. Here, "delay interval" can represent the time interval of the delay module relative to a standard time period. This "standard time period" can be, for example, the "first delay interval" mentioned above, or it can be a preset value. Similarly, "delay level" can represent the difference in delay level between the delay module and the standard level. This "standard level" can be, for example, the "first delay level" mentioned above, or it can be a preset value.

[0082] In one embodiment, the compensation module includes: a compensation load, comprising at least one of a load resistor connected in series with the delay module and a load capacitor connecting the delay module and ground; and a selection module connected to the compensation load, used to control the corresponding compensation load to be electrically connected or disconnected from the plurality of sub-pixels. Specifically, refer to the above description... Figure 5 , Figure 6 According to the relevant description, the compensation load can be, but is not limited to, the "first compensation load" and "second compensation load" mentioned above.

[0083] The present invention also provides an electronic device, including a display panel as described in any of the above descriptions, or including a source driver chip as described in any of the above descriptions.

[0084] This invention provides a display panel, a source driver chip, and an electronic device, comprising: a plurality of first sub-pixels; a plurality of second sub-pixels; a first source driver chip including a first delay module electrically connected to the plurality of first sub-pixels and including a first delay load; a second source driver chip including a second delay module electrically connected to the plurality of second sub-pixels and including a second delay load; wherein the second source driver chip further includes a first compensation module electrically connected to the plurality of second sub-pixels and the second delay module, the first compensation module being used to compensate for the difference in equivalent resistance between the second delay load and the first delay load based on parameters of the second delay module and parameters of the first delay module, thereby improving the uneven display of the image caused by the difference in equivalent resistance between the second delay load and the first delay load.

[0085] The display panel, source driver chip, and electronic device provided in the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: Multiple first sub-pixels; Multiple second sub-pixels; The first source driver chip includes a first delay module, which is electrically connected to a plurality of the first sub-pixels and includes a first delay load. The second source driver chip includes a second delay module, which is electrically connected to a plurality of second sub-pixels and includes a second delay load; The first delay module and the second delay module both have delay parameters, which are delay intervals and / or delay levels. The second source driver chip further includes a first compensation module electrically connected to multiple second sub-pixels and the second delay module. The first compensation module includes a compensation load, which includes multiple sub-compensation modules connected in parallel, and / or multiple sub-compensation modules connected in series. Each sub-compensation module includes at least one corresponding sub-compensation load, and the multiple sub-compensation loads in the multiple sub-compensation modules constitute the compensation load. The first compensation module is used to compensate for the difference in equivalent resistance between the second delay load and the first delay load based on the delay parameters of the second delay module and the delay parameters of the first delay module.

2. The display panel as described in claim 1, characterized in that, When the delay parameter is a delay interval, the first delay module has a first delay interval, the second delay module has a second delay interval, and the first compensation module is used to compensate for the difference between the equivalent resistance of the second delay load and the first delay load based on the difference between the second delay interval and the first delay interval. And / or, when the delay parameter is a delay level, the first delay module has a first delay level, the second delay module has a second delay level, and the first compensation module is used to compensate for the difference between the equivalent resistance of the second delay load and the first delay load based on the difference between the second delay level and the first delay level.

3. The display panel as described in claim 1 or 2, characterized in that, The first delay module has a first delay interval, and the second delay module has a second delay interval; The first delay module is used to sequentially output a plurality of first voltages corresponding to a plurality of first sub-pixels at the first delay interval, and the second delay module is used to sequentially output a plurality of second voltages corresponding to a plurality of second sub-pixels at the second delay interval.

4. The display panel as described in claim 2, characterized in that, The first delay module has a first delay interval, the second delay module has a second delay interval, the second delay interval is smaller than the first delay interval, and the equivalent resistance of the second delay load is smaller than the equivalent resistance of the first delay load; Wherein, the absolute value of the difference between the sum of the equivalent resistance values ​​of the compensation load and the second delay load and the equivalent resistance value of the first delay load is less than the absolute value of the difference between the equivalent resistance values ​​of the second delay load and the first delay load.

5. The display panel as described in claim 1, characterized in that, The sub-compensation load includes at least one of a load resistor and a load capacitor, wherein the load resistor is connected in series with the second delay module, and the load capacitor is connected to the second delay module and ground; The sub-compensation module further includes a sub-selection module connected to the sub-compensation load. The sub-selection module is used to control the corresponding sub-compensation load to be electrically connected or disconnected from multiple second sub-pixels.

6. The display panel as described in claim 5, characterized in that, The sub-compensation module includes an input terminal and an output terminal, and the sub-selection module includes: The first switch connects the load capacitor to ground; The second switch connects the load resistor and the output terminal; The third switch connects the input terminal and the output terminal; The sub-compensation module further includes a sub-control module electrically connected to the first switch, the second switch, and the third switch. The sub-control module is used to control the first switch and the second switch to turn on, and to control the third switch to turn off, so that the corresponding sub-compensation load is electrically connected to a plurality of second sub-pixels. It is also used to control the third switch to turn on, and to control the first switch and the second switch to turn off, so that the corresponding sub-compensation load is disconnected from a plurality of second sub-pixels.

7. The display panel as described in claim 1 or 2, characterized in that, Also includes: Multiple third sub-pixels; The third source driver chip includes a third delay module, which is electrically connected to a plurality of the third sub-pixels and includes a third delay load. The third source driver chip further includes a second compensation module electrically connected to the plurality of third sub-pixels and the third delay module. The second compensation module is used to compensate for the difference in equivalent resistance between the third delay load and the first delay load based on the delay parameters of the third delay module and the delay parameters of the first delay module. Wherein, the absolute value of the difference between the delay parameter of the third delay module and the delay parameter of the first delay module is greater than the absolute value of the difference between the delay parameter of the second delay module and the delay parameter of the first delay module, and the compensation value of the second compensation module is greater than the compensation value of the first compensation module.

8. A source driver chip, characterized in that, The source driver chip, used in a display panel as described in any one of claims 1-7, comprises: A delay module, having delay parameters, is electrically connected to multiple sub-pixels of a display panel and includes a delay load; the delay parameters are delay intervals and / or delay levels. A compensation module is electrically connected to multiple sub-pixels and the delay module. The compensation module includes a compensation load and a selection module. The selection module is connected to the compensation load and is used to control the corresponding compensation load to be electrically connected or disconnected from the multiple sub-pixels. The compensation module is used to compensate for the difference in equivalent resistance between the delay load and the first delay load of the first source driver chip of the display panel according to the delay parameter.

9. The source driver chip as described in claim 8, characterized in that, The compensation load includes: At least one of the following: a load resistor connected in series with the delay module and a load capacitor connecting the delay module and ground.

10. An electronic device, characterized in that, It includes a display panel as described in any one of claims 1 to 7, or a source driver chip as described in claim 8 or 9.

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