Methods, systems, and storage devices for performing near-memory computation

Abstract

A method, system, and storage device are provided for performing near-memory computation. The method includes: receiving, at a processor core of the storage device, a request to perform a first function on first data, the first function including a first operation and a second operation; performing the first operation on the first data by a first processor core acceleration engine of the storage device based on first processor core custom instructions to generate first result data; and performing the second operation on the first result data by a first coprocessor acceleration engine of the storage device based on first coprocessor custom instructions.

Description

Technical Field

[0001] Some aspects of embodiments of this disclosure relate to systems and methods for processing formatted data and functions in a computing storage device. Background Technology

[0002] In the field of computer storage devices, a system may include a host and one or more storage devices connected to (e.g., communicatively integrated into) the host. Such computer storage systems have become increasingly popular, partly for allowing many different users to share the system's computing resources. As the number of users of such systems, and the number and complexity of applications running on them, increase, storage requirements grow over time.

[0003] Therefore, there may be a need for methods, systems, and apparatuses suitable for improving the use of storage devices in storage systems.

[0004] This background section is intended to provide context only, and the disclosure of any embodiment or concept in this section does not constitute an admission that the embodiment or concept is prior art. Summary of the Invention

[0005] Some aspects of embodiments of this disclosure relate to computer storage systems and provide improvements to computing storage devices.

[0006] According to some embodiments of this disclosure, a method for performing near-memory computations is provided, the method comprising: receiving at a processor core of a storage device a request to perform a first function on first data, the first function including a first operation and a second operation; performing the first operation on the first data by a first processor core acceleration engine of the storage device based on a first processor core custom instruction to generate first result data; and performing the second operation on the first result data by a first coprocessor acceleration engine of the storage device based on a first coprocessor custom instruction.

[0007] The storage device may be configured to receive the request for performing the first function via a communication protocol; the first processor core custom instructions may cause the first processor core acceleration engine to perform the first operation; and the first coprocessor custom instructions may cause the first coprocessor acceleration engine to perform the second operation.

[0008] The request can be received via an application programming interface (API) integrated into the processor core.

[0009] The method may further include: receiving a request to perform a second function on second data, wherein the second function includes a third operation and a fourth operation, and the processor core stores second processor core custom instructions and second coprocessor custom instructions; the second processor core acceleration engine performs the third operation based on the second processor core custom instructions to generate second result data; and the second coprocessor acceleration engine of the storage device performs the fourth operation on the second result data based on the second coprocessor custom instructions.

[0010] The method may further include: receiving a request to perform a second function on second data, wherein the second function includes a first operation and a third operation, and the processor core stores a second coprocessor custom instruction; the first operation is performed by a first processor core acceleration engine based on the first processor core custom instruction to generate second result data; and the third operation is performed on the second result data by the second coprocessor acceleration engine of the storage device based on the second coprocessor custom instruction.

[0011] The first processor core acceleration engine can be configured to perform acceleration operations associated with the first function, which may include at least one of comparison operations, decoding operations, parsing operations, graph traversal operations, linked list operations, and parallel comparison operations.

[0012] The first coprocessor acceleration engine can be configured to execute a function-specific algorithm associated with the first function, which may include at least one of a compression algorithm, a decompression algorithm, an artificial intelligence (AI) neural network training algorithm, and an AI inference engine algorithm.

[0013] According to one or more other embodiments of this disclosure, a system for performing near-memory computing is provided, the system comprising: a processing unit including a processor core storing first processor core custom instructions and first coprocessor custom instructions and including a first processor core acceleration engine; and a coprocessor including a first coprocessor acceleration engine and coupled to the processor core, wherein the processing unit is configured to: receive a request for performing a first function on first data, the first function including a first operation and a second operation; cause the first processor core acceleration engine to perform the first operation on the first data based on the first processor core custom instructions to generate first result data; and cause the first coprocessor acceleration engine to perform a second operation on the first result data based on the first coprocessor custom instructions.

[0014] The processing unit can be configured to receive the request for performing a first function via a communication protocol; a first processor core custom instruction can cause the first processor core acceleration engine to perform a first operation, and a first coprocessor custom instruction can cause the first coprocessor acceleration engine to perform a second operation.

[0015] The request can be received via an application programming interface (API) integrated into the processor core.

[0016] The processing unit can be configured to: receive a request to perform a second function on second data, wherein the second function includes a third operation and a fourth operation, and the processor core stores second processor core custom instructions and second coprocessor custom instructions; cause the second processor core acceleration engine to perform the third operation based on the second processor core custom instructions to generate second result data; and cause the second coprocessor acceleration engine to perform the fourth operation on the second result data based on the second coprocessor custom instructions.

[0017] The processing unit can be configured to: receive a request to perform a second function on second data, wherein the second function includes a first operation and a third operation, and the processor core stores a second coprocessor custom instruction; cause a first processor core acceleration engine to perform the first operation based on the first processor core custom instruction to generate second result data; and cause the second coprocessor acceleration engine to perform a third operation on the second result data based on the second coprocessor custom instruction.

[0018] The first processor core acceleration engine can be configured to perform acceleration operations associated with the first function, which may include at least one of comparison operations, decoding operations, parsing operations, graph traversal operations, linked list operations, and parallel comparison operations.

[0019] The first coprocessor acceleration engine can be configured to execute a function-specific algorithm associated with the first function, which may include at least one of a compression algorithm, a decompression algorithm, an artificial intelligence (AI) neural network training algorithm, and an AI inference engine algorithm.

[0020] According to one or more other embodiments of this disclosure, a storage device for performing near-memory computation is provided, the storage device comprising: a processing unit including a processor core storing first processor core custom instructions and first coprocessor custom instructions and including a first processor core acceleration engine; and a coprocessor including a first coprocessor acceleration engine and coupled to the processor core, wherein the storage device is configured to: receive a request for performing a first function on first data, the first function including a first operation and a second operation; cause the first processor core acceleration engine to perform the first operation on the first data based on the first processor core custom instructions to generate first result data; and cause the first coprocessor acceleration engine to perform a second operation on the first result data based on the first coprocessor custom instructions.

[0021] The storage device can be configured to receive the request for performing a first function via a communication protocol; a first processor core custom instruction can cause the first processor core acceleration engine to perform a first operation; and a first coprocessor custom instruction can cause the first coprocessor acceleration engine to perform a second operation.

[0022] The request can be received via an application programming interface (API) integrated into the processor core.

[0023] The storage device may be configured to: receive a request to perform a second function on second data, wherein the second function includes a third operation and a fourth operation, and the processor core includes second processor core custom instructions and second coprocessor custom instructions; cause the second processor core acceleration engine to perform the third operation based on the second processor core custom instructions to generate second result data; and cause the second coprocessor acceleration engine to perform the fourth operation on the second result data based on the second coprocessor custom instructions.

[0024] The storage device may be configured to: receive a request to perform a second function on second data, wherein the second function includes a first operation and a third operation, and the processor core stores a second coprocessor custom instruction; cause a first processor core acceleration engine to perform the first operation based on the first processor core custom instruction to generate second result data; and cause the second coprocessor acceleration engine to perform a third operation on the second result data based on the second coprocessor custom instruction.

[0025] The first processor core acceleration engine can be configured to perform acceleration operations associated with the first function, which may include at least one of comparison operations, decoding operations, parsing operations, graph traversal operations, linked list operations, and parallel comparison operations; and the first coprocessor acceleration engine can be configured to perform function-specific algorithms associated with the first function, which may include at least one of compression algorithms, decompression algorithms, artificial intelligence (AI) neural network training algorithms, and AI inference engine algorithms. Attached Figure Description

[0026] Non-limiting and non-exhaustive embodiments of this disclosure are described with reference to the following figures, wherein, unless otherwise stated, the same reference numerals refer to the same parts throughout different views.

[0027] Figure 1A This is a system diagram depicting an architecture for processing formatted data in a computing storage device according to some embodiments of the present disclosure.

[0028] Figure 1B It is a diagram depicting the predefined instructions associated with the example function.

[0029] Figure 1CThis is a diagram depicting custom instructions associated with example functions according to some embodiments of the present disclosure.

[0030] Figure 2 This is a diagram depicting the scheduling of a scanning engine according to some embodiments of the present disclosure.

[0031] Figure 3 This is a system diagram depicting the architecture of a computing storage device for processing various functions according to some embodiments of the present disclosure.

[0032] Figure 4 This is a flowchart depicting a method for processing formatted data in a computing storage device according to some embodiments of the present disclosure.

[0033] Figure 5 This is a flowchart depicting a method for processing various functions in a computing storage device according to some embodiments of the present disclosure.

[0034] Throughout the various views in the accompanying drawings, corresponding reference numerals denote corresponding components. Those skilled in the art will understand that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements, layers, and regions in the drawings may be exaggerated relative to other elements, layers, and regions to aid in the clarity and understanding of the various embodiments. Furthermore, common but easily understood elements and components unrelated to the description of the embodiments may not be shown in order to lessen obstruction of the views of these various embodiments and to make the description clearer. Detailed Implementation

[0035] The aspects of this disclosure and methods of implementing it can be more readily understood by referring to the detailed embodiments and accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may be embodied in various different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects of this disclosure to those skilled in the art. Therefore, descriptions of processes, elements, and techniques that are not essential for a full understanding of the aspects and features of this disclosure by those skilled in the art may be omitted.

[0036] Unless otherwise indicated, the same reference numerals, symbols, or combinations thereof denote the same elements throughout the drawings and written description, and therefore their description will not be repeated. Furthermore, for clarity, parts unrelated to the description of the embodiments may be omitted. In the drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity.

[0037] In the detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the various embodiments. However, it will be clear that various embodiments may be practiced without these specific details or with one or more equivalent arrangements.

[0038] It will be understood that although the terms “zeroth,” “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, first component, first region, first layer, or first portion described below may be referred to as a second element, second component, second region, second layer, or second portion.

[0039] It will be understood that when a component or assembly is referred to as being "on," "connected to," or "joined to" another component or assembly, it may be directly on, directly connected to, or directly joined to the other component or assembly, or there may be one or more intermediate components or assemblies. However, "directly connected / directly joined" refers to a component being directly connected to or joined to another component without any intermediate components. Similarly, other expressions describing relationships between components (such as "between," "immediately between," or "adjacent to" and "closely adjacent to") can be interpreted similarly. Furthermore, it will be understood that when a component or assembly is referred to as being "between" two components or assemblies, it may be the only component or assembly between the two components, or there may be one or more intermediate components or assemblies.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising,” “having,” and “including,” as used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, each of the terms “or” and “and / or” includes any and all combinations of one or more of the associated listed items.

[0041] For the purposes of this disclosure, expressions such as “at least one of…” modify the entire column of elements when following an element in a column, rather than modifying any individual element in the column. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (such as XYZ, XYY, YZ, and ZZ).

[0042] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as terms of approximation rather than terms of degree, and are intended to take into account the inherent biases in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. As used herein, “about” or “approximately” includes the value and indicates an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the value. Furthermore, the use of “may” when describing embodiments of this disclosure refers to “one or more embodiments of this disclosure.”

[0043] When one or more embodiments can be implemented differently, a particular order of processing may be executed differently than the order in which they are described. For example, two consecutively described processes may be executed substantially simultaneously or in the reverse order of their description.

[0044] (For example, in any system diagram included herein) Any component or combination of components described herein may be used to perform one or more of the operations in any flowchart included herein. Furthermore, (i) the operations are merely examples and may include various additional operations not explicitly covered, and (ii) the temporal order of the operations may vary.

[0045] Electronic or electrical devices and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of such devices may be formed on an integrated circuit (IC) chip or a discrete IC chip. Furthermore, various components of such devices may be implemented on a flexible printed circuit film, a tape-on package (TCP), a printed circuit board (PCB), or may be formed on a substrate.

[0046] Furthermore, the various components of these devices can be processes or threads that execute computer program instructions and interact with other system components for performing the various functions described herein, running on one or more processors in one or more computing devices. The computer program instructions are stored in memory, which may be implemented in a computing device using standard memory devices, such as random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Moreover, those skilled in the art will recognize that, without departing from the spirit and scope of the embodiments of this disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0047] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as their meaning in the context of the relevant field and / or in this specification, and shall not be interpreted in an idealized or overly formal sense.

[0048] As described above, in the field of computer storage devices, a system may include a host and one or more storage devices communicatively coupled to the host. The storage devices may be configured to perform functions of an application running on the host. For example, the storage device may be a computational storage device. As used herein, a "computational storage device" is a storage device that includes processing circuitry, in addition to a storage device controller, for performing functions in the vicinity of the memory. The processing circuitry may include (e.g., may be) hardware logic circuitry (e.g., application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs)). The processing circuitry may be configured to perform functions of an application running on the host. For example, the system may be configured to enable the application to select a storage device method for performing functions, rather than a host processor method. For example, because the hardware logic circuitry of the storage device can process data faster than the software logic of the host processor, the storage device method may perform functions more efficiently than the host processor method (or a general-purpose embedded processor method). For example, host processors and general-purpose embedded processors may not be optimal for throughput and power consumption.

[0049] However, in some cases, hardware logic circuitry may not be flexible enough to handle different formats and functions. For example, storage devices have a limited size to accommodate a limited number of different hardware logic circuits. Furthermore, hardware is not as easily modified as software. Therefore, a given storage device may not be able to perform a sufficient number of functions, or may not be able to perform functions for a sufficient number of data formats.

[0050] Some aspects of embodiments of this disclosure provide a storage device that uses a combination of software instructions and a hardware acceleration engine near the memory to accelerate the execution of functions at the storage device, while providing greater flexibility than methods that use only hardware logic circuitry to execute functions at the storage device. Some aspects of embodiments of this disclosure provide improvements and advantages over executing functions using general-purpose host processors or only general-purpose embedded processors (such as faster processing with less power consumption and lower latency). Some aspects of embodiments of this disclosure also provide improvements and advantages over hardware execution of functions in computing storage devices using only specific functions, such as the flexibility to execute more functions for a wider range of data formats.

[0051] Figure 1A This is a system diagram depicting an architecture for processing formatted data in a computing storage device according to some embodiments of the present disclosure.

[0052] Reference Figure 1A System 1 for processing formatted data may include a host 100 and a storage device 200 (e.g., a computing storage device). Host 100 may include a host processor 110 (e.g., a central processing unit (CPU) and / or a graphics processing unit (GPU)). Host 100 and storage device 200 may be associated with system memory 150. For example, system memory 150 may include data stored in system 1 on behalf of users of system 1 (e.g., end users and / or service providers). In some embodiments, host 100 may be external to storage device 200 (e.g., storage device 200 may be remote from host 100). For example, storage device 200 may be a networked device communicatively connected to host 100 via a communication link compatible with one or more of the following protocols: Descriptive State Transfer (REST) ​​ / Inter-Process Communication (IPC) / Remote Procedure Call (RPC) via Non-Volatile Memory Fast (NVMe) / NVMe over Network (NVMe-oF) / Compute Fast Link (CXL) / Peripheral Component Interconnect Fast (PCIe) / Remote Direct Memory Access (RDMA) / Transmission Control Protocol (TCP) / Internet Protocol (IP), etc.

[0053] In some embodiments, system memory 150 may include formatted data. For example, system 1 may provide database page processing for various different data page formats. Database page processing is a function in a computing storage device used to accelerate database scans. As used herein, a "database page" is a data structure that includes fields associated with the type of data in a dataset.

[0054] Because page processing is implemented in hardware (e.g., ASIC, FPGA, etc.), conventional database search acceleration hardware in computing storage devices only supports specific database formats. Therefore, such conventional databases may not be flexible enough to handle requests from a wide variety of users. Furthermore, such conventional databases may lack sufficient adaptability. For example, if the page format changes in the future through a database version update, hardware-based page processing may not support the new page format. Changing the hardware to work with the new page format can be a costly process. As discussed above, in some embodiments of this disclosure, database page processing may be implemented in System 1 to provide flexibility and adaptability for performing database scan acceleration functions.

[0055] Formatted data may include database page 10. For example, system 1 may perform database page processing on a first database page 10a. The first database page 10a may be associated with a first dataset and may have a first format FM1. The first dataset may be data stored representing a specific user. In addition to the first database page 10a, system 1 is also capable of performing database page processing on a second database page 10b. The second database page 10b may be associated with a second dataset and may have a second format FM2. The second dataset may be data stored representing another specific user. The first format FM1 and the second format FM2 may be different formats. For example, the first database page 10a may have a first database page column 14a and a first database page row 12a (e.g., a first tuple). The second database page 10b may have a second database page column 14b and a second database page row 12b (e.g., a second tuple). Figure 1A As can be seen, the rows and columns of the first database page 10a and the second database page 10b may have different formats. System 1 may perform operations (e.g., decoding operations) on the page data PD corresponding to the first database page 10a and / or the second database page 10b to identify relevant data (e.g., relevant data requested by the user).

[0056] In some embodiments, storage device 200 may include processor core 210. Processor core 210 may be coupled to application programming interface (API) 211. Processor core 210 may be coupled to page buffer 212. Although API 211 and page buffer 212 are depicted as being within processor core 210, it should be understood that API 211 and / or page buffer 212 may be external to processor core 210. Processor core 210 may receive requests (e.g., commands or instructions) from host 100 for performing a function FN. Processor core 210 may receive instructions for performing a function FN via API 211. Processor core 210 may receive page data PD via page buffer 212.

[0057] Processor core 210 may include (e.g., storable) a processor core custom instruction set 216. Processor core custom instruction set 216 may include one or more processor core custom instructions. For example, processor core custom instruction set 216 may include one or more processor core custom instructions CI (described as CI1-CIn, where n is a positive integer) respectively. In some embodiments, the processor core custom instructions CI may run on a general-purpose processor portion of processor core 210. For example, processor core 210 may have an architecture including a general-purpose embedded processor (such as an Advanced Reduced Instruction Set Computing (RISC) Machine (ARM) architecture, a RISC-V architecture, or a Tensilica architecture). Processor core 210 may include one or more processor core acceleration engines 240 (described as 240a-240n respectively). Processor core acceleration engine 240 may be hardware circuitry (e.g., a portion of hardware circuitry) for implementing the processor core custom instruction C1. For example, a first processor core custom instruction CI1 may cause a first processor core acceleration engine 240a to perform one or more operations associated with function FN. The second processor core custom instruction CI2 enables the second processor core acceleration engine 240b to perform one or more operations associated with function FN. In some embodiments, the processor core acceleration engine 240 may be used by the storage device 200 to perform generalized (e.g., generic) acceleration operations. For example, the generalized acceleration operations performed by the processor core acceleration engine 240 may be operations common to various functions (e.g., comparison operations, addition operations, subtraction operations, multiplication operations, decoding operations, parsing operations, graph traversal operations, linked list operations, parallel comparison operations, etc.). Each generalized acceleration operation may have a decoding phase, an execution phase, and a write-back phase. For example, in the decoding phase of a comparison operation, the processor core custom instruction CI and / or one or more processor core acceleration engines 240 may decode the instruction to determine that the operation is a comparison operation. In the execution phase, one or more processor core acceleration engines 240 may perform the comparison operation. In the write-back phase, one or more processor core acceleration engines 240 may generate result data for further processing by another component of the storage device 200. For example, in the case of database page processing, the processor core acceleration engine may return column data 243 as result data for further processing.

[0058] As used herein, “custom instruction” refers to a software instruction stored on storage device 200 that is specific to storage device 200 and causes the hardware logic circuitry (e.g., accelerator engine) of storage device 200 to perform operations associated with the requested function.

[0059] Figure 1B It is a diagram depicting the predefined instructions associated with the example function. Figure 1CThis is a diagram depicting custom instructions associated with example functions according to some embodiments of the present disclosure.

[0060] Reference Figure 1B The host processor 110 can be used to execute a function FN based on predefined instructions. For example, a function FN may include a comparison operation for comparing an item A (e.g., the last name "Kim") with one hundred results (e.g., B[0]-B

[99] ) from column B (e.g., a column listing the last names of all employees of the company). Using predefined (e.g., basic) instructions common to general-purpose processors, the host processor 110 (e.g., as a comparator) can execute one hundred predefined comparison operations OP (e.g., CMP1-CMP100) one at a time.

[0061] Reference Figure 1C The processor core acceleration engine 240 of storage device 200 can be used to execute functions FN based on custom instructions CI. For example, the processor core acceleration engine 240 (e.g., as a comparator) can be implemented to process all one hundred operations at once based on a single custom instruction CI operation OP (e.g., comparison custom instruction CI_CMP). Therefore, custom instruction CI can be used to guide the processing of functions within storage device 200, making the functions more efficient than using a general-purpose processor (such as a CPU or GPU). Furthermore, multiple custom instruction CIs can be stored on storage device 200 (e.g., at the general processing portion of processor core 210) to allow for the flexibility of different acceleration engines within storage device 200 to process different operations corresponding to different functions and different data formats.

[0062] Return to reference Figure 1AThe storage device 200 may include a scan engine pool 220. The scan engine pool 220 may include one or more scan engines. For example, the scan engine pool 220 may include a first scan engine 220a and a second scan engine (e.g., an nth scan engine 220n). The scan engines may perform further processing operations on the resulting data generated by the processor core acceleration engine 240. For example, the first scan engine 220a may perform a scan operation on the portion of page data PD corresponding to a first column, and the nth scan engine 220n may perform a scan operation on the portion of page data PD corresponding to an nth column. The scan engines may be external to the processor core 210 and may be referred to as additional processor core circuitry. In some embodiments, additional processor core circuitry may be hardware logic circuitry for performing more complex and / or heavy algorithms (e.g., function-specific acceleration) than the processor core acceleration engine 240. It should be understood that in some embodiments, some hardware logic circuitry for performing function-specific acceleration may be included within the processor core 210. For example, it should be understood that in some embodiments, the circuitry described herein as additional processor core circuitry may not be limited to being located external to the processor core 210.

[0063] Typically, each scan engine is assigned only one column to a database page, or none at all. In some cases, fewer scan engines are used for some scan operations than the total number of scan engines. For example, if there are fewer columns than scan engines, some scan engines may be idle during a scan operation. In some cases, scan engines may not be able to process columns with indexes larger than the number of scan engines.

[0064] To address this problem, in some embodiments of this disclosure, storage device 200 may include scheduler 230 for assigning any scan engines 220a-220n to any column.

[0065] Figure 2 This is a diagram depicting the scheduling of a scanning engine according to some embodiments of the present disclosure.

[0066] Reference Figure 2Scheduler 230 can be used in conjunction with scan engine pool 220 (including scan engines 220a-220f) to improve the efficiency of database page processing. In some embodiments, scheduler 230 can assign any scan engine 220a-220f to any column associated with database page 10 based on computational efficiency rule 232. For example, instead of using only one scan engine per column, scheduler 230 can assign a first scan engine 220a to perform a scan operation on the data corresponding to portion A of the first column 14a1, and can assign another scan engine (e.g., a third scan engine 220c) to perform a scan operation on the data corresponding to portion C of the first column 14a1. Similarly, scheduler 230 can assign a second scan engine 220b to perform a scan operation on the data corresponding to portion B of the second column 14a2, and can assign another scan engine (e.g., a fourth scan engine 220d) to perform a scan operation on the data corresponding to portion D of the second column 14a2.

[0067] Return to reference Figure 1A In some embodiments, storage device 200 may include local memory 250. Local memory 250 may be used to store page data PDs (e.g., PDa-PDn) corresponding to different formats for later processing. Local memory 250 may include non-volatile memory.

[0068] Therefore, database page processing according to some embodiments of this disclosure may include one or more of the following operations. Host 100 may send a request (e.g., a command or instruction) to storage device 200 to perform a function FN on page data PD associated with a first database page 10a having a first format FM1. Function FN may be a scanning function. A scanning function may include multiple operations (e.g., a scanning function may be performed through multiple smaller operations). For example, a scanning function may include a decoding operation and a comparison operation.

[0069] Storage device 200 may receive a request via API 211 to execute function FN at processor core 210. Storage device 200 may receive page data PD associated with first database page 10a at page buffer 212. Storage device 200 may use processor core custom instruction set 216 to direct the execution of decoding and comparison operations to different processing circuits within storage device 200. For example, first processor core custom instruction CI1 may cause first processor core acceleration engine 240a to perform a decoding operation to determine a first format FM1 from the page data PD corresponding to the first database page 10a. First processor core acceleration engine 240a may generate result data based on first processor core custom instruction CI1. For example, first processor core acceleration engine 240a (or another processor core acceleration engine 240) may extract column data 243 from page data PD based on the decoding operation. In some embodiments, first processor core acceleration engine 240a (or one or more other processor core acceleration engines 240) may perform page rule checking operations (e.g., to verify page data).

[0070] The first processor core custom instruction CI1 can also cause additional processor core circuitry (e.g., the first scan engine 220a) to perform a comparison operation based on column data 243 (e.g., on column data 243). Additionally, the scheduler 230 can cause the first scan engine 220a to perform the comparison operation in conjunction with the nth scan engine 220n to improve efficiency.

[0071] Figure 3 This is a system diagram depicting the architecture of a computing storage device for processing various functions according to some embodiments of the present disclosure.

[0072] Reference Figure 3 The storage device 200 according to some embodiments of the present disclosure enables the flexibility to process various functions in the vicinity of memory. In such embodiments, the storage device may include a coprocessor 310. The coprocessor 310 may be incorporated into the processor core 210 and may include one or more coprocessor acceleration engines 340 (e.g., depicted as 340a-340n respectively). The processor core 210 and the coprocessor 310 may correspond to the processing unit 300 of the storage device 200. The coprocessor acceleration engine 340 may correspond to a coprocessor custom instruction set 316. The coprocessor custom instruction set 316 may include one or more coprocessor custom instructions CCI (e.g., depicted as CCI1-CCIn respectively). In some embodiments, the coprocessor custom instruction set 316 may be stored in the processor core 210 (e.g., at the general processing portion of the processor core 210).

[0073] As mentioned above Figure 1AThe processor core acceleration engine 240 discussed herein can be used by the storage device 200 to perform generalized (e.g., generic) acceleration operations. For example, the generalized acceleration operations performed by the processor core acceleration engine 240 can be operations common to various functions (e.g., comparison operations, addition operations, subtraction operations, multiplication operations, decoding operations, graph traversal operations, linked list operations, parallel comparison operations, etc.). Each generalized acceleration operation can have a decoding phase, an execution phase, and a write-back phase.

[0074] Similar to the above about Figure 1A The additional processor core circuitry discussed (e.g., a scanning engine), the coprocessor acceleration engine 340 can be hardware logic circuitry used in conjunction with the coprocessor custom instruction set 316 to execute more complex and / or heavy algorithms (e.g., feature-specific acceleration) than the processor core acceleration engine 240. For example, the coprocessor acceleration engine 240 could be a larger acceleration engine capable of executing complex algorithms (such as compression algorithms, decompression algorithms, artificial intelligence (AI) neural network training algorithms, and AI inference engine algorithms).

[0075] In some embodiments, storage device 200 may include a data transfer bus 350 for transferring information between host 100, processor core 210, and coprocessor 310. For example, data transfer bus 350 may transfer requests, commands, instructions, results, and status updates between components of system 1. In some embodiments, data transfer bus 350 may include (e.g., an Advanced Extensible Interface (AXI) architecture.

[0076] Therefore, the processing (e.g., execution) of various functions according to some embodiments of this disclosure may include one or more of the following operations. Host 100 may send a request (e.g., a command or instruction) to storage device 200 to perform function FN on data 30. Function FN may be a first function FN1. For example, first function FN1 may be a video processing function. First function FN1 may include multiple operations (e.g., the video processing function may be performed through multiple smaller operations). For example, first function FN1 may include simple accelerated operations common to multiple functions associated with storage device 200, and may include function-specific operations. Processor core 210 may receive a request to perform first function FN1 via data transfer bus 350 and / or API 211. Processor core 210 may receive data 30 via data transfer bus 350 and / or data buffer 312.

[0077] As mentioned above Figure 1ASimilarly, storage device 200 can use processor core custom instruction set 216 to direct the execution of operations associated with the first function FN1 to different processing circuits within storage device 200. For example, the first processor core custom instruction CI1 can cause one or more of the processor core acceleration engines 240 to perform a first operation associated with the first function FN1 on data 30. The processor core acceleration engine 240 can generate processor core result data 245 based on the first processor core custom instruction CI1. Similarly, storage device 200 can use coprocessor custom instruction set 316 to direct the execution of operations associated with the first function FN1 to different coprocessor acceleration engines 340. For example, the first coprocessor custom instruction CCI1 can cause the first coprocessor acceleration engine 340a to perform a second operation associated with the first function FN1 based on the processor core result data 245 (e.g., on the processor core result data 245) to generate coprocessor result data 345. The coprocessor result data 345 can be sent to processor core 210 or data transfer bus 350 for further processing.

[0078] Similarly, host 100 may send instructions to storage device 200 to perform a second function FN2 on data 30. Data 30 may be the same data as or different from the data 30 on which the first function FN1 is performed. For example, the second function FN2 may be a compression function. The second function FN2 may include multiple operations (e.g., the compression function may be performed through multiple smaller operations). For example, the second function FN2 may include simple acceleration operations common to multiple functions associated with storage device 200, and may include function-specific operations. For example, one or more operations associated with the first function FN1 (e.g., one or more generalized acceleration operations) may also be associated with the second function FN2, and one or more operations (e.g., one or more function-specific operations) may not be associated with the first function FN1. Processor core 210 may receive instructions for performing the second function FN2 via data transfer bus 350 and / or API 211. Processor core 210 may receive data 30 via data transfer bus 350 and / or data buffer 312.

[0079] As discussed above with respect to the first function FN1, the storage device 200 can use the processor core custom instruction set 216 to direct the execution of operations associated with the second function FN2 to different processing circuits within the storage device 200. For example, the second processor core custom instruction CI2 can cause one or more of the processor core acceleration engines 240 to perform a first operation associated with the second function F2 on data 30. The processor core acceleration engine 240 can generate processor core result data 245 based on the second processor core custom instruction CI2. Similarly, the storage device 200 can use the coprocessor custom instruction set 316 to direct the execution of operations associated with the second function FN2 to different coprocessor acceleration engines 340. For example, the second coprocessor custom instruction CCI2 can cause the second coprocessor acceleration engine 340b to perform a second operation associated with the second function FN2 based on the processor core result data 245 (e.g., on the processor core result data 245) to generate coprocessor result data 345. The coprocessor result data 345 can be sent to the processor core 210 or the data transfer bus 350 for further processing.

[0080] Figure 4 This is a flowchart depicting a method for processing formatted data in a computing storage device according to some embodiments of the present disclosure.

[0081] Reference Figure 4 The method 4000 for processing formatted data in a computing storage device may include the following example operations. Storage device 200 may receive first data (e.g., page data PD) associated with a first dataset and having a first format FM1 (see...). Figure 1A (Operation 4001). The processor core 210 of the storage device 200 may receive from the host 100 a request (e.g., a command or instruction) for performing a function FN on the first data (Operation 4002). The first processor core acceleration engine 240a may perform a first operation associated with the function FN on the first data based on the first processor core custom instruction CI1 to generate first result data (e.g., column data 243) (Operation 4003). The first scan engine 220a of the storage device 200 may perform a second operation associated with the function FN on the first result data (e.g., column data 243) based on the first processor core custom instruction CI1 (Operation 4004).

[0082] Figure 5 This is a flowchart depicting a method for processing various functions in a computing storage device according to some embodiments of the present disclosure.

[0083] Reference Figure 5The method 5000 for processing various functions in a computing storage device may include the following example operations. The processor core 210 of the storage device 200 may receive a request (e.g., a command or instruction) for performing a first function FN1 on first data (operation 5001). A first processor core acceleration engine 240a may perform a first operation associated with the first function FN1 on the first data based on a first processor core custom instruction CI1 to generate first result data (e.g., processor core result data 245) (operation 5002). A first coprocessor acceleration engine 340a of the storage device 200 may perform a second operation associated with the first function FN1 on the first result data (e.g., processor core result data 245) based on a first coprocessor custom instruction CCI1 (operation 5003).

[0084] The disclosed example embodiments can be extended without limitation to the following statements:

[0085] Statement 1. An example method includes: receiving at a processor core of a storage device a request to perform a first function on first data, the first function including a first operation and a second operation; performing the first operation on the first data by a first processor core acceleration engine of the storage device based on a first processor core custom instruction to generate first result data; and performing the second operation on the first result data by a first coprocessor acceleration engine of the storage device based on a first coprocessor custom instruction.

[0086] Statement 2. An example method includes the method of Statement 1, wherein a storage device is configured to receive, via a communication protocol, a request for performing a first function; a first processor core custom instruction causes a first processor core acceleration engine to perform a first operation; and a first coprocessor custom instruction causes a first coprocessor acceleration engine to perform a second operation.

[0087] Statement 3. An example method includes any one of Statements 1 and 2, wherein the request is received via an Application Programming Interface (API) incorporated into the processor core.

[0088] Statement 4. An example method includes the method of any one of Statements 1-3, and further includes: receiving a request to perform a second function on second data, wherein the second function includes a third operation and a fourth operation, and the processor core stores second processor core custom instructions and second coprocessor custom instructions; performing the third operation by a second processor core acceleration engine based on the second processor core custom instructions to generate second result data; and performing the fourth operation on the second result data by a second coprocessor acceleration engine of the storage device based on the second coprocessor custom instructions.

[0089] Statement 5. An example method includes the method of any one of Statements 1-3, and further includes: receiving a request to perform a second function on second data, wherein the second function includes a first operation and a third operation, and a processor core stores second coprocessor custom instructions; performing the first operation by a first processor core acceleration engine based on the first processor core custom instructions to generate second result data; and performing the third operation on the second result data by a second coprocessor acceleration engine of the storage device based on the second coprocessor custom instructions.

[0090] Statement 6. An example method includes the method of any one of statements 1-5, wherein a first processor core acceleration engine is configured to perform an acceleration operation associated with a first function, the acceleration operation including at least one of a comparison operation, a decoding operation, a parsing operation, a graph traversal operation, a linked list operation, and a parallel comparison operation.

[0091] Statement 7. An example method includes the method of any one of Statements 1-6, wherein the first coprocessor acceleration engine is configured to execute a function-specific algorithm associated with a first function, the function-specific algorithm including at least one of a compression algorithm, a decompression algorithm, an artificial intelligence (AI) neural network training algorithm, and an AI inference engine algorithm.

[0092] Statement 8. An example system for performing the method of any one of Statements 1-7 includes: a processing unit including a processor core storing first processor core custom instructions and first coprocessor custom instructions and including a first processor core acceleration engine; and a coprocessor including the first coprocessor acceleration engine and coupled to the processor core.

[0093] Statement 9. An example storage device for performing the method of any one of Statements 1-7 includes: a processing unit including a processor core storing first processor core custom instructions and first coprocessor custom instructions and including a first processor core acceleration engine; and a coprocessor including the first coprocessor acceleration engine and coupled to the processor core.

[0094] While embodiments of the present disclosure have been specifically shown and described with reference to the examples described herein, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the disclosure as set forth in the appended claims and their equivalents.

Claims

1. A method for performing near-memory computation, the method comprising: The processor core of the storage device receives a request to perform a first function on first data, the first function including a first operation and a second operation; The first processor core acceleration engine of the storage device performs a first operation on the first data based on the first processor core's custom instructions to generate first result data; as well as The first coprocessor acceleration engine of the storage device performs a second operation on the first result data based on custom instructions from the first coprocessor. The first operation is an acceleration operation associated with the first function, and The second operation is a more complex algorithm than the first operation.

2. The method according to claim 1, wherein: The storage device is configured to receive the request for performing the first function via a communication protocol; The first processor core's custom instructions cause the first processor core's acceleration engine to perform the first operation; and The first coprocessor custom instruction causes the first coprocessor acceleration engine to perform the second operation.

3. The method according to claim 1, wherein, The request is received via an application programming interface (API) that is integrated into the processor core.

4. The method according to claim 1, further comprising: Receive a request to perform a second function on second data, wherein the second function includes a third operation and a fourth operation, and the processor core stores second processor core custom instructions and second coprocessor custom instructions; The second processor core acceleration engine executes a third operation based on custom instructions from the second processor core to generate second result data; and The second coprocessor acceleration engine of the storage device performs a fourth operation on the second result data based on custom instructions of the second coprocessor.

5. The method according to claim 1, further comprising: Receive a request to perform a second function on second data, wherein the second function includes a first operation and a third operation, and the processor core stores second coprocessor custom instructions; The first processor core acceleration engine executes a first operation based on custom instructions from the first processor core to generate second result data; and The second coprocessor acceleration engine of the storage device performs a third operation on the second result data based on custom instructions of the second coprocessor.

6. The method according to claim 1, wherein, Accelerated operations include at least one of the following: comparison operations, decoding operations, parsing operations, graph traversal operations, linked list operations, and parallel comparison operations.

7. The method according to claim 1, wherein, The second operation is a function-specific algorithm associated with the first function, which includes at least one of a compression algorithm, a decompression algorithm, an artificial intelligence (AI) neural network training algorithm, and an AI inference engine algorithm.

8. A system for performing near-memory computation, the system comprising: The processing unit includes a processor core, which stores first processor core custom instructions and first coprocessor custom instructions, and includes a first processor core acceleration engine. as well as A coprocessor, including a first coprocessor acceleration engine and integrated into a processor core, wherein the processing unit is configured as follows: Receive a request to perform a first function on first data, the first function including a first operation and a second operation; The first processor core acceleration engine performs a first operation on the first data based on a custom instruction of the first processor core to generate first result data; and The first coprocessor acceleration engine performs a second operation on the first result data based on custom instructions from the first coprocessor. The first operation is an acceleration operation associated with the first function, and The second operation is a more complex algorithm than the first operation.

9. The system according to claim 8, wherein: The processing unit is configured to receive the request for performing the first function via a communication protocol; The first processor core's custom instructions cause the first processor core's acceleration engine to execute the first operation, and The first coprocessor custom instruction causes the first coprocessor acceleration engine to perform the second operation.

10. The system according to claim 8, wherein, The request is received via an application programming interface (API) that is integrated into the processor core.

11. The system according to claim 8, wherein, The processing unit is configured as follows: Receive a request to perform a second function on second data, wherein the second function includes a third operation and a fourth operation, and the processor core stores second processor core custom instructions and second coprocessor custom instructions; The second processor core acceleration engine executes a third operation based on custom instructions from the second processor core to generate second result data; and The second coprocessor acceleration engine performs a fourth operation on the second result data based on custom instructions from the second coprocessor.

12. The system according to claim 8, wherein, The processing unit is configured as follows: Receive a request to perform a second function on second data, wherein the second function includes a first operation and a third operation, and the processor core stores second coprocessor custom instructions; The first processor core acceleration engine executes a first operation based on custom instructions from the first processor core to generate second result data; and The second coprocessor acceleration engine performs a third operation on the second result data based on custom instructions from the second coprocessor.

13. The system according to claim 8, wherein, Accelerated operations include at least one of the following: comparison operations, decoding operations, parsing operations, graph traversal operations, linked list operations, and parallel comparison operations.

14. The system according to claim 8, wherein, The second operation is a function-specific algorithm associated with the first function, which includes at least one of a compression algorithm, a decompression algorithm, an artificial intelligence (AI) neural network training algorithm, and an AI inference engine algorithm.

15. A storage device for performing near-memory computation, the storage device comprising: The processing unit includes a processor core, which stores first processor core custom instructions and first coprocessor custom instructions, and includes a first processor core acceleration engine. as well as A coprocessor, including a first coprocessor acceleration engine and integrated into a processor core, wherein the storage device is configured as follows: Receive a request to perform a first function on first data, the first function including a first operation and a second operation; The first processor core acceleration engine performs a first operation on the first data based on the first processor core's custom instructions to generate the first result data; and The first coprocessor acceleration engine performs a second operation on the first result data based on custom instructions from the first coprocessor. The first operation is an acceleration operation associated with the first function, and The second operation is a more complex algorithm than the first operation.

16. The storage device according to claim 15, wherein: The storage device is configured to receive, via a communication protocol, the request for performing the first function; The first processor core's custom instructions cause the first processor core's acceleration engine to perform the first operation; and The first coprocessor custom instruction causes the first coprocessor acceleration engine to perform the second operation.

17. The storage device according to claim 15, wherein, The request is received via an application programming interface (API) that is integrated into the processor core.

18. The storage device according to claim 15, configured as follows: Receive a request to perform a second function on the second data, wherein, The second function includes the third and fourth operations; and the processor core includes second processor core custom instructions and second coprocessor custom instructions; The second processor core acceleration engine executes a third operation based on custom instructions from the second processor core to generate second result data; and The second coprocessor acceleration engine performs a fourth operation on the second result data based on custom instructions from the second coprocessor.

19. The storage device according to claim 15, configured as follows: Receive a request to perform a second function on the second data, wherein, The second function includes the first operation and the third operation, and the processor core stores custom instructions for the second coprocessor; The first processor core acceleration engine executes a first operation based on custom instructions of the first processor core to generate second result data; and The second coprocessor acceleration engine performs a third operation on the second result data based on custom instructions from the second coprocessor.

20. The storage device according to claim 15, wherein: Accelerated operations include at least one of the following: comparison operations, decoding operations, parsing operations, graph traversal operations, linked list operations, and parallel comparison operations; and The second operation is a function-specific algorithm associated with the first function, which includes at least one of a compression algorithm, a decompression algorithm, an artificial intelligence (AI) neural network training algorithm, and an AI inference engine algorithm.

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