Hybrid rate interface to reduce power consumption and area in high speed DACs and digital transmitters

Abstract

A mixed-rate interface to reduce power consumption and area in high-speed DACs and digital transmitters. A system includes a port to receive a number of bits at a first frequency. One or more cells generate signals for a channel at a channel frequency that is N times the first frequency. The cells transmit at a second frequency that is M times the first frequency but less than the channel frequency. Interface links are coupled between a portion of the input bits of the port and the one or more cells and the portion of the input bits are encoded by T thermometer-coded bits such that each of the T bits is encoded by M repeated parallel bits having a value of the respective T bit. Each interface link includes M interface lines between each T bit and each first cell, and M is less than N to reduce a number of interface lines for the T bits.

Description

Technical Field

[0001] This description generally relates to digital-to-analog converters, and more specifically to interfaces for high-speed digital-to-analog converters. Background Technology

[0002] High-speed digital-to-analog converters (DACs) and digital transmitters have large interfaces between the DAC's digital input ports and the analog radio frequency (RF) band. These large interfaces occupy a significant area and consume substantial power. There is a strong desire for smaller interfaces that consume less power. Summary of the Invention

[0003] On one hand, this disclosure provides a system comprising: a port configured to receive input bits at a first frequency; one or more first units configured to transmit at a second frequency that is N times the first frequency; one or more first interface links coupled between a first portion of the input bits and the one or more first units, wherein each input bit of the first portion is encoded by N repeating parallel bits having a value of the corresponding input bit, and each first interface link includes N parallel interface lines between the N repeating parallel bits of each input bit of the first portion and each first unit; and one or more second units configured to receive input bits at a first frequency that is N times the first frequency. The signal is transmitted at a third frequency that is M times the first frequency; and one or more second interface links are coupled between a second portion of the input bit and the one or more second units, wherein the second portion of the input bit is encoded by T bits of thermometer encoding, wherein each of the T bits is encoded by M repeating parallel bits, and wherein each second interface link includes M parallel interface lines between the M repeating parallel bits of each T bit and each second unit, wherein M is less than N and greater than or equal to one, to reduce the number of interface lines for each bit of the second portion of the input bit compared to the first portion of the input bit.

[0004] On the other hand, this disclosure provides a system comprising: a port including a plurality of input bits, wherein the port is configured to receive the input bits at a first frequency; one or more first units configured to generate a signal for a channel at a channel frequency that is N times the first frequency, wherein N is greater than one, wherein the one or more first units are configured to transmit at a second frequency that is M times the first frequency and the second frequency is less than the channel frequency; and one or more first interface links coupled between a first portion of the input bits of the port and the one or more first units, wherein the first portion of the input bits is encoded by T bits of thermometer encoding, wherein each of the T bits is encoded by M repeating parallel bits having a value of the corresponding T bits, wherein each first interface link includes M interface lines between each T bit and each first unit, and wherein M is less than N to reduce the number of interface lines for the T bits.

[0005] On the other hand, this disclosure provides a system comprising: a port including a first binary coded bit and a second thermometer coded bit, wherein the port is configured to receive the first binary coded bit and the second thermometer coded bit at a first frequency; a first unit configured to transmit at a second frequency that is N times the first frequency, wherein N is greater than one; a first interface link coupled between the first binary coded bit and the first unit, wherein the first binary coded bit is encoded by N repeating parallel bits having values ​​of corresponding input bits and the first interface link includes N interface lines between the first binary coded bit and the first unit; a second unit configured to transmit at a third frequency that is M times the first frequency, wherein M is greater than or equal to one; and a second interface link coupled between the second thermometer coded bit and the second unit, wherein the second thermometer coded bit is encoded by T bits of thermometer encoding, wherein each of the T bits is encoded by M repeating parallel bits having values ​​of the second thermometer coded bit, wherein the second interface link includes M interface lines between the M repeating parallel bits and the second unit, and wherein M is less than N to reduce the area used by the second interface link compared to the first interface link. Attached Figure Description

[0006] The appended claims set forth certain features of the subject matter. However, for purposes of explanation, several aspects of the subject matter are depicted in the following figures.

[0007] Figure 1 This describes digital-to-analog converters based on various aspects of the subject technology.

[0008] Figure 2 This describes digital-to-analog converters based on various aspects of the subject technology.

[0009] Figure 3A and 3B This section describes the digital-to-analog converter based on various aspects of the subject technology.

[0010] Figure 4A , 4B And the 4C description includes a chart of sampled values ​​for each aspect of the subject technology. Detailed Implementation

[0011] The detailed description presented below is intended as a description of various configurations of the subject matter technology and is not intended to represent the only configuration in which the subject matter technology can be practiced. The accompanying drawings are incorporated herein and form part of the detailed description, which contains specific details for providing a thorough understanding of the subject matter technology. However, the subject matter technology is not limited to the specific details set forth herein and can be practiced without one or more specific details. In some instances, structures and components are shown in block diagram form to avoid obscuring the concepts of the subject matter technology.

[0012] When an element is referred to herein as “connected” or “coupled” to another element, it should be understood that the element may be directly connected to said other element, or that there may be an intermediary element present between the elements. Conversely, when an element is referred to as “directly connected” or “directly coupled” to another element, it should be understood that there is no intermediary element in a “direct” connection between the elements. However, the presence of a direct connection does not preclude the existence of other connections in which intermediary elements may be present.

[0013] In a high-speed digital-to-analog converter (DAC), the digital input segment (containing the DAC's input ports) that provides the digital signal can operate at clock frequencies ranging from several hundred MHz to several GHz, for example, between approximately 200 MHz and 10 GHz. However, the analog segment at the DAC's output port can be N times faster, where N is an integer greater than one. Therefore, the analog segment speed can be approximately 16 GHz. In some embodiments, the DAC receives 13-bit signal samples to convert to an analog signal. Of these 13 bits, the first 7 bits (bit 0 to bit 6), e.g., the least significant bit (LSB), switch more frequently than the last 6 bits (bit 7 to bit 12), i.e., the most significant bit (MSB). Furthermore, the MSB has a greater impact on the amplitude of the analog signal; for example, it has a greater effect on changing the amplitude of the analog signal compared to the LSB. Therefore, the first 7 LSBs are represented as binary bits. The 6MSB may not change as quickly as the LSB, but the MSB has a greater impact on signal changes, and therefore, the use of MSB thermometer encoding is less prone to errors and noise compared to LSB. For example, 64 bits are used for thermometer encoding 6MSB. In binary coded bits, the value of a bit changes from one position to the next in powers of 2. However, the values ​​of bits in binary coded bits are equal and each has twice the value of the largest binary bit.

[0014] In some embodiments, thermometer codewords encoded with thermometers are used, which have at most a single transition between bits in each codeword, such that the codeword is either entirely zero or entirely one. If the codeword is a mixture of zeros and ones, then only a single bit in the codeword transitions between one and zero. As described, the analog segment speed can be approximately 16 GHz. Therefore, each bit is represented as 16 bits of the same value (e.g., repeated), and these 16 bits are transmitted from the digital segment of the DAC to the analog segment via 16 interface lines, which are then serialized for transmission. As discussed, each input bit of the DAC has 71 bits, which are 7 binary bits and 64 thermometer bits, such as T bits, and each bit has 16 interface lines. Therefore, there are a total of 1136 interface lines per input bit of the DAC. This number doubles if both in-phase and quadrature signals are used. Therefore, a large area (e.g., substrate area or silicon area) is used to fabricate the interface lines on the DAC chip, and a large amount of power is also used to transmit signals in the interface lines.

[0015] The following paragraphs present methods and structures for reducing the number of interface lines, thereby saving area and power. Thermometer encoding for MSB is less prone to errors and noise compared to LSB using binary bits. In some embodiments, the T-bit or at least a subset of the T-bits changes more slowly than the binary bits of the LSB and can be transmitted at lower frequencies. In some embodiments, each T-bit is represented by fewer than 16 bits, for example, through repetition. For example, the T-bit is represented (e.g., encoded) by M repeating parallel bits of the same value, where M is an integer greater than or equal to one, and is 8 bits, 4 bits, 2 bits, or 1 bit. Therefore, M interface lines are used between the M parallel bits and each DAC unit (e.g., each unit) instead of 16 interface lines. The M parallel interface lines are 8 interface lines, 4 interface lines, 2 interface lines, or 1 interface line, which saves area and power compared to the interface lines used for LSB binary bits. Therefore, the T-bits are transmitted at 8 GHz, 4 GHz, 2 GHz, or 1 GHz, respectively.

[0016] In some embodiments, portions of the T-bits that switch more frequently (e.g., at a frequency comparable to that in binary bits) are transmitted at 16 GHz, while the remaining T-bits are transmitted at a lower speed. In some embodiments, depending on how fast the T-bits change, the T-bits are divided into more than two portions, for example, into four portions. The first portion of the T-bits is transmitted at 16 GHz, the second portion at 8 GHz, the third portion at 4 GHz, and the fourth portion at 1 GHz, and each portion is implemented with 16 interface lines, 8 interface lines, 4 interface lines, and one interface line, respectively.

[0017] In some embodiments, each DAC unit of the digital-to-analog converter (DAC) performs two tasks and generates an analog signal to be transmitted in a communication channel. In some embodiments, the channel frequency is higher than the digital segment frequency, and the digital input bits at the DAC's input ports are generated at a digital segment frequency that is slower than the channel frequency. In some embodiments, each DAC unit is coupled to multiple parallel bits via parallel lines and receives multiple bits at the slower digital segment frequency, for example, simultaneously receiving N parallel bits. As a first task, each DAC includes a serializer, such as a serializer module, which stacks N parallel bits one after another to generate a single serialized signal that is N times the digital segment frequency. In some embodiments, N is the ratio of the channel frequency to the digital segment frequency, and therefore, the single serialized signal is matched to the channel frequency and transmitted through the channel. As a second task, each DAC unit includes a signal generator that provides a communication signal from the single serialized signal for transmission in a communication channel to which each DAC unit can be attached.

[0018] In some embodiments, an interface link is provided between the digital input bits of the digital-to-analog converter (DAC) and each DAC unit. Since each interface link contains N parallel interface lines, the DAC unit receives N parallel bits simultaneously. In some embodiments, each bit of the digital input of the DAC is connected to only one DAC unit via a separate interface link. Therefore, to match the digital segment frequency with the channel frequency, each bit is repeated N times at the input port of the DAC, or N consecutive data of each bit are stored at the input port of the DAC, and the N bits are sent to each DAC unit via an interface link containing N interface lines. Thus, the DAC includes multiple DAC units, such that each DAC unit has a one-to-one connection to each bit of the DAC's input port. Each DAC unit is coupled only to the corresponding bit of the DAC's input port via a separate interface link of the DAC. In some embodiments, the digital segment containing the input segment of the interface system is limited in terms of the data frequency provided to the interface system; for example, the digital segment frequency is limited to 1 gigabits per second (Gbps) as the frequency of the provided digital bits. In some embodiments, the analog segment frequency is several times the frequency of the digital segment, for example, 16 times. Therefore, in some embodiments, parallelism is required to transmit bits from the input port to the DAC unit. In some embodiments, the analog transmitter (e.g., an analog signal generator) in the DAC unit does not receive parallel data, and therefore, the parallel data on the interface line is serialized into a single signal before being sent to the transmitter.

[0019] Figure 1 This describes the interface system 100 for digital-to-analog converters based on various aspects of the subject technology. Figure 1An input port 102 (e.g., a DAC input port) with multiple bits (e.g., input bits) is shown. The input bits of input port 102 can be divided into two groups. The first group is the most significant bit (MSB) in the MSB segment 114 of input port 102. The second group is the least significant bit (LSB) in the LSB segment 112. In some embodiments, the input bits of input port 102 are the locations where digital signals (e.g., multiple bits of a digital signal) are delivered to the DAC. The input bits of input port 102 are combinations of bits in the MSB segment and bits in the LSB segment. In some embodiments, the number of input bits of input port 102 is between 8 and 48 bits. In some embodiments, the number of input bits of input port 102 is 12, 13, 16, or 24. In some embodiments, the number of input bits is 13, the MSB segment has between 4 and 8 bits, and the LSB segment has between 5 and 9 bits. The value of LSB segment 112 is transmitted as binary bits in register 116 via interface 105. In some embodiments, because LSB segment 112 also contains bits, interface 105 is a direct bit mapping between LSB segment 112 and register 116. As shown, bits in MSB segment 114 are transmitted via interface 106 and encoded using a thermometer to form T bits in register 118. In some embodiments, LSB segment 112 contains 7 bits and register 116 also contains 7 bits. In some embodiments, MSB segment contains 6 bits and register 118 contains T bits, such as 64 bits. In some embodiments, interface 105 performs two's complement in the mapping between LSB segment 112 and register 116 to manage negative values.

[0020] like Figure 1 As shown, register 116 is coupled to DAC unit 140 via interface link 202 (e.g., interface lines). As discussed, because register 116 contains binary bits, each bit of register 116 is represented by 16 parallel bits, and interface link 202 contains N parallel interface lines, for example, N is 16. As shown, Figure 1It also includes a digital input segment 201, which contains an input port 102, register 116, and register 118. Register 118 contains a first portion of T bits in segment 118A of register 118, which are T bits transmitted at a lower frequency of 8 GHz, 4 GHz, 2 GHz, or 1 GHz. The first portion of T bits in segment 118A uses M interface lines in the interface link 210 between register 118 and DAC unit 142, such as 8 interface lines, 4 interface lines, 2 interface lines, or 1 interface line. The second portion of T bits in segment 118B of register 118 contains T bits transmitted at a channel frequency of 16 GHz. Therefore, each interface link 208 (e.g., the interface line of interface link 208) coupled to each bit of segment 118B and DAC unit 145 receives data from 16 repeating bits corresponding to the bit of segment 118B. DAC units 140, 142, and 145 generate corresponding waveforms for transmission. DAC units 140 and 145 generate waveforms transmitted via transmitters 122 and 124 at full rate, such as a channel frequency of 16 GHz. DAC unit 142 generates waveforms transmitted via transmitter 120 at partial rate, such as 8 GHz, 4 GHz, 2 GHz, or 1 GHz, or half rate, such as 8 GHz. Therefore, for DAC units 140 or 145, each bit is represented by N repeating parallel bits, for example, encoded. For DAC unit 142, each unit is represented by M repeating parallel bits (for example, encoded), where M is an integer greater than or equal to one and less than N. In some embodiments, N is 16, and M is 8, 4, 2, or 1. Therefore, for the T bits of segment 118A, the number of interface lines is M / N times, for example, 1 / 2, 1 / 4, 1 / 8, or 1 / 16 times, compared to the number of interface lines for the T bits of segment 118B or the binary bits of register 116. Furthermore, for the T bits of segment 118A, approximately M / N times, such as 1 / 2, 1 / 4, 1 / 8, or 1 / 16 times, of the substrate area is used compared to the substrate area used for the T bits of segment 118B or the binary bits of register 116.

[0021] Figure 2 This describes the interface system 200 for digital-to-analog converters based on various aspects of the subject technology. Figure 2 Similar to Figure 1 This allows digital input segment 201 to include input ports 102, such as DAC input ports, registers 116 and 118, and interfaces 105 and 106. DAC unit 140 receives 16 bits per bit of register 116 via 16 interface links 202. DAC unit 145 receives 16 bits per bit of segment 118B of register 118 via 16 interface links 208. Therefore, register 116 represents binary bits, where each bit is repeated N times and encoded by N repeating parallel bits of the same value, said bits being transmitted to DAC unit 140 via N interface lines 212.

[0022] like Figure 2 As shown, interface links 202 and 208 have three or more interface lines 212, and interface link 210 has one or more interface lines 212. Additionally, digital input segment 201 includes and displays a repeating bit 215 of a single binary bit in register 116, for example, N repeating input bits. The repeating bit 215 has the same value as the corresponding binary bit in register 116. The repeating bit 215 is a representation of the corresponding binary bit in register 116 and can be used simultaneously for the corresponding binary bit, and therefore the repeating bit 215 can be a parallel bit. Digital input segment 201 also includes and displays a repeating bit 225 of a single T bit in segment 118B of register 118. The repeating bit 225 has the same value as the corresponding T bit in segment 118B. The repeating bit 225 can be used simultaneously as a representation of the corresponding T bit in segment 118B, and therefore the repeating bit 225 can be a parallel bit.

[0023] For each bit of segment 118A of register 118, DAC unit 142 receives 8 bits, 4 bits, 2 bits, or 1 bit via 8, 4, 2, or one interface link 210. As shown, DAC unit 140 includes a serializer 232 that serializes 16 bits of 16 interface lines and converts the serialized 16 bits into an analog signal 136 via signal generator 204. DAC unit 145 also includes a serializer 232 that serializes 16 bits of 16 interface lines and converts the serialized 16 bits into an analog signal 137 via signal generator 204. DAC unit 142 may further include a serializer 234 that serializes 8, 4, 2, or 1 bits of 8, 4, 2, or 1 interface lines of interface link 210 and converts the serialized 16 bits (e.g., 16 serialized repeating parallel bits) into an analog signal 138 via signal generator 206. In some embodiments, when there is only one interface line, there is no serializer in DAC unit 142. In some embodiments, one or more interface links 210 (e.g., two interface links 210) are coupled to one or more DAC units 142 to generate the analog signal 138.

[0024] Figure 3A and 3BThe sections 300 and 350 of the digital-to-analog converter according to various aspects of the subject matter are described. As shown, 13 bits (e.g., input bits) of input port 102 are transmitted via interface 302. The first portion 7 of the LSB is selected by selector 310 and transmitted as signal 328 via interface 304. In some embodiments, controller 320 determines the number of binary bits (e.g., binary encoded bits) and T bits (e.g., thermometer encoded bits) and instructs selector 310 to divide them. As shown, 6MSBs from bit number 7 to bit number 12 are routed to downsampler 305 via interface 306. The downsampler selects 6MSBs every other sample and transmits them via interface 312 to thermometer encoder 325. The thermometer encoder 325 generates 64T bits. T bits are transmitted via interface 318 to selector 301. Selector 301 selects the first 58 bits of the T bits and transmits them as signal 326, which are transmitted at half rate, e.g., half the channel frequency. In some embodiments, a rate half that of the full channel frequency is expected. In some embodiments, selector 301 selects more or less than 58 bits. In some embodiments, downsampler 305 downsamples the value of T bits at N / M, where N is 16 and M is 8, 4, or 2.

[0025] The 6MSBs from bits 7 to 12 are also guided via interface 306 to incremental calculator 315, which calculates the difference between the values ​​of the 6MSB samples, such as the difference between sample 1 and sample 2 with a put for position 1, the difference between sample 3 and sample 4 with a put for position 3, and so on. The difference signal is transmitted via interface 308 to interpolator 330. The interpolator adds zeros to the difference signal, making positions 2, 4, etc., zero. This generates a zero-fill signal, which is transmitted via interface 314 to thermometer encoder 321, which is identical to thermometer encoder 325, and generates a thermometer code. The thermometer code is then sent via interface 316 to combiner 335, which combines the signal from thermometer encoder 321 with the last 6 bits of T bits (bits 58 to 63) generated by thermometer encoder 325 and received via interface 322. Combiner 335 generates a signal 324 with 6 bits from T bits 58 to 63, which is the thermometer code of the difference between each two points. Therefore, signal 324 has the last 6 bits of the thermometer code generated by thermometer encoder 325, with the difference between each two samples (represented by the thermometer code) placed between T bits 58 to 63.

[0026] Figure 3B Similar to Figure 3A The difference is Figure 3BThe signal 323 contains an averaging and combining unit 337 instead of a combining unit 335. Signal 323 is similar to signal 324; however, instead of T digits 58 to 63, it is represented by a thermometer of the average of two adjacent samples (e.g., consecutive samples) and there is the same difference between the averages as in signal 324.

[0027] Figure 4A , 4B And the 4C description includes a chart of sampled values ​​for each aspect of the subject technology. Figure 4A exhibit Figure 3A and 3B The graph 420 shows the value of signal 326 at coordinate 402 and the sampling point at coordinate 404. (See graph 420 for example.) Figure 3A and 3B As shown, the signal content can be transmitted at half rate. Furthermore, as... Figure 4A As shown in the figure, every two consecutive values ​​are the same. Figure 4B and 4C Charts 440 and 460 show the values ​​at coordinate 402 and the sampling points at coordinate 404, respectively. Figure 4B exhibit Figure 3A The value of signal 323, where zero is between every two points, makes signal 323 a full-rate signal. Figure 4C Display and Figure 3A and 3B The signal has 328 identical binary bits, and is therefore a full-rate signal.

[0028] The technologies discussed above reduce the number of interface lines in the DAC, save area on the DAC chip, and save power consumption without attenuating the generated analog signal.

[0029] According to an aspect of the subject matter, a system includes a port for receiving input bits at a first frequency. The system includes one or more first units for transmitting at a second frequency that is N times the first frequency. The system further includes one or more first interface links coupled between a first portion of the input bit and the one or more first units, such that each input bit of the first portion is encoded by N repeating parallel bits having a value for the corresponding input bit, and each first interface link includes N parallel interface lines between the N repeating parallel bits of each input bit of the first portion and each first unit. The system further includes: one or more second units for transmitting at a third frequency that is M times the first frequency; and one or more second interface links coupled between a second portion of the input bit and the one or more second units. The second portion of the input bit is encoded by T bits of thermometer encoding, such that each of the T bits is encoded by M repeating parallel bits, and each second interface link includes M parallel interface lines between the M repeating parallel bits of each T bit and each second unit, where M is less than N and greater than or equal to one. M is selected to reduce the number of interface lines for each bit of the second portion of the input bits compared to the first portion of the input bits.

[0030] In terms of the subject matter, N equals 16, and the first portion of the input bits is binary encoded such that each bit is encoded by 16 repeating parallel bits, such that each first interface link is coupled between the 16 repeating parallel bits and each first unit. In terms of the subject matter, the input bits comprise 13 bits, the first portion comprises 7 bits, and the second portion comprises 6 bits. In terms of the subject matter, the T bits encoded by the thermometer contain at most one transition between the T bits, and the second portion comprises 6 bits and the T bits encoded by the thermometer are 64. In terms of the subject matter, each first unit includes a serializer for serializing N repeating parallel bits. In terms of the subject matter, each first unit includes a signal generator that generates an analog signal from the serialized N repeating parallel bits at the second frequency. In terms of the subject matter, the first portion contains the least significant input bit, and the second portion contains the most significant input bit of the port.

[0031] According to an aspect of the subject matter, a system includes: a port comprising a plurality of input bits and receiving the input bits at a first frequency; and one or more first units for generating a signal for a channel at a frequency N times the first frequency and a second frequency less than the channel frequency. The one or more first units transmit at a second frequency M times the first frequency and a second frequency less than the channel frequency. The system further includes one or more first interface links coupled to a first portion of the input bits of the port and the one or more first units. The first portion of the input bits is encoded by T bits of thermometer encoding, such that each of the T bits is represented by M repeating parallel bits. Each first interface link includes M parallel interface lines between each of the T bits and each first unit, where M is determined as a fraction of N to reduce the number of interface lines for the T bits.

[0032] In terms of the subject matter, the first frequency is 1 GHz, the channel frequency is 16 GHz, and the second frequency is between 4 GHz and 8 GHz, and each first interface link includes 4 or 8 interface lines. In terms of the subject matter, the system further includes: one or more second units for transmitting at the channel frequency; and one or more second interface links coupled between two or more bits of the input bit of the port, where each of the two or more bits is a binary coded bit represented by N repeating parallel bits, and each second interface link includes N parallel interface lines between the N repeating parallel bits of each thermometer coded bit and each second unit. In terms of the subject matter, the input bit includes 13 bits, the first portion includes 5 bits, and the two or more bits include 8 bits. In terms of the subject matter, each first unit includes a signal generator for generating an analog signal from M serialized parallel bits at the second frequency. In terms of the subject matter, the first portion includes the most significant bit. In terms of the subject matter, T equals 64 and M equals one.

[0033] According to an aspect of the subject matter, a system includes a port comprising a first binary coded bit and a second thermometer coded bit. The port receives the first binary coded bit and the second thermometer coded bit at a first frequency. The system further includes a first unit for transmitting at a second frequency that is N times the first frequency, where N is an integer greater than one. The system further includes a first interface link coupled between the first binary coded bit and the first unit. The first binary coded bit is represented by N repeated parallel bits, and the first interface link includes N parallel interface lines between the first binary coded bit and the first unit. A second unit transmits at a third frequency that is M times the first frequency, where M is an integer greater than or equal to one. The system further includes a second interface link coupled between the second thermometer coded bit and the second unit, where the second thermometer coded bit is represented by T bits of thermometer encoding, such that each of the T bits is represented by M repeated parallel bits. The second interface link includes M parallel interface lines between the M repeated parallel bits and the second unit, where M is a fraction of N to reduce the area used by the second interface link compared to the first interface link.

[0034] In terms of the subject matter, the system further includes two or more thermometer coded bits, which include the second thermometer coded bit. The number of T bits is a power of 2 of the total number of thermometer coded bits. In terms of the subject matter, the values ​​of the T bits are downsampled at N / M. In terms of the subject matter, the system further includes two or more binary coded bits, which include the first binary coded bit. The total number of binary coded bits and thermometer coded bits is 13. In terms of the subject matter, N is 16 and M is 2, and the system receives the two or more binary coded bits and the two or more thermometer coded bits at 1 GHz. The binary coded bits are transmitted at 16 GHz and the thermometer coded bits are transmitted at 2 GHz. In terms of the subject matter, the two or more binary coded bits are transmitted at the channel frequency and the T bits are transmitted at a multiple of M / N of the channel frequency. For the T bits, compared to the two or more binary coded bits, an interface line of M / N times is used and an power and area of ​​M / N times are used.

[0035] Those skilled in the art will appreciate that the various illustrative blocks, modules, elements, components, memory systems, and algorithms described herein can be implemented as electronic hardware, computer software, or a combination of both. To illustrate this hardware-software interchangeability, the various illustrative blocks, modules, elements, components, memory systems, and algorithms have been described above in general terms of their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application. Various components and blocks can be arranged differently (e.g., in different orders or divided in different ways) without departing from the scope of this art.

[0036] It should be understood that any particular order or hierarchy of blocks in the disclosed process is an illustration of the instance method. Based on design preferences, it should be understood that the particular order or hierarchy of blocks in the process may be rearranged, or all described blocks may be executed. Any of the blocks may be executed simultaneously. In one or more embodiments, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the embodiments described above should not be construed as requiring this separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together as a single software product or packaged as multiple software products.

[0037] As used in this specification and any claims of this application, the terms "base station," "receiver," "computer," "server," "processor," and "memory" all refer to electronic devices or other technical devices. These terms exclude persons or groups of people. For the purposes of this specification, the terms "display" or "showing" mean displaying on an electronic device.

[0038] As used herein, the phrase “at least one of…” preceding a series of items (where the terms “and” or “or” are used to separate any one of the items) modifies the entire list, not each member of the list (i.e., each item). The phrase “at least one of…” does not require selection of at least one of every listed items; rather, the phrase allows for the meaning of at least one of any of the items and / or at least one of any combination of items and / or at least one of each of the items. By example, the phrases “at least one of A, B, and C” or “at least one of A, B, or C” respectively refer to only A, only B, or only C; any combination of A, B, and C; and / or at least one of each of A, B, and C.

[0039] The predicates “configured to,” “operable to,” and “programmed to” do not imply any specific tangible or intangible modification of the subject; rather, they are intended to be used interchangeably. In one or more embodiments, “processor configured to monitor and control operation” or “component” may also mean that the processor is programmed to monitor and control operation or that the processor is operable to monitor and control operation. Similarly, “processor configured to execute code” can be interpreted as “processor programmed to execute code” or “operable to execute code.”

[0040] For example, phrases such as "aspect," "the aspect," "on the other hand," "some aspects," "one or more aspects," "implementation," "the implementation," "another implementation," "some implementations," "one or more implementations," "embodiment," "the embodiment," "another embodiment," "some embodiments," "one or more embodiments," "configuration," "the configuration," "another configuration," "some configurations," "one or more configurations," "inventive technology," "invention," "this invention," and other variations are used for convenience and do not imply that the disclosure associated with such phrases is necessary for the present technology or that such disclosure applies to all configurations of the present technology. The disclosure associated with such phrases may apply to all configurations or one or more configurations. The disclosure associated with such phrases may provide one or more instances. For example, the phrase "one aspect" or "some aspects" may refer to one or more aspects, and vice versa, and this similarly applies to other foregoing phrases.

[0041] The term “exemplary” is used herein to mean “serving as an example, illustration, or description.” Any embodiment described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, within the scope of the terms “comprising,” “having,” or the like as used in the description or claims, this term is intended to be interpreted in a manner similar to how the term “comprising” is interpreted when used as a transitional word in the claims.

[0042] All structural and functional equivalents of the elements throughout the various aspects described herein, known or hereafter known to a person skilled in the art, are clearly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be made public, regardless of whether it is expressly stated in the claims. No element of the claims should be construed in accordance with 35 U.S.SC §112(f) unless the element is clearly described using the phrase “component for…” or, in the case of a memory system claim, using the phrase “step for…”.

[0043] The preceding description is provided to enable those skilled in the art to practice the various aspects described herein. Those skilled in the art will readily understand various modifications to these aspects, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects presented herein, but rather to be given the full scope consistent with the language of the claims, wherein, unless expressly stated, elements referenced in the singular do not necessarily mean "one and only one," but rather "one or more." Unless specifically stated otherwise, the term "some" refers to one or more. Masculine pronouns (e.g., his) include feminine and neutral pronouns (e.g., her and its), and vice versa. Headings and subheadings (if present) are used for convenience only and do not limit this disclosure.

Claims

1. A system comprising: A port configured to receive input bits at a first frequency; One or more first units are configured to transmit at a second frequency that is N times the first frequency; One or more first interface links coupled between a first portion of the input bits and one or more first units, wherein each input bit of the first portion is encoded by N repeating parallel bits having a value of the corresponding input bit, and each first interface link includes N parallel interface lines between the N repeating parallel bits of each input bit of the first portion and each first unit. One or more second units configured to transmit at a third frequency that is M times the first frequency; and One or more second interface links coupled between a second portion of the input bit and the one or more second units, wherein the second portion of the input bit is encoded by T bits of thermometer encoding, wherein each of the T bits is encoded by M repeating parallel bits, and wherein each second interface link includes M parallel interface lines between the M repeating parallel bits of each T bit and each second unit, wherein M is less than N and greater than or equal to one, to reduce the number of interface lines for each bit of the second portion of the input bit compared to the first portion of the input bit.

2. The system of claim 1, wherein N equals 16, wherein the first portion of the input bits is binary encoded such that each bit is encoded by 16 repeating parallel bits, wherein each first interface link is coupled between the 16 repeating parallel bits and each first unit.

3. The system of claim 1, wherein the input bits comprise 13 bits, the first portion comprises 7 bits, and the second portion comprises 6 bits.

4. The system of claim 1, wherein the T bits of the thermometer code include at most one transition between the T bits, and wherein the second portion includes 6 bits and the T bits of the thermometer code are 64.

5. The system of claim 1, wherein each first unit includes a serializer configured to serialize N repeating parallel bits.

6. The system of claim 5, wherein each first unit includes a signal generator configured to generate an analog signal from the serialized N repeating parallel bits at the second frequency.

7. The system of claim 1, wherein the first portion includes the least significant input bit of the port, and the second portion includes the most significant input bit of the port.

8. A system comprising: A port including a plurality of input bits, wherein the port is configured to receive the input bits at a first frequency; One or more first units configured to generate a signal for a channel at a channel frequency that is N times the first frequency, where N is greater than one, wherein the one or more first units are configured to transmit at a second frequency that is M times the first frequency and the second frequency is less than the channel frequency; and One or more first interface links coupled between a first portion of the input bit of the port and the one or more first units, wherein the first portion of the input bit is encoded by T bits of thermometer encoding, wherein each of the T bits is encoded by M repeating parallel bits having a value of the corresponding T bit, wherein each first interface link includes M interface lines between each T bit and each first unit, and wherein M is less than N to reduce the number of interface lines for the T bits.

9. The system of claim 8, wherein the first frequency is 1 GHz, the channel frequency is 16 GHz, and the second frequency is 4 GHz or 8 GHz, and wherein each first interface link includes 4 or 8 interface lines.

10. The system of claim 8, further comprising: One or more second units configured to transmit at the channel frequency; and One or more second interface links coupled between two or more bits of the input bit of the port and the one or more second units, wherein each of the two or more bits is a binary coded bit and is encoded by N repeating parallel bits having the value of the corresponding input bit, and each second interface link includes N interface lines between the N repeating parallel bits of each binary coded bit and each second unit.

11. The system of claim 10, wherein the input bits comprise 13 bits, the first portion comprises 5 bits, and the two or more bits comprise 8 bits.

12. The system of claim 8, wherein each first unit includes a signal generator configured to generate an analog signal from M serialized parallel bits at the second frequency.

13. The system of claim 8, wherein the first portion includes the most significant bit of the input bit.

14. The system of claim 8, wherein T equals 64 and M equals one.

15. A system comprising: A port, comprising a first binary coded bit and a second thermometer coded bit, wherein the port is configured to receive the first binary coded bit and the second thermometer coded bit at a first frequency; The first unit is configured to transmit at a second frequency that is N times the first frequency, where N is greater than one; A first interface link is coupled between the first binary encoded bit and the first unit, wherein the first binary encoded bit is encoded by N repeating parallel bits having values ​​of corresponding input bits and the first interface link includes N interface lines between the first binary encoded bit and the first unit. The second unit is configured to transmit at a third frequency that is M times the first frequency, where M is greater than or equal to one; and A second interface link is coupled between the second thermometer encoding bit and the second unit, wherein the second thermometer encoding bit is encoded by T bits of thermometer encoding, wherein each of the T bits is encoded by M repeating parallel bits having the value of the second thermometer encoding bit, wherein the second interface link includes M interface lines between the M repeating parallel bits and the second unit, and wherein M is less than N to reduce the area used by the second interface link compared to the first interface link.

16. The system of claim 15, further comprising: Two or more thermometer code bits, which include the second thermometer code bit, wherein the number of T bits is a power of 2 of the total number of thermometer code bits.

17. The system of claim 16, wherein the values ​​of the T bits are downsampled in N / M order.

18. The system of claim 16, further comprising: Two or more binary code bits, which include the first binary code bit, wherein the total number of binary code bits and thermometer code bits is 13.

19. The system of claim 18, wherein N is 16 and M is 2, and wherein the system receives the two or more binary coded bits and the two or more thermometer coded bits at 1 GHz, transmits the binary coded bits at 16 GHz, and transmits the thermometer coded bits at 2 GHz.

20. The system of claim 18, wherein the two or more binary coded bits are transmitted at a channel frequency and the T bits are transmitted at M / N times the channel frequency, and wherein for the T bits, an interface line of M / N times the power and area are used compared to the two or more binary coded bits.

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