Optimized pixel design for mitigating MIM image lag

Abstract

The present disclosure relates to an optimized pixel design for mitigating MIM image lag. A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a pixel voltage source and the floating diffusion. A lateral overflow integration capacitor LOFIC network includes: a first LOFIC coupled between the floating diffusion and a first bias voltage source; and a second LOFIC coupled between the floating diffusion and a second bias voltage source. At the end of an integration period, the first LOFIC is configured to be forward biased and the second LOFIC is configured to be reverse biased, and during a readout period, the image charge discharged from the first LOFIC and the image charge discharged from the second LOFIC compensate each other.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors, and particularly, but not exclusively, to high dynamic range (HDR) complementary metal oxide semiconductor (CMOS) image sensors. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cell phones, security cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range) through both device architecture design and image acquisition processing. The technology used to manufacture image sensors has continued to advance rapidly. For example, the demand for higher resolution and lower power consumption has driven further miniaturization and integration of these devices.

[0003] A typical image sensor operates in response to image light from an external scene incident on the image sensor. The image sensor includes a pixel array having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate an image charge upon absorbing the image light. The image charge generated by the pixel light can be measured as an analog output image signal on a column bit line, which varies as a function of the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out from the column bit line as an analog image signal and converted into a digital value to produce a digital image (e.g., image data) representing the external scene. The analog image signals on the bit lines are coupled to a readout circuit that includes an input stage having an analog / digital conversion (ADC) circuit to convert those analog image signals from the pixel array into digital image signals. Summary of the invention

[0004] In one aspect, the present disclosure relates to a pixel circuit comprising: a photodiode configured to photogenerate one or more image charges in response to incident light; a floating diffusion coupled to receive the one or more image charges from the photodiode; a transfer transistor coupled between the photodiode and the floating diffusion to transfer the one or more image charges from the photodiode to the floating diffusion; a reset transistor coupled between a pixel voltage source and the floating diffusion, wherein the reset transistor is configured to switch in response to a reset control signal; a lateral overflow integration capacitor (LOICC); An LOFIC IC) network is provided, which is coupled to the floating diffusion, a first bias voltage source and a second bias voltage source, the LOFIC network comprising: a first LOFIC, which is coupled between the floating diffusion and the first bias voltage source; and a second LOFIC, which is coupled between the floating diffusion and the second bias voltage source; wherein at the end of an integration period, the first LOFIC is configured to be forward biased, and the second LOFIC is configured to be reverse biased, and wherein during a readout period, charges released from the first LOFIC and charges released from the second LOFIC compensate each other.

[0005] In another aspect, the present disclosure relates to a method of operating a pixel circuit, comprising: during an integration period - photogenerating image charge in a photodiode in response to incident light; when the photodiode is saturated, transferring at least one overflow image charge from the photodiode to a lateral overflow integration capacitor (LOFIC) network of the pixel circuit, wherein the LOFIC network comprises a first LOFIC coupled between a floating diffusion and a first bias voltage source and a second LOFIC coupled between the floating diffusion and a second bias voltage source; at an end of the integration period, configuring the first bias voltage source to be at a first low voltage so that the first LOFIC is forward biased; and at an end of the integration period, configuring the second bias voltage source to be at a second low voltage so that the second LOFIC is reverse biased; and during a readout period - configuring the first LOFIC and the second LOFIC to scale the image charge, wherein the image charge released from the first LOFIC and the image charge released from the second LOFIC compensate each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0007] Figure 1 An example of an imaging system including a pixel array according to the teachings of the present disclosure is illustrated.

[0008] Figure 2 Illustrated is a schematic diagram of an exemplary pixel circuit including a lateral overflow integration capacitor (LOFIC) in accordance with the teachings of the present disclosure.

[0009] Figure 3 Illustrated is a timing diagram of an exemplary pixel circuit including a LOFIC according to the teachings of the present disclosure.

[0010] Figures 4A to 4D Illustrated are bias changes of a LOFIC included in an exemplary pixel circuit during idle and integration periods in accordance with the teachings of the present disclosure.

[0011] Figure 5 Illustrated is a schematic diagram of an exemplary pixel circuit including a LOFIC according to the teachings of the present disclosure.

[0012] Figure 6 Illustrated is a timing diagram of an exemplary pixel circuit including a LOFIC according to the teachings of the present disclosure.

[0013] Figures 7A to 7B Illustrated are bias changes of a LOFIC included in an exemplary pixel circuit during idle and integration periods in accordance with the teachings of the present disclosure.

[0014] Throughout the several views of the drawings, corresponding reference numerals indicate corresponding components. Those skilled in the art will appreciate that the elements in the various figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the various figures may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present disclosure. In addition, common but well-known elements that are useful or necessary in commercially feasible embodiments are generally not depicted in order to facilitate less obstructed viewing of these various embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] Examples are disclosed for imaging systems with pixel circuits including lateral overflow integrating capacitors (LOFICs) that provide reduced metal-insulator-metal (MIM) induced image lag. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, one skilled in the art will recognize that the techniques described herein may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0016] References throughout this specification to "one example" or "one embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the example is included in at least one example of the present disclosure. Therefore, the appearances of the phrase "in one example" or "in one embodiment" in various places throughout the specification do not necessarily all refer to the same example. Furthermore, in one or more examples, particular features, structures, or characteristics may be combined in any suitable manner.

[0017] For ease of description, spatially relative terms (e.g., "below," "below," "above," "below," "above," "upper," "top," "bottom," "left," "right," "center," "middle," etc.) may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the various figures. It should be understood that, in addition to the orientations depicted in the various figures, spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the various figures is rotated or flipped, the element described as being "below" or "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" may encompass orientations above and below. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly. In addition, it should also be understood that when an element is referred to as being "between" two other elements, the element may be the only element between the two other elements, or one or more intermediate elements may also be present.

[0018] Throughout this specification, several terms are used. These terms will assume their ordinary meaning in the art to which they belong, unless otherwise specifically defined herein or the context in which they are used clearly implies otherwise. It should be noted that in this document, component names and symbols are used interchangeably (e.g., Si and silicon); however, both have the same meaning.

[0019] As will be discussed, various examples of imaging systems having pixel circuits including lateral overflow integration capacitors (LOFICs) are disclosed that provide a reduction in metal-insulator-metal (MIM) induced image lag. It should be appreciated that the LOFIC may be included in a pixel circuit to increase the full well capacity of the pixel circuit, and thereby increase the high dynamic range capability of the corresponding image sensor. The LOFIC capacitance is positively correlated to the full well capacity. Therefore, as the capacitance of the LOFIC employed in the pixel circuit increases, the full well capacity of the pixel circuit also increases. For this reason, a high LOFIC capacitance is typically required. However, due to the large RC load as the capacitance of the LOFIC increases, the time required for the row driver of the imaging system to charge and / or reset the LOFIC increases. Therefore, as the capacitance of the LOFIC in the pixel circuit increases, the image lag also increases, which causes the frame rate to slow down.

[0020] It should be understood that the image hysteresis caused by LOFIC may be associated with the high dielectric constant or high-k materials included in the insulating materials of the MIM LOFIC due to the hysteresis characteristics and slow relaxation behavior of high-k materials. The relaxation behavior of high dielectric constant materials can cause image quality degradation, such as image hysteresis, due to various mechanisms including trap-to-trap tunneling, structural relaxation, coupling with phonon energy, etc.

[0021] Some imaging systems include pixel circuits each having a LOFIC that is configured to be reverse biased during idle periods. This compensates or eliminates residual charge in the LOFIC to reduce the LOFIC discharge time and thereby reduce image lag. However, this approach may lead to other problems such as dark image non-uniformity (DINU).

[0022] Thus, as will be shown and described in the various examples below, an exemplary pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion to transfer image charge from the photodiode to the floating diffusion. A reset transistor is coupled between the pixel voltage source and the floating diffusion. A lateral overflow integrating capacitor (LOFIC) network is coupled to the floating diffusion, a first bias voltage source, and a second bias voltage source. The LOFIC network includes a first LOFIC coupled between the floating diffusion and the first bias voltage source and a second LOFIC coupled between the floating diffusion and the second bias voltage source. At the end of the integration period, the first LOFIC is configured to be forward biased and the second LOFIC is configured to be reverse biased, and during the readout period, the image charge released from the first LOFIC and the image charge released from the second LOFIC compensate for each other.

[0023] In various examples, each of the first LOFIC and the second LOFIC is a metal-insulator-metal (MIM) storage capacitor, the MIM storage capacitor including a high-k material disposed between a first metal electrode and a second metal electrode. In various examples, the high-k material may be formed of a single layer or a multi-layer stack of high-k insulating materials. In various examples, the high-k material may include one of aluminum oxide (Al2O3), zirconium dioxide (ZrO2), hafnium oxide (HfO), or a combination thereof.

[0024] For illustration purposes, Figure 1 An example of an imaging system 100 having a readout circuit 106 according to the teachings of the present disclosure is shown. In particular, Figure 1 The example depicted in the diagram illustrates an imaging system 100 including a pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and function logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array including a plurality of pixel circuits 104 (e.g., Pl, P2, ..., Pn) arranged in rows (e.g., Rl to Ry) and columns (e.g., Cl to Cx) to acquire image data of a person, place, object, etc., which can then be used to reproduce an image of the person, place, object, etc. In various examples, at least one of the plurality of pixel circuits 104 (e.g., Pl, P2, ..., Pn) includes the aforementioned LOFIC network circuitry.

[0025] In various examples, readout circuitry 106 may be configured to read out image signals via column bit lines 112. As will be discussed, in various examples, readout circuitry 106 may include an analog-to-digital converter (ADC) 107 in accordance with the teachings of the present disclosure. In the examples described, the digital image data values ​​produced by analog-to-digital converter 107 in readout circuitry 106 may then be received by function logic 108. Function logic 108 may simply store the digital image data or even manipulate the digital image data by applying post-process image effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or others).

[0026] In one example, control circuit 110 is coupled to pixel array 102 to control the operation of a plurality of photodiodes in pixel array 102. For example, control circuit 110 may generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with a lighting effect such as a flash.

[0027] In one example, the imaging system 100 is implemented on a single semiconductor wafer. In another example, the imaging system 100 is located on a stacked semiconductor wafer. For example, the pixel array 102 may be implemented on a pixel wafer, while the readout circuit 106, the control circuit 110, and the functional logic may be implemented on an application specific integrated circuit (ASIC) wafer, wherein the pixel wafer and the ASIC wafer are interconnected by bonding (hybrid bonding, oxide bonding, etc.) or by one or more through substrate vias (TSVs). In another example, the pixel array 102 and the control circuit 110 are implemented on a pixel wafer, while the readout circuit 106 and the functional logic 108 are implemented on an ASIC wafer, wherein the pixel wafer and the ASIC wafer are stacked and interconnected by bonding (hybrid bonding, oxide bonding, etc.) or by one or more TSVs.

[0028] In one example, the imaging system 100 may be included in a digital camera, a cell phone, a laptop computer, an endoscope, a security camera, an imaging device for a head mounted display device, or an imaging device for an automobile, etc. In addition, the imaging system 100 may be coupled to other pieces of hardware, such as a processor (general purpose or otherwise), a memory element, an output (USB port, wireless transmitter, HDMI port, etc.), a light / flash, an electrical input (keyboard, touch display, track pad, mouse, microphone, etc.), and / or a display. The other pieces of hardware may deliver instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate image data provided by the imaging system 100.

[0029] Figure 2 A schematic diagram of an exemplary pixel circuit 204 including a lateral overflow integration capacitor (LOFIC) 254 is illustrated in accordance with the teachings of the present disclosure. It should be appreciated that Figure 2 The pixel circuit 204 may be included in Figure 1 0 and 1. The example of pixel circuitry 104 in imaging system 100 is shown in FIG. 1, and similarly named and numbered elements described above are similarly coupled and function below.

[0030] In the illustrated example, the pixel circuit 204 includes a photodiode 214 configured to photogenerate image charge in response to incident light. A first floating diffusion FD1 218 is coupled to receive image charge from the photodiode 214. A transfer transistor TX 216 is coupled between the photodiode 214 and the first floating diffusion FD1 218 to transfer image charge from the photodiode 214 to the first floating diffusion FD1 218. A reset transistor RST 234 is coupled between a pixel voltage source pixel VDD 260 and the first floating diffusion FD1 218. A lateral overflow gate transistor LFG 230 is coupled between the reset transistor RST 234 and the first floating diffusion FD1 218. A dual floating diffusion transistor DFD 224 is coupled between the lateral overflow gate transistor LFG 230 and the first floating diffusion FD1 218. A second floating diffusion FD2 228 is coupled between the lateral overflow gate transistor LFG 230 and the dual floating diffusion transistor DFD 224. Floating diffusion capacitor FDC 229 is coupled to second floating diffusion FD2 228. Source follower transistor SF 220 is coupled between pixel voltage source VDD 260 and row select transistor RS 222, which is coupled to a bit line (eg, Figure 1 The gate terminal of the source follower transistor SF 220 is coupled to the first floating diffusion FD1 218.

[0031] Transfer transistor TX 216 is configured to switch in response to transfer control signal TX 236. Reset transistor RST 234 is configured to switch in response to reset control signal RST 244 and is configured to reset pixel circuit 204 during, for example, idle periods, precharge periods, and between image signal and reset signal readouts. Dual floating diffusion transistor DFD 224 is configured to switch in response to dual floating diffusion control signal DFD 238 and is configured to transfer image charge from first floating diffusion FD1 218 to second floating diffusion FD2 228, thereby allowing image charge to overflow from photodiode 214 to second floating diffusion FD2 228 through first floating diffusion FD1 218 when photodiode 214 is saturated. Lateral overflow gate transistor LFG 230 is configured to switch in response to lateral overflow gate control signal LFG 242. Row select transistor RS222 is configured to switch in response to row select control signal RS246 and is configured to transfer the signal from source follower transistor SF 220 to the bit line. It should be appreciated that pixel circuit 204 may include fewer, additional and / or alternative components (e.g., transistors, capacitors, buffers, switches) depending on the specific requirements of the imaging system.

[0032] The pixel circuit 204 further includes a lateral overflow integrating capacitor (LOFIC) network 250 coupled to the first floating diffusion FD1 218, the first bias voltage source Vcap-1 248-1, and the second bias voltage source Vcap-2 248-2. In the illustrated example, the LOFIC network 250 is coupled to a node between the reset transistor RST 234 and the lateral overflow gate transistor LFG 230. The LOFIC network 250 may include a first LOFIC CAP1 254-1 coupled between the first floating diffusion FD1 218 and the first bias voltage source Vcap-1 248-1 and a second LOFIC CAP2 254-2 coupled between the first floating diffusion FD1 218 and the second bias voltage source Vcap-2 248-2. The lateral overflow gate transistor LFG 230 is configured (e.g., by appropriate gate biasing using the lateral overflow gate control signal LFG 242) to transfer overflow charge from the second floating diffusion FD2 228 to the first LOFIC CAP1 254-1 or the second LOFIC CAP2 254-2. The LOFIC network 250 may further include a first voltage buffer 252-1 coupled between the first LOFIC 254-1 and the first bias voltage source Vcap-1 248-1 and a second voltage buffer 252-2 coupled between the second LOFIC 254-2 and the second bias voltage source Vcap-2 248-2.

[0033] It should be appreciated that each LOFIC 254-1, 254-2 includes a first metal electrode, which may be referred to as a capacitor top metal (CTM), and a second metal electrode, which may be referred to as a capacitor bottom metal (CBM). As such, the CTM of the first LOFIC 254-1 is coupled to the first voltage buffer 252-1 at node A, the CTM of the second LOFIC 254-2 is coupled to the second voltage buffer 252-2 at node B, and the CBMs of the first LOFIC 254-1 and the second LOFIC 254-2 are coupled to the lateral overflow gate transistor LFG 230 at node C. It should be appreciated that the first bias voltage source Vcap-1 248-1 and the second bias voltage source Vcap-2 248-2 may be configured to forward bias, zero bias, or reverse bias the first LOFIC 254-1 and the second LOFIC 254-2, respectively, by adjusting the voltage values ​​at nodes A and B to be higher, equal to, or lower than the voltage value at node C. In some embodiments, the control circuit (e.g., Figure 12) may include circuitry that modulates the voltage levels supplied by the first bias voltage source Vcap-1 248-1 and the second bias voltage source Vcap-2 248-2. In some embodiments, the first bias voltage source Vcap-1 248-1 and the second bias voltage source Vcap-2 248-2 may be included on an ASIC die, while the control circuit is included on a pixel die. In other embodiments, the first bias voltage source Vcap-1 248-1 and the second bias voltage source Vcap-2 248-2 may be included on an ASIC die with the control circuit.

[0034] Figure 3 A timing diagram illustrating an exemplary pixel circuit including a LOFIC according to the teachings of the present disclosure is illustrated. It should be understood that Figure 3 The timing diagram can be as follows Figure 2 , and similarly named and numbered elements described above are similarly coupled and function below.

[0035] In the illustrated example, the timing diagram includes an idle period, a precharge period, an integration period, and a readout period. The idle period can be arranged between the readout period of the previous frame and the precharge period of the current frame. The timing diagram depicts the pixel voltage source pixel VDD 360, the reset control signal RST 344, the first bias voltage source Vcap-1 348-1, the second bias voltage source Vcap-2 348-2, the CTM of the first LOFIC (e.g., in Figure 2 354a, the CTM of the second LOFIC (e.g., at node B) 354b, and the CBM of the first and second LOFICs (e.g., at node C) 354c. In the illustrated example, the pixel voltage source pixel VDD 360 is configured to remain at a constant non-zero value (e.g., ranging from 2.8V to 3.6V) throughout the entire timing diagram.

[0036] The voltage values ​​at CTM(A) 354a and CTM(B) 354b may be controlled by adjusting the voltage levels provided by the first bias voltage source Vcap-1 348-1 and the second bias voltage source Vcap-2 348-2, respectively, and by using buffers (e.g., the first voltage buffer 252-1 and the second voltage buffer 252-2). The voltage value at CBM(C) 354c may vary depending on the overflow charge flowing from the photodiode (e.g., flowing from the photodiode 214 and passing through the lateral overflow gate transistor LFG 230 and the double floating diffusion transistor DFD 224). When the voltage value at CTM(A) 354a or CTM(B) 354b exceeds the voltage value at CBM(C) 354c, the first LOFIC or the second LOFIC is configured to be forward biased. Conversely, when the voltage value at CTM(A) 354a or CTM(B) 354b is less than the voltage value at CBM(C) 354c, the first LOFIC or the second LOFIC is configured to be reverse biased. When the voltage value at CTM(A) 354a or CTM(B) 354b is equal to the voltage value at CBM(C) 354c, the first LOFIC or the second LOFIC is configured to be zero biased.

[0037] As shown, during the idle period, the reset control signal RST 344 is configured to be at a high value (e.g., ranging from 2.8V to 3.6V) in order to reset the pixel circuit. The first bias voltage source Vcap-1 348-1, the second bias voltage source Vcap-2 348-2, the voltage value at CTM(A) 354a, and the voltage value at CTM(B) 354b are configured to be at their respective low values. The voltage value at CBM(C) 354c is configured to be at an intermediate value (e.g., ranging from 1.4V to 2.8V). As described in further detail below, the low value of the first bias voltage source Vcap-1 348-1 and the voltage value at CTM(A) can be configured to be non-zero (e.g., voltage levels ranging from 2.8V to 4.2V) so that the first LOFIC can be forward biased. The low value of the second bias voltage source Vcap-2 348-2 and the voltage value at CTM(B) may be configured to be zero so that the second LOFIC may be reverse biased.

[0038] As shown, during the precharge period following the idle period, the pixel voltage source pixel VDD 360 and the reset control signal RST 344 can be configured to remain at their respective high values ​​(e.g., 2.8V and 3.6V, respectively), and the remaining illustrated voltage values ​​can be switched to their respective high values. In various examples, the high values ​​of the first bias voltage source Vcap-1 348-1 and CTM(A) 354a can be 4.2V, the high values ​​of the second bias voltage source Vcap-2 348-2 and CTM(B) 354b can be 1.4V, and the high value of CBM(C) 354c can be 2.8V. In various examples, during precharge, the voltage values ​​of CTM(A) 354a, CTM(B) 354b, and CBM(C) 354c increase together such that the first LOFIC remains forward biased and the second LOFIC remains reverse biased.

[0039] As shown, during the integration period following the pre-charge period, the reset control signal RST 344, the first bias voltage source Vcap-1 348-1, the second bias voltage source Vcap-2 348-2, the voltage value at CTM(A) 354a, and the voltage value at CTM(B) 354b are configured to switch to their respective low values. The photodiode can be configured to photogenerate image charge in response to incident light. The overflowing image charge from the photodiode can be configured to be transferred to the first LOFIC and / or the second LOFIC (e.g., through the lateral overflow gate transistor LFG 230 and the dual floating diffusion transistor DFD 224), thereby reducing the voltage value at CBM(C) 354c (e.g., from 1.4V to 0.4V). The reduction in the voltage level at CBM(C) 354c depends on the amount of overflowing image charge. In the illustrated timing diagram, during the integration period, the first LOFIC and the second LOFIC remain forward biased and reverse biased, respectively.

[0040] As shown, during the readout cycle following the integration period, the sample and hold image signal ("SHS") and the sample and hold reset signal ("SHR") are sequentially readout. In the illustrated example, the reset control signal RST 344, the first bias voltage source Vcap-1 348-1, and the second bias voltage source Vcap-2 348-2 are configured to pulse at their respective high values ​​(e.g., 3.6V, 4.2V, and 1.4V, respectively) after the SHS readout in preparation for the SHR readout. The voltage values ​​at CTM(A) 354a and CTM(B) 354b are configured to remain at their respective high values ​​(e.g., 4.2V and 1.4V, respectively) throughout the readout cycle. The voltage value at CBM(C) 354c is configured to be at the image signal value when the SHS is read out, at its high value (e.g., 2.8V) when the SHR is read out, and at its low value (e.g., 0V) between SHS readout and SHR readout.

[0041] It should be understood that the illustrated timing diagram may be represented by other Figure 2 The pixel circuit 204 may be applied to a pixel circuit other than the pixel circuit 204 illustrated in FIG. Figure 3 The timing diagram illustrated in FIG. 2 is different from the timing diagram illustrated in FIG.

[0042] Figures 4A to 4D The diagram illustrates the bias changes of the first LOFIC CAP1 454-1 and the second LOFIC CAP2 454-2 included in an exemplary pixel circuit during an idle period and an integration period in accordance with the teachings of the present disclosure. It should be appreciated that Figures 4A to 4D The bias map can be as follows Figure 2 2 and 3. An exemplary bias diagram of the first LOFIC 254-1 and the second LOFIC 254-2 is shown in FIG. 2, and similarly named and numbered elements described above are similarly coupled and function below.

[0043] Figures 4A to 4B Illustrated are bias changes of the first LOFIC 454 - 1 and the second LOFIC 454 - 2 in light and dark frames, respectively, when coupled to a bias voltage source having a first set of voltage settings. Figures 4A to 4B The bias change illustrated in FIG. 1 may correspond to Figure 3 For example, during an idle period of the pixel circuit, by configuring the voltage supplied from the first bias voltage source (e.g., the first bias voltage source Vcap-1 248-1), the voltage value at node A (e.g., Figure 2) can be set to a high value, such as 2.8V; by configuring the voltage provided from the second bias voltage source (e.g., second bias voltage source Vcap-2 248-2), the voltage value at node B can be set to a low value, such as a ground reference voltage or 0V; and by configuring the pixel voltage source (e.g., pixel VDD 360) coupled to node C through reset transistor RST 234, the voltage value at node C can be set to 1.4V. Therefore, during the idle period, the first LOFIC 454-1 is configured to be biased by the voltage difference between node A and node C (e.g., voltage value at A - voltage value at C = 2.8V - 1.4V = 1.4V (i.e., forward biased by 1.4V)), and the second LOFIC 454-2 is configured to be biased by the voltage difference between node B and node C (e.g., voltage value at B - voltage value at B, C = 0V - 1.4V = -1.4V (i.e., reverse biased by 1.4V).

[0044] like Figure 4A As shown in , during the integration period in the light frame (e.g., frame capture in the presence of incident light), the voltage values ​​at nodes A and B may be maintained at 2.8V and 0V, respectively, but the voltage value at node C decreases from 1.4V to 0.4V due to overflow image charge from the photodiode. Therefore, the forward bias amplitude of the first LOFIC 454-1 is configured to increase to 2.8V-0.4V=2.4V, while the reverse bias amplitude of the second LOFIC 454-2 is configured to decrease to 0.4V (i.e., |0V-0.4V|=0.4V). Figure 4B As shown in , during the integration period in a dark frame (e.g., a frame captured without incident light), the bias of the first LOFIC 454-1 and the second LOFIC 454-2 are configured to remain at their respective values ​​(i.e., 1.4V and -1.4V, respectively) while maintaining the voltage at node C at the beginning of the integration period in a light frame.

[0045] Figures 4C to 4D The diagram illustrates the bias changes of the first LOFIC 454-1 and the second LOFIC 454-2 in the light frame and the dark frame, respectively, when coupled to the first bias voltage source and the second bias voltage source having the second set of voltage settings. For example, during the idle period, the voltage values ​​at nodes A and B may be maintained at 0V, while the voltage value at node C is maintained at a preset voltage value (e.g., 1.4V), resulting in both the first LOFIC 454-1 and the second LOFIC 454-2 being reverse biased by an amplitude of 1.4V.

[0046] like Figure 4CAs shown in , during an integration period in a light frame, for example when the photodiode is saturated, due to overflowing image charge from the photodiode, the voltage value across the first LOFIC 454-1 and the second LOFIC 454-2 may jump to 1.4V, the voltage value at node B may remain at 0V, and the voltage value at node C may decrease from 1.4V to 0.4V. Therefore, the forward bias amplitude of the first LOFIC is configured to increase to 1.4V-0.4V=1.0V, and the reverse bias amplitude of the second LOFIC is configured to decrease to 0.4V (i.e., V-0.4V=the absolute value of |-0.4V|). As shown in FIG. Figure 4B As shown in FIG. 4 , during the integration period in the dark frame, the bias of the first LOFIC 454 - 1 and the second LOFIC 454 - 2 are configured to remain at their respective values ​​(ie, 0 V and −1.4 V, respectively) at the beginning of the integration period in the light frame.

[0047] Reference together Figure 3 , 4A 4C, at the end of the integration period, the first LOFIC is configured to be forward biased and the second LOFIC is configured to be reverse biased. During the readout period following the integration period, the first LOFIC is configured to scale the image charge and the second LOFIC is configured to generate the image charge. Assuming that the biases of the first LOFIC and the second LOFIC are opposite, their discharges (e.g., the charge captured in their respective high-k materials from the previous frame) have opposite charges and therefore compensate each other, thereby allowing the pixel circuit to maintain the signal voltage and mitigate the MIM hysteresis generated during the integration period.

[0048] Figure 5 A schematic diagram of an exemplary pixel circuit 504 including a LOFIC 554 is illustrated in accordance with the teachings of the present invention. Figure 5 The pixel circuit 504 may be included in Figure 1 1. An example of a pixel circuit 104 in an imaging system 100 is shown in FIG. 1, and similarly named and numbered elements described above are similarly coupled and function similarly below.

[0049] In the illustrated example, the pixel circuit 504 includes a photodiode 514 configured to photogenerate image charge in response to incident light. A first floating diffusion FD1 518 is coupled to receive image charge from the photodiode 514. A transfer transistor TX 516 is coupled between the photodiode 514 and the first floating diffusion FD1 518 to transfer image charge from the photodiode 514 to the first floating diffusion FD1 518. A reset transistor RST 534 is coupled between a pixel voltage source pixel VDD 560 and the first floating diffusion FD1 518. A lateral overflow gate transistor LFG 530 is coupled between the reset transistor RST 534 and the first floating diffusion FD1 518. A dual floating diffusion transistor DFD 524 is coupled between the lateral overflow gate transistor LFG 530 and the first floating diffusion FD1 518. A second floating diffusion FD2 528 is coupled between the lateral overflow gate transistor LFG 530 and the dual floating diffusion transistor DFD 524. Floating diffusion capacitor FDC 529 is coupled to a second floating diffusion FD2 528. Source follower transistor SF 520 is coupled between a pixel voltage source VDD 560 and a row select transistor RS 522, which is coupled to a bit line (eg, Figure 1 The gate terminal of the source follower transistor SF 520 is coupled to the first floating diffusion FD1 518.

[0050] Transfer transistor TX 516 is configured to switch in response to transfer control signal TX 536. Reset transistor RST 534 is configured to switch in response to reset control signal RST 544 and is configured to reset pixel circuit 504 during, for example, idle periods, precharge periods, and between image signal and reset signal readouts. Dual floating diffusion transistor DFD 524 is configured to switch in response to dual floating diffusion control signal DFD 538 and is configured to transfer image charge from first floating diffusion FD1 518 to second floating diffusion FD2 528, thereby allowing image charge to overflow from photodiode 514 to second floating diffusion FD2 528 through lateral overflow gate transistor LFG 530 and dual floating diffusion transistor DFD 524. Lateral overflow gate transistor LFG 530 is configured to switch in response to lateral overflow gate control signal LFG 542. Row select transistor RS 522 is configured to switch in response to row select control signal RS 546 and is configured to transfer the signal from source follower transistor SF 520 to the bit line. It should be appreciated that pixel circuit 504 may include fewer, additional and / or alternative components (e.g., transistors, capacitors, buffers, switches) depending on the specific requirements of the imaging system.

[0051] The pixel circuit 504 further includes a lateral overflow integrating capacitor (LOFIC) network 550 coupled to the first floating diffusion FD1 518, the first bias voltage source Vcap-1 548-1, and the second bias voltage source Vcap-2 548-2. In the illustrated example, the LOFIC network 550 is coupled to a node between the reset transistor RST 534 and the lateral overflow gate transistor LFG 530. The LOFIC network 550 may include a first LOFIC CAP1 554-1 coupled between the first floating diffusion FD1 518 and the first bias voltage source Vcap-1 548-1 and a second LOFIC CAP2 554-2 coupled between the first floating diffusion FD1 518 and the second bias voltage source Vcap-2 548-2. The lateral overflow gate transistor LFG 530 may be configured to transfer or allow overflow image charge from the photodiode 514 to overflow from the second floating diffusion FD2 528 to the first LOFIC CAP1 554-1 or the second LOFIC CAP2 554-2. The LOFIC network 550 may further include a first voltage buffer 552-1 coupled between the first LOFIC 554-1 and the first bias voltage source Vcap-1 548-1 and a second voltage buffer 552-2 coupled between the second LOFIC 554-2 and the second bias voltage source Vcap-2 548-2.

[0052] It should be appreciated that each LOFIC 554-1, 554-2 includes a first metal electrode, which may be referred to as a capacitor top metal (CTM), and a second metal electrode, which may be referred to as a capacitor bottom metal (CBM). As such, the CTM of the first LOFIC 554-1 is coupled to the first voltage buffer 552-1 at node A, the CTM of the second LOFIC 554-2 is coupled to the second voltage buffer 552-2 at node B, and the CBMs of the first LOFIC 554-1 and the second LOFIC 554-2 are coupled to the lateral overflow gate transistor LFG 530 at node C. It should be appreciated that the first bias voltage source Vcap-1 548-1 and the second bias voltage source Vcap-2 548-2 may be configured to forward bias, zero bias, or reverse bias the first LOFIC 554-1 and the second LOFIC 554-2, respectively, by adjusting the voltage values ​​at nodes A and B to be higher, equal to, or lower than the voltage value at node C.

[0053] The illustrated LOFIC network 550 further includes a first local reset transistor T1 556-1 coupled between a pixel voltage source pixel VDD 560 and a first LOFIC 554-1 (i.e., between the pixel VDD 560 and node A) and a second local reset transistor T2 556-2 coupled between the first local reset transistor T1 556-1 and a second LOFIC 554-2 (i.e., between node A and node B). The first local reset transistor T1 556-1 is configured to switch in response to a first local reset control signal T1 532-1, and the second local reset transistor T2 556-2 is configured to switch in response to a second local reset control signal T2 532-2. The first local reset transistor T1 556-1 and the second local reset transistor T2 556-2 are configured to provide a MIM local reset, reduce loading effects and improve settling time of the first LOFIC 554-1 and the second LOFIC 554-2.

[0054] Figure 6 A timing diagram illustrating an exemplary pixel circuit including a LOFIC according to the teachings of the present disclosure is illustrated. It should be understood that Figure 6 The timing diagram can be as follows Figure 5 00404 is shown in FIG. 5 , and similarly named and numbered elements described above are similarly coupled and function below.

[0055] In the illustrated example, the timing diagram includes an idle period, a precharge period, an integration period, and a readout period. The precharge period may be between the idle period and the integration period. The idle period may be before the integration period of the current frame or after the readout period of the previous frame before the current frame. The timing diagram depicts the pixel voltage source pixel VDD 660, the reset control signal RST 644, the first local reset control signal T1 632-1, the second local reset control signal T2 632-2, the first bias voltage source Vcap-1 648-1, the second bias voltage source Vcap-2 648-2, the CTM of the first LOFIC (e.g., at Figure 5 654a, the CTM of the second LOFIC (e.g., at node B) 654b, and the CBM of the first and second LOFICs (e.g., at node C) 654c. In the illustrated example, the pixel voltage source pixel VDD 660 is configured to remain at a constant non-zero value (e.g., 2.8V) throughout the entire timing diagram.

[0056] The voltage values ​​at CTM(A) 654a and CTM(B) 654b may be controlled by adjusting the voltage values ​​output by the first bias voltage source Vcap-1 648-1 and the second bias voltage source Vcap-2 648-2, respectively, and by using buffers (e.g., the first voltage buffer 552-1 and the second voltage buffer 552-2). The voltage value at CBM(C) 654c may vary depending on the amount of overflow charge flowing from the photodiode (e.g., flowing from the photodiode 514 coupled thereto and passing through the lateral overflow gate transistor LFG 530). When the voltage value at CTM(A) 654a or CTM(B) 654b exceeds the voltage value at CBM(C) 654c, the first LOFIC or the second LOFIC is configured to be forward biased. Conversely, when the voltage value at CTM(A) 654a or CTM(B) 654b is less than the voltage value at CBM(C) 654c, the first LOFIC or the second LOFIC is configured to be reverse biased. When the voltage value at CTM(A) 654a or CTM(B) 654b is equal to the voltage value at CBM(C) 654c, the first LOFIC or the second LOFIC is configured to be zero biased.

[0057] As shown, during the idle period, the reset control signal RST 644, the first local reset control signal T1 632-1, and the second local reset control signal T2 632-2 are configured to be at a high value (e.g., 3.6V) to reset the pixel circuit. During the idle period, the first bias voltage source Vcap-1 648-1, the second bias voltage source Vcap-2 648-2, the voltage value at CTM(A) 654a, the voltage value at CTM(B) 654b, and the voltage value at CBM(C) 654c are all configured to be at a common voltage, for example, at 1.4V, so that the first LOFIC and the second LOFIC are zero biased, thereby allowing the first LOFIC and the second LOFIC to discharge.

[0058] As shown, during the pre-charge cycle, the pixel voltage source pixel VDD 660 and the reset control signal RST 644 can be configured to remain at their respective high values ​​(e.g., 2.8V and 3.6V, respectively). The first local reset control signal T1 632-1 and the second local reset control signal T2 632-2 are configured to switch to their low values ​​(e.g., 0V). The voltage values ​​at the first bias voltage source Vcap-1 648-1 and CTM (A) 654a are configured to switch to their high values ​​(e.g., 2.8V), while the voltage values ​​at the second bias voltage source Vcap-2 648-2 and CTM (B) 654b and CBM (C) 654c are configured to remain at their intermediate values ​​(e.g., 1.4V). Therefore, during pre-charge, the first LOFIC is configured to be forward biased and the second LOFIC is configured to remain at zero bias. In other embodiments, during pre-charge, the voltage value at the first bias voltage source Vcap-1 648-1 and CTM(A) 654a is configured to remain at 1.4V so that the first LOFIC maintains zero bias. In other embodiments, during pre-charge, the voltage value at CBM(C) 654c is configured to decrease to 1V so that the second LOFIC is forward biased.

[0059] As shown, during the integration period, the reset control signal RST 644, the first bias voltage source Vcap-1 648-1, the second bias voltage source Vcap-2 648-2, the voltage value at CTM(A) 654a, and the voltage value at CTM(B) 654b are configured to switch to their respective low values. The first local reset control signal T1 632-1 and the second local reset control signal T2 632-2 are configured to remain off. The photodiode can be configured to photogenerate image charge in response to incident light. The overflowing image charge from the photodiode can be transferred to the first LOFIC and the second LOFIC, thereby reducing the voltage value at CBM(C) 654c (e.g., from 1.4V to 0.7V). In the illustrated timing diagram, during the integration period, the first LOFIC and the second LOFIC are configured to be forward biased and reverse biased, respectively.

[0060] As shown, during the readout cycle, the sample and hold image signal ("SHS") and the sample and hold reset signal ("SHR") are sequentially readout. In the illustrated example, the reset control signal RST 644, the first local reset control signal T1 632-1, the second local reset control signal T2 632-2, the first bias voltage source Vcap-1 648-1, and the second bias voltage source Vcap-2 648-2 are configured to pulse at their respective high values ​​after the SHS readout in preparation for the SHR readout. Throughout the entire readout cycle, the voltage values ​​at CTM (A) 654a and CTM (B) 654b are configured to remain at their respective high values ​​(e.g., 2.8V). The voltage value at CBM(C) 654c is configured to be at the image signal value when the SHS is read out, at its high value (e.g., 2.8V) when the SHR is read out, and at its low value (e.g., 0V) between SHS readout and SHR readout.

[0061] It should be understood that in addition to Figure 5 In addition to the pixel circuit 504 illustrated in FIG. 1 , the illustrated timing diagram may also be applied by the pixel circuit, and the pixel circuit 504 may be based on Figure 6 The timing diagram illustrated in FIG. 2 is different from the timing diagram illustrated in FIG.

[0062] Figures 7A to 7B Illustrated are bias changes of a first LOFIC CAP1 754-1 and a second LOFIC CAP2 754-2 included in an exemplary pixel circuit during an idle period and an integration period in accordance with the teachings of the present disclosure. Fig. 7A depicts the changes in the light frame, and Figure 7B Depicts the changes in the dark frame. It should be understood that Figures 7A to 7B The bias map can be as follows Figure 5 0046] An exemplary bias diagram of the first LOFIC 554-1 and the second LOFIC 554-2 is shown in FIG. 1 , and similarly named and numbered elements described above are similarly coupled and function below.

[0063] Figures 7A to 7B The bias change illustrated in FIG. 1 may correspond to Figure 6 For example, during an idle period, the voltage values ​​at nodes A, B, and C (illustrated in FIG. Figure 5 Thus, during the idle period, both the first LOFIC 754-1 and the second LOFIC 754-2 are configured to be zero biased, such that during the idle period, the first LOFIC 754-1 and the second LOFIC 754-2 are operable to release residual charge (eg, charge trapped in their high-k materials).

[0064] like Fig. 7A As shown in , during the integration period in the light frame, the voltage values ​​at nodes A and B are configured to be 1.4V and 0V, respectively, but due to the overflow of the image charge of the photodiode, the voltage value at node C decreases from 1.4V to 0.7V. Therefore, the forward bias amplitude of the first LOFIC is configured to increase to 1.4V-0.7V=0.7V, and the reverse bias amplitude of the second LOFIC is configured to decrease to 0.7V (i.e., 0V-0.7V=|-0.7V| absolute value). Figure 7B As shown in FIG. 5 , during the integration period in the dark frame, the bias of the first LOFIC 754 - 1 and the second LOFIC 754 - 2 are configured to remain at their respective values ​​(ie, 0 V and −1.4 V, respectively) at the beginning of the integration period in the light frame.

[0065] Reference together Figure 6 and 7A , at the end of the integration period, the first LOFIC 754-1 is configured to be forward biased and the second LOFIC 754-2 is configured to be reverse biased. During the readout period after the integration period, the first LOFIC 754-1 is configured to release the image charge and the second LOFIC 754-2 is configured to generate the image charge. Assuming that the biases of the first LOFIC 754-1 and the second LOFIC 754-2 are opposite, their discharges have opposite charges and therefore compensate for each other, thereby allowing the pixel circuit to maintain the signal voltage and mitigate the MIM hysteresis generated during the integration period.

[0066] and Figure 2 , 3 Compared with the embodiments illustrated in FIGS. 4A to 4D, Figure 5 , 6 7A-7B include a local reset transistor configured to provide a MIM local reset, reduce loading effects and improve settling time of the first LOFIC and the second LOFIC. Also, in the latter embodiments, the maximum bias amplitude of either LOFIC is smaller (e.g., less than 1000 Ω). Figure 4A Compared to the 2.4V of the LOFIC 454-1 illustrated in the figure, Fig. 7A The maximum bias amplitude of the LOFIC 754-2 illustrated in FIG is 1.4 V), which can further reduce the MIM hysteresis.

[0067] The above description of the illustrated examples of the present disclosure (including what is described in the Abstract) is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Although specific examples of the present disclosure are described herein for illustrative purposes, as those skilled in the art will recognize, various modifications are possible within the scope of the present disclosure.

[0068] In light of the above detailed description, these modifications may be made to the present disclosure. The terms used in the appended claims should not be interpreted as limiting the present disclosure to the specific examples disclosed in this specification. On the contrary, the scope of the present disclosure will be determined entirely by the appended claims, which will be interpreted according to established principles of claim interpretation.

Claims

1. A pixel circuit, comprising: a photodiode configured to photogenerate one or more image charges in response to incident light; a floating diffusion coupled to receive the one or more image charges from the photodiode; a transfer transistor coupled between the photodiode and the floating diffusion to transfer the one or more image charges from the photodiode to the floating diffusion; a reset transistor coupled between a pixel voltage source and the floating diffusion, wherein the reset transistor is configured to switch in response to a reset control signal; A lateral overflow integrating capacitor LOFIC network is coupled to the floating diffusion, a first bias voltage source, and a second bias voltage source, the LOFIC network comprising: a first LOFIC coupled between the floating diffusion and the first bias voltage source; and a second LOFIC coupled between the floating diffusion and the second bias voltage source; wherein at the end of the integration period, the first LOFIC is configured to be forward biased and the second LOFIC is configured to be reverse biased, and During the readout cycle, the charge released from the first LOFIC and the charge released from the second LOFIC compensate each other. 2 . The pixel circuit of claim 1 , wherein during the integration period, the first LOFIC is configured to be forward biased, and wherein during the integration period, the second LOFIC is configured to be reverse biased.

3. The pixel circuit of claim 1 , wherein during an idle period occurring prior to the integration period, the first LOFIC is configured to be forward biased, and wherein during the idle period, the second LOFIC is configured to be reverse biased. 4 . The pixel circuit of claim 1 , wherein during an idle period, the first LOFIC and the second LOFIC are configured to be reverse biased.

5. A pixel circuit according to claim 1, wherein during the integration period, the forward bias amplitude of the first LOFIC is configured to increase based on the amount of overflow image charge received by the first LOFIC from the photodiode, and wherein during the integration period, the reverse bias amplitude of the second LOFIC is configured to decrease based on the amount of overflow image charge received by the second LOFIC from the photodiode.

6. The pixel circuit of claim 1 , wherein the LOFIC network further comprises: a first local reset transistor coupled between the pixel voltage source and the first LOFIC; and A second local reset transistor is coupled between the first local reset transistor and the second LOFIC.

7. The pixel circuit of claim 6, wherein during an idle period, the first local reset transistor and the second local reset transistor are configured to be turned on, and wherein during a precharge period and the integration period, the first local reset transistor and the second local reset transistor are configured to be turned off.

8. The pixel circuit of claim 6 , wherein during a reset signal readout period and an image signal readout period, the first local reset transistor and the second local reset transistor are configured to be turned off, and wherein during a period between the reset signal readout period and the image signal readout period, the first local reset transistor and the second local reset transistor are configured to be turned on.

9. The pixel circuit of claim 6, wherein during an idle period occurring before the integration period, the first LOFIC and the second LOFIC are configured to be zero biased.

10. The pixel circuit of claim 1 , wherein during an idle period occurring before the integration period, the reset transistor is configured to be turned on, the first bias voltage source is configured to be at a first low voltage, and the second bias voltage source is configured to be at a second low voltage; wherein during a precharge period occurring between the idle period and the integration period, the reset transistor is configured to be turned on, the first bias voltage source is configured to be at a first high voltage, and the second bias voltage source is configured to be at a second high voltage; and Wherein during the integration period, the reset transistor is configured to be turned off, the first bias voltage source is configured to be at the first low voltage, and the second bias voltage source is configured to be at the second low voltage.

11. The pixel circuit of claim 1 , wherein the LOFIC network further comprises: a first voltage buffer coupled between the first LOFIC and the first bias voltage source; and A second voltage buffer is coupled between the second LOFIC and the second bias voltage source.

12. A method of operating a pixel circuit, comprising: During the integration period— photogenerating image charge in a photodiode in response to incident light; transferring at least one overflow image charge from the photodiode to a lateral overflow integration capacitor (LOFIC) network of the pixel circuit when the photodiode is saturated, wherein the LOFIC network includes a first LOFIC coupled between a floating diffusion and a first bias voltage source and a second LOFIC coupled between the floating diffusion and a second bias voltage source; At the end of the integration period, configuring the first bias voltage source to be at a first low voltage such that the first LOFIC is forward biased; and at the end of the integration period, configuring the second bias voltage source to be at a second low voltage such that the second LOFIC is reverse biased; as well as During the read cycle— The first LOFIC and the second LOFIC are configured to release image charges, wherein the image charges released from the first LOFIC and the image charges released from the second LOFIC compensate each other.

13. The method according to claim 12, further comprising: During the idle period that occurs before the integration period— configuring the first bias voltage source to be at the first low voltage such that the first LOFIC is forward biased; and The second bias voltage source is configured to be at the second low voltage such that the second LOFIC is reverse biased.

14. The method according to claim 12, further comprising: During the idle period that occurs before the integration period— configuring the first bias voltage source to be at the first low voltage such that the first LOFIC is reverse biased; and The second bias voltage source is configured to be at the second low voltage such that the second LOFIC is reverse biased.

15. The method according to claim 12, further comprising: During the integration period— configuring the forward bias amplitude of the first LOFIC to increase based on an amount of overflow image charge received by the first LOFIC from the photodiode; and The reverse bias amplitude of the second LOFIC is configured to decrease based on an amount of overflow image charge received by the second LOFIC from the photodiode.

16. The method of claim 12, wherein the LOFIC network further comprises: a first local reset transistor coupled between a pixel voltage source and the first LOFIC; and a second local reset transistor coupled between the first local reset transistor and the second LOFIC.

17. The method according to claim 16, further comprising: During idle periods— configuring the first local reset transistor and the second local reset transistor to be turned on; During a precharge period occurring between the idle period and the integration period— configuring the first local reset transistor and the second local reset transistor to be off; and During the integration period— The first local reset transistor and the second local reset transistor are configured to remain off.

18. The method according to claim 16, further comprising: During the read cycle— During a reset signal readout period and an image signal readout period, configuring the first local reset transistor and the second local reset transistor to be turned off; and During a period between the reset signal readout period and the image signal readout period, the first local reset transistor and the second local reset transistor are configured to be turned on.

19. The method of claim 16, further comprising: During idle periods— configuring the first bias voltage source to be at the first low voltage so that the first LOFIC is zero biased; and The second bias voltage source is configured to be at the second low voltage such that the second LOFIC is zero biased.

20. The method of claim 12, wherein the LOFIC network further comprises: a first voltage buffer coupled between the first LOFIC and the first bias voltage source; and A second voltage buffer is coupled between the second LOFIC and the second bias voltage source.

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