Matrix low-rank decomposition-based on-chip training method and device for resistive memory storage-computing integration

Abstract

The present application relates to the technical field of on-chip training, and particularly relates to a matrix low-rank decomposition-based on-chip training method and device for resistive memory storage-computing integrated chips, wherein the method comprises: substituting a target training network model into a preset non-ideal factor model for offline training to obtain a pre-training model having tolerance to actual non-ideal factors of a target storage-computing integrated chip; performing low-rank decomposition on the pre-training model by using a matrix low-rank decomposition network to obtain a main pre-training network and a bypass network; deploying the main pre-training network to a resistive memory array of the target storage-computing integrated chip and deploying the bypass network to a digital unit of the target storage-computing integrated chip to perform on-chip training on the resistive memory array and the digital unit and obtain a trained resistive memory array. Thus, the problems of excessive time and power consumption cost, poor scalability, inapplicability to large-scale deep neural networks, and large accuracy loss after training of the prior on-chip training method are solved.

Description

Technical Field

[0001] This invention relates to the field of on-chip training technology, and in particular to an on-chip training method and apparatus for memristor-based in-memory computing based on low-rank matrix decomposition. Background Technology

[0002] Over the past decade or so, the field of artificial intelligence has undergone significant technological innovation, particularly with the substantial progress made in deep learning algorithms across computer vision, natural language processing, and reinforcement learning. These algorithms typically rely on large-scale neural network models, whose parameter and data volumes have increased dramatically, leading to a surge in demand for computing resources. Traditional CMOS-based von Neumann architecture chips, such as CPUs, suffer from low energy efficiency and limited computing power when performing deep learning tasks due to the separation of their storage and processing units. While GPUs offer high computing power, they still fall short in terms of energy efficiency. Therefore, in edge computing scenarios, high-performance, high-energy-efficiency chips based on non-von Neumann architectures represent a crucial research direction.

[0003] In-memory computing chips based on non-volatile memory arrays break through the limitations of the von Neumann architecture, integrating storage and computing units to reduce latency and energy consumption during data transfer between them. The high energy efficiency resulting from this integration is even more pronounced for computationally intensive tasks such as neural networks. In in-memory computing chips, the core computing unit consists of a non-volatile memory array and peripheral circuitry (such as analog-to-digital converters and digital-to-analog converters). It can accelerate the computation of matrix-vector multiplication (MVM), a core operator in computationally intensive tasks like neural networks, through analog computation. While this approach boasts high energy efficiency and scalability, the use of analog computation by non-volatile memory arrays and peripheral circuitry for MVM calculations faces the combined effects of multiple layers of non-ideal factors, including memristor units, memristor arrays, and peripheral analog circuitry, leading to accuracy losses and results lower than those achieved by digital chips. This accuracy loss is particularly severe when dealing with multi-layered deep networks.

[0004] To address the accuracy loss issue inherent in in-memory computing, current solutions fall into two categories: offline training and on-chip training.

[0005] The offline training approach involves modeling the non-ideal factors of the memristor array and peripheral circuitry during computation to obtain compact models, such as device relaxation models, device finite state (quantization models), device read / write noise models, and circuit IR-drop models. These models are then fed into the network training, leveraging the redundancy of neural networks to obtain models that can tolerate these non-ideal factors, before being deployed to the chip. However, this method has two problems: 1) Modeling difficulty: Most of the non-ideal factors in the device array and circuitry are strongly coupled, resulting in many influencing factors in constructing the chip state model. It is also difficult to use these compact models to perfectly match the actual operating behavior of the chip. Therefore, the trained network cannot fully adapt to the non-ideal factors on the chip, often leading to reduced accuracy after deployment. 2) Difficulty adapting to chip changes: The trained network will experience write errors during deployment to the memristor array. Furthermore, after writing, due to the retention characteristics of the device, the weight values ​​will drift over time, and offline learning cannot adapt to these internal chip changes.

[0006] On-chip training involves incorporating the chip into the training process. First, the offline-trained network model is deployed onto the chip, followed by further adaptive training. During adaptive training, the inference process is actually completed on the chip, and gradient calculations are performed on-chip to update the model, achieving higher computational accuracy. This approach does not require a perfectly compact model to represent chip behavior and can adapt to changes in the chip. Current methods include hybrid training and layer-by-layer training. However, these methods have the following problems: 1) Hybrid training can only perform on-chip adjustments on the last few layers, lacking scalability. When deploying deep, large-scale neural networks on-chip, the redundancy of the last layer cannot completely compensate for the accuracy loss of the preceding layers; 2) Layer-by-layer training is a layer-wise greedy algorithm. It can train deep neural networks that adapt to non-ideal chip conditions. However, its training cost is extremely high, including time and power costs, making this method impractical.

[0007] Meanwhile, whether training is done offline or on-chip, in the process of deploying deep neural networks, although it can compensate for most of the effects of non-ideal factors compared to the computation results of digital chips, there will still be a significant loss of accuracy. This is determined by the characteristics of analog memristor arrays. Summary of the Invention

[0008] This invention provides a memristor-based in-memory computing on-chip training method and apparatus based on low-rank matrix decomposition, which solves the problems of excessive time and power consumption, poor scalability, inapplicability to large-scale deep neural networks, and significant accuracy loss after training in existing on-chip training methods.

[0009] The first aspect of this invention provides an on-chip training method for memristor-based in-memory computing based on low-rank matrix decomposition, comprising the following steps: substituting a target training network model into a preset non-ideal factor model for offline training to obtain a pre-trained model that is tolerant to actual non-ideal factors of the target in-memory computing chip; performing low-rank decomposition on the pre-trained model using a low-rank matrix decomposition network to obtain a main intervention training network and a bypass network; deploying the main intervention training network to the memristor array of the target in-memory computing chip, and deploying the bypass network to the digital unit of the target in-memory computing chip to perform on-chip training on the memristor array and the digital unit, thereby obtaining a trained memristor array.

[0010] Optionally, it further includes: before performing offline training, quantizing and adding noise to the target training network model, so as to use the quantized and noise-added target training network model to be substituted into the preset non-ideal factor model for offline training.

[0011] Optionally, the step of using a matrix low-rank decomposition network to perform low-rank decomposition on the pre-trained model to obtain the main intervention training network and the bypass network includes: obtaining the main network layer of the pre-trained model and using the main network layer as the main intervention training network; using a matrix low-rank decomposition network to perform low-rank decomposition on the main network layer to obtain multiple two-layer small networks, and using the multiple two-layer small networks as the bypass network.

[0012] Optionally, each two-layer network can be either a two-layer fully connected network or a two-layer convolutional network.

[0013] Optionally, the step of deploying the main intervention training network to the memristor array of the target in-memory computing chip and deploying the bypass network to the digital unit of the target in-memory computing chip to perform on-chip training on the memristor array and the digital unit to obtain the trained memristor array includes: deploying the main intervention training network to the memristor array of the target in-memory computing chip for forward inference to obtain a first output; deploying the bypass network to the digital unit of the target in-memory computing chip for forward inference to obtain a second output; comparing the first output and the second output with preset theoretical values ​​and obtaining residuals based on the comparison results; and using the residuals to perform reverse updates on the gradient of the bypass network to obtain the trained memristor array.

[0014] A second aspect of the present invention provides an on-chip training device for memristor-based in-memory computing based on matrix low-rank decomposition, comprising: an offline training module for substituting a target training network model into a preset non-ideal factor model for offline training to obtain a pre-trained model that is tolerant to actual non-ideal factors of the target in-memory computing chip; a low-rank decomposition module for performing low-rank decomposition on the pre-trained model using a matrix low-rank decomposition network to obtain a main intervention training network and a bypass network; and an on-chip training module for deploying the main intervention training network to the memristor array of the target in-memory computing chip and deploying the bypass network to the digital unit of the target in-memory computing chip to perform on-chip training on the memristor array and the digital unit to obtain a trained memristor array.

[0015] Optionally, the on-chip training module includes a digital matrix multiplication calculation unit, a first analog-in-memory computing subunit, a second analog-in-memory computing subunit, and a special function calculation unit, wherein,

[0016] The simulated in-memory computing unit is used to deploy the main intervention training network to the memristor array of the target in-memory computing chip for forward inference to obtain the first output;

[0017] The first digital matrix multiplication calculation unit is used to deploy the bypass network to the digital unit of the target in-memory computing chip for forward inference to obtain the second output;

[0018] A special function calculation unit is used to compare the first output and the second output with a preset theoretical value to obtain the residual;

[0019] The second digital matrix multiplication calculation unit is used to update the gradient of the bypass network in reverse using the residual to obtain the trained memristor array.

[0020] A third aspect of the present invention provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the memristor in-memory computing on-chip training method based on matrix low-rank decomposition as described in the above embodiments.

[0021] A fourth aspect of the present invention provides a computer program product, wherein when the computer program / instructions are executed by a processor, the above-described memristor-based in-memory computing on-chip training method is implemented.

[0022] A fifth aspect of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described memristor-based in-memory computing on-chip training method based on low-rank matrix decomposition.

[0023] The present invention proposes a memristor-based in-memory computing on-chip training method and apparatus based on low-rank matrix decomposition. After deploying the offline-trained network model onto the memristor array, several layers of corresponding bypass networks are deployed in digital cells and trained on-chip. During on-chip training, the number of parameters and computational cost of the bypass networks are much smaller than those of the corresponding layers of the original network, and the weight updates only occur in the bypass networks. Therefore, repeated programming operations on the memristors are not required, resulting in fast convergence and low power consumption. It can be scaled up to large-scale deep neural networks and can also improve the computational accuracy of the entire system, with the upper limit of accuracy being closer to the computational results of a fully digital chip.

[0024] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0025] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0026] Figure 1 A flowchart of a memristor-based in-memory computing on-chip training method based on low-rank matrix decomposition provided in an embodiment of the present invention;

[0027] Figure 2 A schematic diagram of the in-memory computing array and its implementation of matrix-vector multiplication provided in an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the core computing unit of the in-memory computing chip provided in an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the decomposition process of the low-rank matrix decomposition network provided in an embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram illustrating the complete deployment process of online training based on low-rank decomposition provided in an embodiment of the present invention;

[0031] Figure 6 This is a schematic diagram illustrating the specific structure of the backbone network and bypass network provided in an embodiment of the present invention.

[0032] Figure 7 This is a schematic diagram of the bypass network structure of the fully connected layer provided in an embodiment of the present invention;

[0033] Figure 8 This is a schematic diagram of the bypass network structure of the convolutional layer provided in an embodiment of the present invention;

[0034] Figure 9This is a block diagram of a memristor-based in-memory computing on-chip training device based on low-rank matrix decomposition provided in an embodiment of the present invention.

[0035] Figure 10 This is a schematic diagram of the specific architecture of the on-chip training module provided in an embodiment of the present invention;

[0036] Figure 11 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation

[0037] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0038] The following description, with reference to the accompanying drawings, describes an embodiment of the memristor-based in-memory computing on-chip training and apparatus based on low-rank matrix decomposition.

[0039] Specifically, Figure 1 This is a flowchart illustrating an on-chip training method for memristor-based in-memory computing based on low-rank matrix decomposition, provided in an embodiment of the present invention.

[0040] like Figure 1 As shown, the memristor in-memory computing on-chip training method based on low-rank matrix decomposition includes the following steps:

[0041] In step S101, the target training network model is substituted into a preset non-ideal factor model for offline training to obtain a pre-trained model that is tolerant of the actual non-ideal factors of the target in-memory computing chip.

[0042] In some embodiments, the method further includes: quantizing and adding noise to the target training network model before offline training, so as to use the quantized and noise-added target training network model to be substituted into a preset non-ideal factor model for offline training.

[0043] In actual execution, the target training network model is first quantized and noise-added. The quantized and noise-added target training model is then fed into a pre-set non-ideal factor model such as a circuit for offline training to obtain a pre-trained model that has a certain tolerance to the actual non-ideal factors of the target in-memory computing chip.

[0044] It should be noted that the in-memory computing chip used in the embodiments of the present invention is a non-volatile memory array whose basic units include, but are not limited to, novel non-volatile memory devices such as resistive random access memory (RRAM), phase change memory (PCM), magnetic random access memory (MRAM), and ferroelectric memory (FeRAM), as well as traditional non-volatile memory devices such as floating gate transistors (Flash) and dynamic random access memory (DRAM). Furthermore, the structure of the non-volatile memory array should include both 1T1R (1 Transistor 1RRAM) and 2T2R (2 Transistors 2RRAM) structures.

[0045] like Figure 2 As shown, the target in-memory computing chip in this embodiment of the invention performs matrix-vector multiplication using an analog method for computational tasks such as neural networks. Specifically, it maps the element values ​​of the matrix to the conductance values ​​of the array cells, and inputs the element values ​​of the vector into the encoding module to encode them into voltage pulses. It then uses Ohm's law and Kirchhoff's law to perform analog calculations. The calculation results are output in the form of current in each column. The output current is quantized into digital quantities by output quantization circuits such as ADC to obtain the calculation results of matrix-vector multiplication.

[0046] Furthermore, such as Figure 3 As shown, the core computing unit of the target in-memory computing chip in this embodiment of the invention includes modules such as an input / output buffer unit, a digital-to-analog converter unit, an analog-to-digital converter unit, a programming unit, a state control and selection unit, an input / output module, and a non-volatile memory array. During inference computation, weight data is first mapped to the non-volatile memory array through the programming unit. For input data such as images, it first enters the input buffer unit through the input and output modules, is converted into a voltage signal by the digital-to-analog converter unit, and then inputs to the non-volatile memory array. The resulting output, a current signal, is converted into a digital signal by the analog-to-digital converter unit and a shift accumulator, buffered in the output buffer unit, and output through the input and output modules. The state control and selection unit can control the core computing unit to perform forward computation, weight mapping, and reverse updates. In this embodiment of the invention, this core computing unit is referred to as XB (CrossBar).

[0047] In step S102, the pre-trained model is decomposed into a low-rank matrix using a low-rank matrix decomposition network to obtain the main intervention training network and the bypass network.

[0048] In some embodiments, a low-rank matrix factorization network is used to perform low-rank decomposition on the pre-trained model to obtain the main intervention training network and the bypass network, including:

[0049] Obtain the main network layer of the pre-trained model and use the main network layer as the main intervention training network;

[0050] The main network layer is decomposed into multiple two-layer subnetworks by using a matrix low-rank decomposition network, which can then be used as bypass networks.

[0051] It should be noted that low-rank matrix decomposition networks can transform the weight matrix W of a neural network into several smaller matrices through low-rank decomposition, thereby reducing the number of model parameters and computational cost. This allows for training of downstream tasks with significantly lower computational and storage requirements compared to full-network fine-tuning. Compared to full-network fine-tuning, it also offers advantages such as reducing overfitting, improving model generalization ability, and rapidly adapting to new task domains. Therefore, the over-parameterized model obtained through pre-training in this embodiment actually exists on a lower intrinsic dimension. Assuming that the weight changes during model adaptation also have a low "intrinsic rank," a network layer in a pre-trained model can be approximated by two smaller network layers obtained through low-rank decomposition. For example... Figure 4 As shown, the original pre-trained network has a single layer W with m*n parameters. Using low-rank matrix factorization, the network can be decomposed into two smaller layers A and B with parameters m*r and r*n respectively, where r is much smaller than min(m,n). Here, we use A*B to approximate W. The two smaller layers A and B have a parameter count of (m+n)*r. The parameter count of W, m*n, is m*n / ((m+n)*r) times the parameter count of the smaller layers A and B.

[0052] Therefore, in actual implementation, the embodiments of the present invention first obtain the main network layer of the pre-trained model and use the main network layer as the main intervention training network. Then, the main network layer is decomposed into a low-rank matrix using a matrix low-rank decomposition network to obtain multiple two-layer small networks. These multiple two-layer small networks are used as bypass networks. Each two-layer small network can be a two-layer fully connected layer network or a two-layer convolutional layer network.

[0053] In step S103, the main intervention training network is deployed to the memristor array of the target in-memory computing chip, and the bypass network is deployed to the digital unit of the target in-memory computing chip to perform on-chip training on the memristor array and the digital unit, thereby obtaining the trained memristor array.

[0054] In some embodiments, a main intervention training network is deployed to the memristor array of the target in-memory computing chip, and a bypass network is deployed to the digital unit of the target in-memory computing chip to perform on-chip training on the memristor array and the digital unit, resulting in a trained memristor array, including:

[0055] The main intervention training network is deployed to the memristor array of the target in-memory computing chip for forward inference to obtain the first output;

[0056] The bypass network is deployed to the digital unit of the target in-memory computing chip for forward inference to obtain the second output;

[0057] The first and second outputs are compared with preset theoretical values, and the residuals are obtained based on the comparison results.

[0058] The gradient of the bypass network is updated in reverse using the residuals to obtain the trained memristor array.

[0059] In actual implementation, such as Figure 5 and 6 As shown, the main intervention training network is deployed in the memristor array of the target in-memory computing chip, and the bypass network is deployed in the digital unit (DMU) layers of the target DMU. Multiple two-layer fully connected networks and multiple two-layer convolutional networks are deployed on the DMU layers respectively. Forward inference is jointly performed by the main intervention training network deployed in the memristor array and the bypass network deployed in the DMU. For any layer with a bypass network, the output of that layer is obtained by adding the result of the main intervention training network and the result of the bypass network. During this process, the output with errors caused by the actual non-ideal factors of the target DMU will be reflected in the final calculation result. Therefore, the main intervention training network deployed in the memristor array will be frozen and does not need to be updated. Only the bypass network deployed in the DMU needs to be updated according to the gradient. This update process involves subtracting the summed output from a preset theoretical value, using the difference as a residual, and updating the gradient of the bypass network in reverse according to the residual, thus completing the backpropagation process (i.e., reverse update), thereby obtaining the trained memristor array.

[0060] It should be noted that the gradient update algorithm for the bypass network can be implemented using algorithms such as backpropagation (BP).

[0061] Furthermore, such as Figure 7 As shown, when a two-layer fully connected network is deployed in a layer of a digital unit, matrix multiplication is performed directly, with weights W. The two fully connected layers are A and B. Assume W ∈ R. d×k Then, A∈R d×r ,B∈R r×k And r << min(d,k), where r is a hyperparameter representing the set intrinsic rank.

[0062] Furthermore, such as Figure 8 As shown, when a two-layer convolutional network is deployed in a certain layer of a digital unit, assume that the parameter of its weight W is c.in ,k,k,c out The two convolutional network layers are A and B. The weight parameters of the first layer A are c. in The weight parameters of the second layer B are r,1,1,c. out The overall reduction in parameters is: Where r is a hyperparameter representing the set intrinsic rank.

[0063] It should be noted that r is a hyperparameter that can be selected based on the specific training results. Typical values ​​that can be provided are 1, 2, 4, 8, and 6. Its value is related to the complexity of the computational task, the size of the pre-trained model, and other factors. This value affects the number of trainable parameters, which in turn affects the overall power consumption during training and the final training effect.

[0064] The selection of layers for bypass networks is also a hyperparameter. Those skilled in the art can set it in every layer, every other layer, or in a more sparse manner. It is related to the complexity of the computational task, the size of the pre-trained model, and other factors. This value affects the number of trainable parameters, which in turn affects the overall power consumption during training and the final training effect.

[0065] In summary, the on-chip training method for memristor in-memory computing based on low-rank matrix decomposition proposed in this embodiment of the invention has the following beneficial effects:

[0066] (1) Since training is performed by digital units, compared with the previous on-chip training scheme, the large-scale memristor programming process is avoided during training, and the reading and writing noise of the memristor is avoided from affecting the training convergence. At the same time, the number of parameters to be trained is small, so the convergence speed is fast and the time cost is small.

[0067] (2) Because the large-scale memristor programming process is avoided during training, the power consumption of training is low;

[0068] (3) It can support on-chip training of networks of any depth and can compensate for the accuracy loss caused by deploying memristor arrays in the corresponding layers. Therefore, it has strong scalability and can be applied to large-scale deep neural networks.

[0069] (4) Since the introduction of digital units with no precision loss, the network branches of the calculation bypass can provide more information, thereby reducing the precision loss of the analog part due to non-ideal factors.

[0070] Next, referring to the accompanying drawings, a memristor-based in-memory computing on-chip training device based on matrix low-rank decomposition according to an embodiment of the present invention is described.

[0071] Figure 9This is a block diagram of a memristor-based on-chip training device for memory computing based on low-rank matrix decomposition, according to an embodiment of the present invention.

[0072] like Figure 9 As shown, the memristor in-memory computing on-chip training device 90 based on matrix low-rank decomposition includes: an offline training module 901, a low-rank decomposition module 902, and an on-chip training module 903.

[0073] The offline training module 901 is used to substitute the target training network model into a preset non-ideal factor model for offline training, so as to obtain a pre-trained model that is tolerant of the actual non-ideal factors of the target in-memory computing chip. The low-rank decomposition module 902 is used to perform low-rank decomposition on the pre-trained model using a matrix low-rank decomposition network to obtain the main intervention training network and the bypass network. The on-chip training module 903 is used to deploy the main intervention training network to the memristor array of the target in-memory computing chip and deploy the bypass network to the digital unit of the target in-memory computing chip to perform on-chip training on the memristor array and the digital unit, so as to obtain the trained memristor array.

[0074] In some embodiments, the on-chip training module includes a digital matrix multiplication computation unit, a first analog-in-memory computation subunit, a second analog-in-memory computation subunit, and a special function computation unit, wherein...

[0075] The simulated in-memory computing unit is used to deploy the main intervention training network to the memristor array of the target in-memory computing chip for forward inference to obtain the first output;

[0076] The first digital matrix multiplication calculation unit is used to deploy the bypass network to the digital unit of the target in-memory computing chip for forward inference to obtain the second output.

[0077] A special function calculation unit is used to compare the first output and the second output with a preset theoretical value to obtain the residual;

[0078] The second digital matrix multiplication unit is used to update the gradient of the bypass network in reverse using the residuals to obtain the trained memristor array.

[0079] In actual implementation, such as Figure 10As shown, the on-chip training method based on low-rank matrix decomposition of memristors proposed in this embodiment of the invention requires an analog in-memory computing unit based on a memristor array, as well as a digital computing unit for deploying a bypass network to support the training task. Therefore, in addition to constructing an offline training module 901, a low-rank decomposition module 902, and an on-chip training module 903, this embodiment of the invention also constructs a heterogeneous hardware architecture to assist in the implementation of the on-chip training module 903. This heterogeneous hardware architecture includes a digital matrix multiplication computing unit, a first analog in-memory computing subunit, a second analog in-memory computing subunit, a special function computing unit, an instruction cache unit, an intermediate activation cache unit, a weight cache unit, etc.

[0080] The first and second analog-in-memory computing subunits constitute the analog-in-memory computing unit, which deploys the main intervention training neural network to realize matrix multiplication calculations in the analog domain, providing high-energy-efficiency network computing. The digital matrix multiplication calculation unit is deployed with a bypass network, which can realize high-precision matrix multiplication calculations and supports backpropagation algorithms. The instruction cache unit includes digital unit instruction cache and analog unit instruction cache, which store the instructions controlling the analog-in-memory computing unit and the digital matrix multiplication calculation unit, respectively. The intermediate activation cache unit is used to store the input and output data of each layer. This cache unit is shared by the digital unit and the analog unit. The input data is sent to both parts for calculation at the same time, and the output results are temporarily stored in the intermediate activation cache unit after being adjusted, added, and activated by a special function calculation unit for scaling, etc., for the calculation of the next layer.

[0081] In addition, this heterogeneous hardware architecture may also include a controller, a storage unit, and an I / O unit. The controller is responsible for scheduling tasks and is usually a CPU; the storage unit is responsible for storing basic information such as weights and input data, and its capacity is larger than that of the cache unit; the I / O unit is responsible for communication.

[0082] It should be noted that the foregoing explanation of the embodiment of the memristor in-memory computing on-chip training method based on low-rank matrix decomposition also applies to the memristor in-memory computing on-chip training device based on low-rank matrix decomposition in this embodiment, and will not be repeated here.

[0083] The memristor-based in-memory computing on-chip training device based on low-rank matrix decomposition proposed in this invention has the following advantages:

[0084] (1) Since training is performed by digital units, compared with the previous on-chip training scheme, the large-scale memristor programming process is avoided during training, and the reading and writing noise of the memristor is avoided from affecting the training convergence. At the same time, the number of parameters to be trained is small, so the convergence speed is fast and the time cost is small.

[0085] (2) Because the large-scale memristor programming process is avoided during training, the power consumption of training is low;

[0086] (3) It can support on-chip training of networks of any depth and can compensate for the accuracy loss caused by deploying memristor arrays in the corresponding layers. Therefore, it has strong scalability and can be applied to large-scale deep neural networks.

[0087] (4) Since the introduction of digital units with no precision loss, the network branches of the calculation bypass can provide more information, thereby reducing the precision loss of the analog part due to non-ideal factors.

[0088] Figure 11 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. The electronic device may include:

[0089] The memory 1101, the processor 1102, and the computer program stored on the memory 1101 and executable on the processor 1102.

[0090] When the processor 1102 executes the program, it implements the on-chip training method for memristor in-memory computing based on matrix low-rank decomposition provided in the above embodiments.

[0091] Furthermore, electronic devices also include:

[0092] Communication interface 1103 is used for communication between memory 1101 and processor 1102.

[0093] The memory 1101 is used to store computer programs that can run on the processor 1102.

[0094] The memory 1101 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0095] If the memory 1101, processor 1102, and communication interface 1103 are implemented independently, then the communication interface 1103, memory 1101, and processor 1102 can be interconnected via a bus to complete communication between them. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be divided into address buses, data buses, control buses, etc. For ease of representation, Figure 11The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0096] Optionally, in a specific implementation, if the memory 1101, processor 1102, and communication interface 1103 are integrated on a single chip, then the memory 1101, processor 1102, and communication interface 1103 can communicate with each other through an internal interface.

[0097] The processor 1102 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.

[0098] This invention also provides a computer program product, which, when executed by a processor, implements the above-described memristor-based in-memory computing on-chip training method based on low-rank matrix decomposition.

[0099] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the above-described memristor-based in-memory computing on-chip training method based on low-rank matrix decomposition.

[0100] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0101] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0102] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or N executable instructions for implementing custom logic functions or processes, and the scope of preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0103] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0104] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0105] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0106] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0107] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A memristor-based in-memory computing on-chip training method based on low-rank matrix decomposition, characterized in that, Includes the following steps: The target training network model is substituted into a pre-set non-ideal factor model for offline training to obtain a pre-trained model that can tolerate the actual non-ideal factors of the target in-memory computing chip. The pre-trained model is decomposed into a low-rank matrix using a low-rank matrix decomposition network to obtain the main intervention training network and the bypass network, specifically including: Obtain the main network layer of the pre-trained model and use the main network layer as the main intervention training network; The main network layer is decomposed into multiple two-layer subnetworks by using a matrix low-rank decomposition network, and these multiple two-layer subnetworks are used as the bypass network. The main intervention training network is deployed to the memristor array of the target in-memory computing chip, and the bypass network is deployed to the digital unit of the target in-memory computing chip to perform on-chip training on the memristor array and the digital unit, resulting in a trained memristor array, specifically including: The main intervention training network is deployed to the memristor array of the target in-memory computing chip for forward inference to obtain the first output; The bypass network is deployed to the digital unit of the target in-memory computing chip for forward inference to obtain the second output; The first output and the second output are compared with preset theoretical values, and the residuals are obtained based on the comparison results. The gradient of the bypass network is updated in reverse using the residual to obtain the trained memristor array.

2. The on-chip training method for memristor in-memory computing based on low-rank matrix decomposition according to claim 1, characterized in that, Also includes: Before offline training, the target training network model is quantized and noise-added, so that the quantized and noise-added target training network model can be substituted into the preset non-ideal factor model for offline training.

3. The memristor in-memory computing on-chip training method based on low-rank matrix decomposition according to claim 1, characterized in that, Each two-layer network consists of two fully connected layers or two convolutional layers.

4. A memristor-based in-memory computing on-chip training device based on low-rank matrix decomposition, characterized in that, include: The offline training module is used to train the target training network model by substituting it into a preset non-ideal factor model to obtain a pre-trained model that can tolerate the actual non-ideal factors of the target in-memory computing chip. The low-rank decomposition module is used to perform low-rank decomposition on the pre-trained model using a matrix low-rank decomposition network to obtain the main intervention training network and the bypass network, specifically including: Obtain the main network layer of the pre-trained model and use the main network layer as the main intervention training network; The main network layer is decomposed into multiple two-layer subnetworks by using a matrix low-rank decomposition network, and these multiple two-layer subnetworks are used as the bypass network. An on-chip training module is used to deploy the main intervention training network to the memristor array of the target in-memory computing chip, and to deploy the bypass network to the digital unit of the target in-memory computing chip, so as to perform on-chip training on the memristor array and the digital unit to obtain a trained memristor array. The on-chip training module includes: a digital matrix multiplication calculation unit, a first analog in-memory computing subunit, a second analog in-memory computing subunit, and a special function calculation unit. The first simulated in-memory computing subunit is used to deploy the main intervention training network to the memristor array of the target in-memory computing chip for forward inference to obtain the first output; A digital matrix multiplication calculation unit is used to deploy the bypass network to the digital unit of the target in-memory computing chip for forward inference to obtain a second output; A special function calculation unit is used to compare the first output and the second output with a preset theoretical value to obtain the residual; The second analog in-memory computing subunit is used to update the gradient of the bypass network in reverse using the residual, so as to obtain the trained memristor array.

5. An electronic device, characterized in that, include: The memory, the processor, and the computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the memristor in-memory computing on-chip training method based on matrix low-rank decomposition as described in any one of claims 1-3.

6. A computer program product, characterized in that, When the computer program / instruction is executed by the processor, it implements the on-chip training method for memristor-based in-memory computing according to any one of claims 1-3.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to implement the memristor in-memory computing on-chip training method based on matrix low-rank decomposition as described in any one of claims 1-3.

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