A heuristic quantum circuit decomposition method based on a quantum instruction set

Abstract

The application provides a heuristic quantum circuit decomposition method based on a quantum instruction set, and belongs to the technical field of quantum circuit decomposition. The problem of deep circuit depth and low fidelity when the quantum circuit is decomposed into a quantum instruction set is solved. The technical scheme is as follows: S1: converting the quantum circuit to be decomposed into a DAG; S2: quantum gate cancellation; S3: quantum gate exchange cancellation; S4: quantum gate merging; S5: quantum gate exchange merging; S6: converting the DAG into a preprocessed quantum circuit; S7: converting the preprocessed quantum circuit into a preprocessed DAG; S8: creating a quantum gate decomposition task; S9: quantum gate decomposition; S10: creating a storage DAG; S11: single-qubit gate merging; and S12: converting the storage DAG into a quantum circuit with completed heuristic decomposition. The application has the beneficial effects of reducing the depth of the decomposed quantum circuit and improving the fidelity of the quantum circuit.

Description

Technical Field

[0001] This invention relates to the field of quantum circuit decomposition technology, and in particular to a heuristic quantum circuit decomposition method based on quantum instruction sets. Background Technology

[0002] Quantum computing is a computational method based on the principles of quantum mechanics, utilizing qubits for information processing. Unlike classical computers, qubits can exist in superposition and entangled states, allowing quantum computers to process multiple possibilities in parallel, thus improving computational efficiency. Quantum computers use quantum gates to manipulate qubits to perform quantum computations. A quantum gate is a basic unit of operation used to perform specific operations on a qubit. Quantum computers have hardware limitations; they cannot execute complex quantum gates, but only those contained in their native gate set. Advanced quantum circuits contain a wide variety of quantum gates, thus requiring decomposition into the quantum gates supported by the computer itself.

[0003] A quantum instruction set is a set of operational instructions consisting of quantum gates used to perform specific computational tasks on a quantum computer. Similar to the instruction set architecture in classical computers, the quantum instruction set defines the basic operations that can be executed on a quantum computer. As described in the paper: McKinney, Evan, et al. "Parallel driving for fast quantum computing under speed limits." Proceedings of the 50th Annual International Symposium on Computer Architecture. 2023., increasing the fidelity of quantum circuits requires an efficient instruction set. These instructions include single-qubit operations (1Q gates) and two-qubit operations (2Q gates), etc. As described in the paper: Huang C, Wang T, Wu F, et al. Quantum instruction set design for performance[J]. Physical Review Letters, 2023, 130(7): 070601., the quantum instruction set is the interface provided to software by quantum hardware vendors. Quantum instruction sets provide an abstraction layer. Expressing quantum circuits using quantum instruction sets simply involves decomposing the quantum circuit into quantum gates within the instruction set, regardless of whether these gates can be directly executed on a quantum computer. Quantum instruction sets typically contain only a few 2Q and 1Q gates; therefore, decomposing the multi-qubit gates in the original circuit into 1Q and 2Q gates within a specified instruction set is the core of quantum instruction set implementation.

[0004] Among the methods for decomposing quantum circuits, as described in the paper: Jun Zhang, Jiri Vala, Shankar Sastry, and K Birgitta Whaley. Geometric theory of nonlocal two-qubit operations. Phys. Rev. A, 67(4): 042313, 2003., the KAK decomposition (Cartan KAK Decomposition) is a method for decomposing an arbitrary two-qubit gate into a specific sequence of basic gates. This is achieved by solving for the eigenvalues ​​of the two-qubit gates to be decomposed, which is a mathematically rigorous process. KAK decomposition guarantees the accuracy of the decomposition and can be implemented on most quantum computing platforms. However, the gate depth of the decomposed quantum circuit is relatively high.

[0005] Heuristic-based quantum circuit decomposition methods are designed using heuristics. These methods decompose circuits with the fewest possible 2Q gates while maintaining fidelity. Since the error rate of 2Q gates is much higher than that of 1Q gates, the number of 2Q gates after decomposition directly affects the fidelity of the quantum circuit. This approach is particularly suitable for quantum circuit decomposition methods operating as quantum instruction sets.

[0006] Currently, heuristic-based quantum circuit decomposition methods first convert the quantum circuit into a Directed Acyclic Graph (DAG), then traverse each quantum gate in the DAG that needs to be decomposed, and decompose them one by one. For example, the paper: L. Lao, P. Murali, M. Martonosi and D. Browne, "Designing Calibration and Expressivity-Efficient Instruction Sets for Quantum Computing," 2021 ACM / IEEE 48th Annual International Symposium on Computer Architecture (ISCA), Valencia, Spain, 2021, pp. 846-859, doi:10.1109 / ISCA52012.2021.00071, describes using the heuristic Broyden–Fletcher–Goldfarb–Shanno algorithm (BFGS) to decompose each quantum gate in the quantum circuit. However, this method does not consider the inherent problems of dealing with quantum circuits themselves, such as the possibility of preprocessing the quantum circuits. Preprocessing and optimizing the quantum circuits before decomposition could significantly reduce the workload. For example, for a quantum circuit with a depth of 2 containing two qubits (QuantumVolume(QV)), directly using heuristics to decompose the circuit into only those containing... The instruction sets for gates and U3 gates will contain 4 to 6 decomposed circuits. Gates. However, if the QV quantum circuit is preprocessed by merging these two gates before decomposing the quantum circuit, the decomposed circuit will contain only 2 to 3 gates. Therefore, current heuristic-based quantum circuit decomposition methods have significant technical shortcomings that can be improved.

[0007] In summary, the existing technology has the following problems that can be improved:

[0008] (1) In a quantum circuit, if there are two or more consecutive 2Q gates, and the two qubits they act on are the same, they will cancel each other out after interacting. That is, their respective matrices will become identity matrices after being multiplied in order. So, before decomposing the quantum circuit, the cancellation operation will be performed first, which will reduce the depth of the overall circuit and thus reduce the number of quantum gates in the decomposed quantum circuit.

[0009] (2) In a quantum circuit, if there are two or more consecutive 2Q gates, and the two qubits they operate on are the same, and there are only 1Q gates between these 2Q gates, then these quantum gates can be merged. The result of merging is a new 2Q gate. Therefore, before decomposing the quantum circuit, merging is performed first, which will reduce the depth of the overall circuit and thus reduce the number of quantum gates in the decomposed quantum circuit.

[0010] (3) In a quantum circuit, if there is no opportunity to directly cancel or merge gates, but there are two quantum gates that can exchange positions, and after the position exchange, an opportunity to cancel or merge quantum gates is generated, then performing the gate exchange operation and then the gate cancellation or gate merging operation will also reduce the overall circuit depth first, and thus reduce the number of quantum gates in the decomposed quantum circuit. Summary of the Invention

[0011] The purpose of this invention is to provide a heuristic quantum circuit decomposition method based on quantum instruction sets. By adding a preprocessing step, the heuristic quantum circuit decomposition method is improved and optimized to reduce the circuit depth when decomposing quantum circuits into quantum instruction sets and improve the fidelity of quantum circuits.

[0012] To achieve the aforementioned objectives, the present invention employs the following technical solution: a heuristic quantum circuit decomposition method based on quantum instruction sets, comprising the following steps:

[0013] Step S1: Convert the quantum circuit to be decomposed into a Directed Acyclic Graph (DAG). Each node in the DAG is a quantum gate in the quantum circuit to be decomposed, including the type of the quantum gate, the qubits it operates on, and the corresponding matrix representation information. The directed edges in the DAG are added according to the dependencies of all quantum gates in the quantum circuit to be decomposed. Because the DAG can clearly represent the dependencies and execution order of quantum gates in the quantum circuit, the sequential relationship of quantum gate operations is more intuitive and clear. By converting the quantum circuit to be decomposed into a DAG, a preprocessing step for the quantum circuit can be performed.

[0014] Step S2: Define the set of quantum gates that can be canceled, and define the cancellation rules of quantum gates to perform the quantum gate cancellation step; by canceling the quantum gates that can be directly canceled in the quantum circuit to be decomposed, the number of quantum gates in the quantum circuit to be decomposed is reduced, so as to optimize the quantum circuit to be decomposed.

[0015] Step S3: Define the set of quantum gates that can be exchanged, and define the exchange rules of quantum gates to perform the quantum gate exchange cancellation step; by exchanging quantum gates, new quantum gate cancellation opportunities are generated in the quantum circuit to be decomposed, and after the quantum gate exchange cancellation, the number of quantum gates in the quantum circuit to be decomposed is further reduced in order to optimize the quantum circuit to be decomposed.

[0016] Step S4: Define the set of quantum gates that can be merged and define the merging rules of quantum gates to perform the merging steps of quantum gates; by merging the quantum gates that can be merged in the quantum circuit to be decomposed, the number of quantum gates in the quantum circuit to be decomposed can be reduced, so as to optimize the quantum circuit to be decomposed.

[0017] Step S5: Quantum gate exchange and merging step; By exchanging quantum gates, new quantum gate merging opportunities are generated in the quantum circuit to be decomposed. After the quantum gate exchange and merging, the number of quantum gates in the quantum circuit to be decomposed is further reduced in order to optimize the quantum circuit to be decomposed.

[0018] Step S6: Convert the DAG into a quantum circuit according to the order of the quantum gate nodes in the DAG, which is the preprocessed quantum circuit; this is because the DAG can determine the execution order of the quantum gates through topological sorting, ensuring that all dependencies are satisfied; converting the DAG into a preprocessed quantum circuit completes the preprocessing work of the quantum circuit.

[0019] Step S7: Convert the preprocessed quantum circuit into a preprocessed DAG; each node in the DAG is a quantum gate in the preprocessed quantum circuit, which contains information such as the type of the quantum gate, the qubits it operates on, and the corresponding matrix representation; the directed edges in the DAG are added according to the dependencies of all quantum gates in the quantum circuit to be decomposed; because the DAG can clearly represent the dependencies and execution order of quantum gates in the quantum circuit, the sequential relationship of quantum gate operations is more intuitive and clear; by converting the preprocessed quantum circuit into a DAG, the heuristic decomposition step of the preprocessed quantum circuit can be performed;

[0020] Step S8: Traverse the preprocessed DAG and create a decomposition task for each multi-qubit gate; because multi-qubit gates in a quantum circuit need to be decomposed into quantum gates contained in the quantum instruction set;

[0021] Step S9: Execute the quantum gate decomposition task in parallel; parallel execution allows the decomposition of multiple quantum gates to be processed simultaneously, rather than sequentially; this can significantly reduce the overall computation time.

[0022] Step S10: Create a storage DAG to store the decomposed quantum circuits; in order to store the decomposed quantum circuits, first store the decomposed quantum circuits in the DAG;

[0023] Step S11: Merge the single-qubit gate nodes in the stored DAG; by merging the single-qubit gates that can be merged in the decomposed quantum circuit, the number of single-qubit gates in the decomposed quantum circuit can be reduced, so as to optimize the decomposed quantum circuit.

[0024] Step S12: Convert the stored DAG into a quantum circuit according to the order of the quantum gate nodes in the stored DAG, which is the quantum circuit for heuristic decomposition. Convert the stored DAG into a preprocessed quantum circuit to complete the heuristic decomposition of the quantum circuit.

[0025] Step S2 specifically includes the following steps:

[0026] S21: Define the set of quantum gates that can cancel each other out;

[0027] The set containing only single-qubit gates X, Y, Z, and H is defined as U. c ;

[0028] The set containing only two-qubit gates (CX, CY, CZ, and CH) is defined as CU. c ;

[0029] The set containing only two-qubit SWAP gates is defined as G. sw ;

[0030] As shown in Table 1;

[0031] Table 1. Set of quantum gates capable of cancellation

[0032] <![CDATA[U c ]]> {X,Y,Z,H} <![CDATA[CU c ]]> {CX,CY,CZ,CH} <![CDATA[G sw ]]> {SWAP}

[0033] S22: Define the cancellation rule for quantum gates;

[0034] Definition of the cancellation rule for quantum gates I: If n adjacent two-qubit gates are identical and belong to CU c A set of n two-qubit gates, where the control bits and target bits of these n two-qubit gates are the same. If n is even, then these n two-qubit gates can cancel each other out.

[0035] If n is odd, the first n-1 two-qubit gates can cancel each other out, leaving 1 two-qubit gate remaining.

[0036] Definition of Quantum Gate Cancellation Rule II: If n adjacent two-qubit gates are identical and belong to G...sw A set of n two-qubit gates, where the two qubits acting on these n two-qubit gates are the same. If n is even, then these n two-qubit gates can cancel each other out.

[0037] If n is odd, the first n-1 two-qubit gates can cancel each other out, leaving 1 two-qubit gate remaining.

[0038] Where n≥2;

[0039] S23: Cancellation step of quantum gate;

[0040] Traverse the quantum gate nodes in the DAG. If there are n consecutive two-qubit gate nodes, these two-qubit gate nodes are directly connected by edges in the DAG, and the two-qubit gates represented by these nodes satisfy quantum gate cancellation rule I or quantum gate cancellation rule II.

[0041] If n is even, these two-qubit gates can cancel each other out;

[0042] If n is odd, the first n-1 quantum gates in these two-qubit gates can cancel each other out;

[0043] In a DAG, the predecessor node of the first canceled two-qubit gate node in the topological order directly points to the successor node of the last canceled two-qubit gate node in the topological order. Deleting the nodes representing these two-qubit gates completes the cancellation operation of these two-qubit gate nodes in the DAG.

[0044] If there are not n consecutive two-qubit gate nodes, or if there are n consecutive two-qubit gate nodes, but the two-qubit gates represented by these nodes do not satisfy the cancellation rule I or the cancellation rule II of quantum gates, then there are no quantum gates that can cancel each other out.

[0045] Repeat step S23 until there are no two-qubit gate nodes in the DAG that can be directly canceled; the cancellation of the quantum gates is complete.

[0046] Where: n≥2;

[0047] Step S3 specifically includes the following steps:

[0048] S31: Define the set of quantum gates that can be exchanged;

[0049] This will include only single-qubit gates: P(λ) gate, RZ(λ) gate, S gate, and S... + Door, T-door, T + The set of gates, Z gates, is defined as G. c ;

[0050] Will only include single-qubit gates SX gate, SX + The set of gates, X-gates, and RX(θ) gates is defined as G. x ;

[0051] The set containing only single-qubit gates Y and RY(θ) is defined as G. y ;

[0052] This will include only single-qubit gates: P(λ) gate, RZ(λ) gate, S gate, and S... + Door, T-door, T + The set of gates, U1(λ) gates, and Z gates is defined as G. z ;

[0053] G is defined as a set containing only single-qubit gates (H gates). h ;

[0054] U in step S21 c and CU c They are all sets of quantum gates that can be exchanged;

[0055] As shown in Table 2;

[0056] Table 2. Set of quantum gates that can be exchanged.

[0057] <![CDATA[U c ]]> {X,Y,Z,H} <![CDATA[CU c ]]> {CX,CY,CZ,CH} <![CDATA[G c ]]> <![CDATA[{P(λ),RZ(λ),S,S + ,T,T + ,Z}]]> <![CDATA[G x ]]> <![CDATA[{SX,SX + ,X,RX(θ)}]]> <![CDATA[G y ]]> {Y,RY(θ)} <![CDATA[G z ]]> <![CDATA[{P(λ),RZ(λ),S,S + ,T,T + ,U1(λ),Z}]]> <![CDATA[G h ]]> {H}

[0058] S32: Define the commutation rules for quantum gates;

[0059] Definition of the commutation rule for quantum gates I: If a two-qubit gate belongs to CU c A gate set, where the single-qubit gate adjacent to this two-qubit gate is located on the control bit of this two-qubit gate, and this single-qubit gate belongs to G. c If the two-qubit gate and the single-qubit gate satisfy the above conditions, then their positions can be interchanged; if the two-qubit gate and the single-qubit gate do not satisfy the above conditions, then their positions cannot be interchanged.

[0060] Quantum gate commutation rule II: If a two-qubit gate is a CX gate, the adjacent single-qubit gate is located on the target qubit of the two-qubit gate, and this single-qubit gate belongs to the G category. x If the two quantum gates are a set of gates, then the positions of the two quantum gates can be interchanged; if the two quantum gates and the one quantum gate do not satisfy the above conditions, then the positions of the two quantum gates cannot be interchanged.

[0061] Quantum gate commutation rule III: If two identical two-qubit gates are adjacent and belong to the CU... cIf two two-qubit gates are in a set such that the control bit of one of them is different from the target bit of the other, then the positions of the two two-qubit gates can be swapped; if the two two-qubit gates do not satisfy the above condition, then the positions of the two gates cannot be swapped.

[0062] In addition to the CX gate, the two-qubit gate can also be a CY gate, a CZ gate, or a CH gate;

[0063] Single-qubit gates belong to G x In addition to the gate collection, it can also provide G y Gate set or G z Gate set or G h Gate collection.

[0064] S33: The steps of cancellation after exchange in a quantum gate;

[0065] Traverse the quantum gate nodes in the DAG. At this point, there are no more two-qubit gate nodes that can directly cancel each other out. However, if there are two quantum gate nodes that represent quantum gates that satisfy quantum gate swapping rule I, quantum gate swapping rule II, or quantum gate swapping rule III, then the order of these two quantum gates can be swapped. If swapping the order of these two quantum gates generates new conditions that satisfy quantum gate cancellation, then swap the nodes representing these two quantum gates in the DAG and perform step S23. Repeat step S33 until there are no more quantum gate nodes in the DAG that can cancel each other out after swapping. At this point, the quantum gate swapping cancellation operation is complete.

[0066] Step S4 specifically includes the following steps:

[0067] S41: Define the set of quantum gates that can be merged;

[0068] The set containing all single-qubit gate SU(2) gates is defined as G. s ;

[0069] The set containing all two-qubit gate SU(4) gates is defined as G. d ;

[0070] The two-qubit gate resulting from the merging of quantum circuits will be defined as U. m ;

[0071] As shown in Table 3:

[0072] Table 3. Set of quantum gates that can be merged.

[0073] <![CDATA[G s ]]> {SU(2)} <![CDATA[G d ]]> {SU(4)} <![CDATA[U m ]]> Synthesized quantum gate

[0074] S42: Define the merging rules for quantum gates;

[0075] The merging rule for quantum gates is defined as follows: In a quantum circuit, if multiple consecutive two-qubit gates operate on only two qubits, and these two-qubit gates are surrounded only by single-qubit gates, with no multi-qubit gates operating on other qubits, then these quantum gates can be merged into an equivalent two-qubit gate, denoted as U. m ;

[0076] If no quantum gates satisfy the above conditions, then these quantum gates cannot be merged;

[0077] S43: The merging steps of quantum gates;

[0078] Traversing the quantum gate nodes in the DAG, there are no longer any quantum gate nodes that can be canceled or swapped to cancel each other out. However, if there are two or more consecutive quantum gate nodes, and the quantum gates represented by these nodes satisfy the merging rules defined for quantum gates, then these two-qubit gates and one-qubit gates can be merged. The result of the merger is denoted as U. m ;

[0079] U m It is a two-qubit gate, U m The matrix representation is the product of the matrix representation of the tensor product of the merged single-qubit gate and the single-qubit gate I gate and the matrix representation of the merged two-qubit gate multiplied in the order of action of the quantum gates;

[0080] In a DAG, the nodes representing these merged quantum gates are replaced with a new node, namely the synthesized two-qubit gate U. m Nodes;

[0081] Repeat step S43 until there are no more quantum gate nodes in the DAG that can be directly merged.

[0082] Step S5 specifically includes the following steps:

[0083] If there are two two-qubit gate nodes, and the two-qubit gates represented by these two two-qubit gate nodes satisfy the commutation rule III of the quantum gate, then the order of these two two-qubit gates can be interchanged.

[0084] If swapping the order of these two quantum gates results in new conditions for merging the quantum gates, then swap the nodes representing these two two-qubit gates in the DAG and proceed with step S43.

[0085] Repeat step S5 until there are no more quantum gate nodes in the entire DAG that meet the conditions for merging after exchanging; the quantum gate merging is complete.

[0086] Step S8: Traverse the preprocessed DAG; create a decomposition task for each multi-qubit gate;

[0087] A decomposition task is created for each multi-qubit gate according to the topological order of the quantum gate nodes in the preprocessed DAG. The decomposition task is to decompose the multi-qubit gate to be decomposed into quantum circuits containing only the quantum gates contained in the quantum instruction set.

[0088] Step S9 specifically includes the following steps:

[0089] The decomposition task is performed in parallel. The decomposition of gates with different levels is verified iteratively. The Broyden–Fletcher–Goldfarb–Shanno algorithm (BFGS) is used to decompose each quantum gate with the fewest levels while satisfying the fidelity requirement of each quantum gate to be decomposed. The decomposition scheme with the lowest fidelity among all decomposition schemes at the decomposition level is recorded as the decomposition scheme of the quantum gate to be decomposed.

[0090] The BFGS decomposition method is used to decompose the quantum gates to be decomposed in parallel. The BFGS decomposition method uses the generated constraints and cost function to optimize through multiple attempts to obtain a smaller number of decomposition layers. By evaluating the fidelity and selecting the decomposition scheme with the best fidelity at the current number of decomposition layers, a decomposed quantum circuit is generated.

[0091] When all decomposition tasks have been completed, all multi-qubit gates in the quantum circuit have been decomposed into quantum circuits containing only the quantum gates included in the quantum instruction set.

[0092] Step S10 specifically includes the following steps:

[0093] Add the quantum registers and classical registers from the preprocessed quantum circuit to the storage DAG;

[0094] For single-qubit gates in the preprocessed quantum circuit, they are added as nodes to the storage DAG;

[0095] For the two-qubit gate in the preprocessed quantum circuit, the quantum gates in the decomposed quantum circuit are added as nodes to the storage DAG.

[0096] Step S11 specifically includes the following steps:

[0097] By traversing the quantum gate nodes in the DAG, if there are two or more single-qubit gate nodes representing consecutive single-qubit gates that act on the same qubit, then these single-qubit gates can be merged.

[0098] The result of merging is a parameterized single-qubit gate contained in a quantum instruction. The matrix representation of this synthesized parameterized single-qubit gate is the product of the matrix representations of the merged single-qubit gates multiplied in the order of action of the quantum gates.

[0099] In the storage DAG, the nodes representing these merged quantum gates are replaced with a new node, which is the node of the synthesized single-qubit gate;

[0100] Repeat step S11 until there are no single-qubit gate nodes in the stored DAG that can be directly merged.

[0101] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0102] (1) Reduce the depth of the quantum circuit after decomposition

[0103] The improved heuristic quantum circuit decomposition method preprocesses the original quantum circuit by canceling and merging redundant quantum gates before decomposing the circuit based on a specified instruction set. This approach reduces the number of quantum gates required for decomposition, thereby reducing the depth of the decomposed circuit. The more times cancelable and mergeable quantum gates appear in the quantum circuit to be decomposed, the greater the reduction in circuit depth after preprocessing, and consequently, the greater the reduction in the final depth of the decomposed quantum circuit.

[0104] (2) Improve the overall fidelity of quantum circuits

[0105] By preprocessing, the depth of the decomposed circuit is reduced, which means a decrease in the number of quantum gates, especially 2Q gates. The error rate of 2Q gates is not negligible; the more 2Q gates appear in the circuit, the greater the circuit distortion. Therefore, optimizing the circuit through preprocessing before decomposition can improve the overall fidelity of the quantum circuit.

[0106] (3) Improve the expressive power of quantum instruction sets

[0107] Because of the limitations of current heuristic quantum circuit decomposition methods, directly using this method to evaluate and screen instruction sets for different quantum circuits also has its shortcomings. The improved heuristic quantum circuit decomposition method preprocesses and optimizes the circuit to be decomposed before performing quantum circuit decomposition. Using the improved decomposition method to evaluate and screen instruction sets allows for the selection of instruction sets more suitable for different quantum circuits. After selecting better instruction sets suitable for different quantum circuits using a better decomposition method, not only is the number of quantum gates reduced and the fidelity of the quantum circuit improved, but more importantly, the expressive power of the instruction set is enhanced. For different circuits, a good decomposition method can correspondingly improve the expressive power of a specified instruction set. Attached Figure Description

[0108] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0109] Figure 1 This is a schematic diagram of the quantum circuit after decomposition using the quantum instruction set in this invention; wherein: (a) is a schematic diagram of the original quantum circuit; (b) is a schematic diagram of the decomposed quantum circuit;

[0110] Figure 2 This is a schematic diagram of the quantum circuit after heuristic decomposition of the 2Q gate according to the present invention;

[0111] Figure 3 This is a schematic diagram of the heuristic quantum circuit decomposition method of the present invention;

[0112] Figure 4 This is a schematic diagram of the improved heuristic quantum circuit decomposition method of the present invention;

[0113] Figure 5 This is a schematic diagram of the cancellation of quantum gates in this invention; wherein: (a) is CU c (a) is a diagram illustrating the cancellation of gate sets; (b) is G sw A diagram illustrating the cancellation of gate sets;

[0114] Figure 6 This is a schematic diagram illustrating the exchange between the single-qubit gate and the two-qubit gate of the present invention; wherein: (a) is the CU c Door and G c (a) is a diagram illustrating the exchange of gate sets; (b) shows the CX gate and the G gate. x (c) is a diagram illustrating the exchange of gate sets; CY gate and G gate. y Diagram of gate set exchange; (d) shows the CZ gate and G gate. z Diagram of gate set exchange; (e) shows the CH gate and G gate. h Diagram of gate set swapping;

[0115] Figure 7 For the present invention CU c A diagram illustrating the exchange of gate sets; where: (a) is the CU c (a) is a diagram showing the switching of bits when the gate only controls the same bit; (b) is a CU. c A diagram illustrating the swapping process when only the target bits of the gate are the same;

[0116] Figure 8 The cancellation is achieved by exchanging quantum gates according to the present invention; wherein: (a) is a schematic diagram of gate cancellation after exchanging a single-qubit gate with a two-qubit gate; (b) is a schematic diagram of gate cancellation after exchanging two two-qubit gates;

[0117] Figure 9 This is a schematic diagram illustrating the merging of quantum gates in this invention;

[0118] Figure 10 The present invention provides a diagram of the merging of quantum circuits after the exchange; wherein: (a) is a schematic diagram of the original quantum circuit; (b) is a schematic diagram of the quantum circuit after the exchange; and (c) is a schematic diagram of the merged quantum circuit.

[0119] Figure 11 This is a comparative schematic diagram of the heuristic decomposition method and the heuristic decomposition method after preprocessing in Embodiment 2 of the present invention; wherein: (a) is a schematic diagram of the QV quantum circuit; (b) is a schematic diagram of the quantum circuit after decomposition; (c) is a schematic diagram of the quantum circuit after preprocessing (a); (d) is a schematic diagram of the quantum circuit after preprocessing and then decomposition.

[0120] Figure 12 This is a schematic diagram of the original quantum circuit in Embodiment 3 of the present invention;

[0121] Figure 13 This is a schematic diagram of the preprocessed quantum circuit in Embodiment 3 of the present invention;

[0122] Figure 14 This is a schematic diagram of the random QV quantum circuit in Embodiment 4 of the present invention;

[0123] Figure 15 This is a schematic diagram of the heuristic quantum circuit decomposition before improvement in Embodiment 4 of the present invention;

[0124] Figure 16 This is a schematic diagram of the preprocessed QV quantum circuit in Embodiment 4 of the present invention;

[0125] Figure 17 This is a schematic diagram of the heuristic quantum circuit decomposition performed after preprocessing in Embodiment 4 of the present invention. Detailed Implementation

[0126] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Of course, the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0127] Expressing quantum circuits using quantum instruction sets simply involves decomposing the quantum circuit into quantum gates contained within the quantum instruction set, regardless of whether these quantum gates can be directly executed on a quantum computer. Quantum instruction sets typically contain only a few 2Q and 1Q gates. Figure 1 This is an example diagram illustrating the decomposition of a quantum circuit into a quantum instruction set. Among them, Figure 1 The quantum circuit in (a) has two qubits and contains a random two-qubit gate. Figure 1 The quantum circuit in (b) is... Figure 1 The quantum circuit in (a) is decomposed into a quantum circuit after the quantum instruction set, where the instruction set consists of iSWAP gates and U gates.

[0128] Figure 2 The image shows an example quantum circuit diagram after decomposing a 2Q gate using a heuristic decomposition method, where the selected instruction set is fSim gates and U3 gates. The quantum circuit after decomposing the 2Q gate consists of alternating 1Q and 2Q gates in the instruction set, and the number of 2Q gates after decomposition is the layer number.

[0129] Figure 3 The process of a heuristic quantum circuit decomposition method is demonstrated. However, this decomposition method also has its drawbacks.

[0130] Current heuristic-based quantum circuit decomposition methods decompose each quantum gate individually. However, these methods do not consider the inherent problems of dealing with quantum circuits themselves, such as the possibility of preprocessing the quantum circuits before decomposition, which could significantly reduce the workload.

[0131] Therefore, current heuristic-based quantum circuit decomposition methods have significant technical shortcomings that can be improved. It is necessary to improve existing heuristic quantum circuit decomposition methods by preprocessing the quantum circuits to be decomposed before decomposition.

[0132] Example 1

[0133] See Figure 4 As shown, the present invention provides a technical solution: a heuristic quantum circuit decomposition method based on a quantum instruction set, the method comprising the following steps:

[0134] Step S1: Convert the quantum circuit to be decomposed into a Directed Acyclic Graph (DAG). Each node in the DAG is a quantum gate in the quantum circuit to be decomposed, including the type of the quantum gate, the qubits it operates on, and the corresponding matrix representation information. The directed edges in the DAG are added according to the dependencies of all quantum gates in the quantum circuit to be decomposed. Because the DAG can clearly represent the dependencies and execution order of quantum gates in the quantum circuit, the sequential relationship of quantum gate operations is more intuitive and clear. By converting the quantum circuit to be decomposed into a DAG, a preprocessing step for the quantum circuit can be performed.

[0135] Step S2: Define the set of quantum gates that can be canceled, and define the cancellation rules of quantum gates to perform the quantum gate cancellation step; by canceling the quantum gates that can be directly canceled in the quantum circuit to be decomposed, the number of quantum gates in the quantum circuit to be decomposed is reduced, so as to optimize the quantum circuit to be decomposed.

[0136] Step S2 specifically includes the following steps:

[0137] S21: Define the set of quantum gates that can cancel each other out;

[0138] The set containing only single-qubit gates X, Y, Z, and H is defined as U. c ;

[0139] The set containing only two-qubit gates (CX, CY, CZ, and CH) is defined as CU. c ;

[0140] The set containing only two-qubit SWAP gates is defined as G. sw ;

[0141] As shown in Table 1;

[0142] Table 1. Set of quantum gates capable of cancellation

[0143] <![CDATA[U c ]]> {X,Y,Z,H} <![CDATA[CU c ]]> {CX,CY,CZ,CH} <![CDATA[G sw ]]> {SWAP}

[0144] S22: Define the cancellation rule for quantum gates;

[0145] Definition of the cancellation rule for quantum gates I: If n adjacent two-qubit gates are identical and belong to CU c A set of n two-qubit gates, where the control qubits and target qubits are the same. If n is even, the n two-qubit gates can cancel each other out.

[0146] If n is odd, the first n-1 two-qubit gates can cancel each other out, leaving 1 two-qubit gate remaining.

[0147] Definition of Quantum Gate Cancellation Rule II: If n adjacent two-qubit gates are identical and belong to G... sw A set of n two-qubit gates, where the two qubits acting on these n two-qubit gates are the same. If n is even, then these n two-qubit gates can cancel each other out.

[0148] If n is odd, the first n-1 two-qubit gates can cancel each other out, leaving 1 two-qubit gate remaining.

[0149] Where n≥2;

[0150] refer to Figure 5 As shown in (a), in a quantum circuit, the two two-qubit gates are identical and belong to the CU. c A set (e.g., two CX gates) where these two two-qubit gates are adjacent and the control qubit and target qubit are the same, and these two two-qubit gates can cancel each other out;

[0151] refer to Figure 5 As shown in (b), the two two-qubit gates are identical and belong to G. sw A set (such as two SWAP gates) where the two two-qubit gates are adjacent and the two qubits that act are the same can cancel each other out;

[0152] S23: Cancellation step of quantum gate;

[0153] Traverse the quantum gate nodes in the DAG. If there are n consecutive two-qubit gate nodes, these two-qubit gate nodes are directly connected by edges in the DAG, and the two-qubit gates represented by these nodes satisfy quantum gate cancellation rule I or quantum gate cancellation rule II.

[0154] If n is even, these two-qubit gates can cancel each other out;

[0155] If n is odd, the first n-1 quantum gates in these two-qubit gates can cancel each other out;

[0156] In a DAG, the predecessor node of the first canceled two-qubit gate node in the topological order directly points to the successor node of the last canceled two-qubit gate node in the topological order. Deleting the nodes representing these two-qubit gates completes the cancellation operation of these two-qubit gate nodes in the DAG.

[0157] If there are no such n consecutive two-qubit gate nodes, or if there are such n consecutive two-qubit gate nodes, but the two-qubit gates represented by each of these nodes do not satisfy the cancellation rule I or the cancellation rule II of quantum gates, then there are no quantum gates that can cancel each other out.

[0158] Repeat step S23 until there are no two-qubit gate nodes in the DAG that can be directly canceled; the cancellation of the quantum gates is complete.

[0159] Where: n≥2.

[0160] Step S3: Define the set of quantum gates that can be exchanged, and define the exchange rules of quantum gates to perform the quantum gate exchange cancellation step; by exchanging quantum gates, new quantum gate cancellation opportunities are generated in the quantum circuit to be decomposed, and after the quantum gate exchange cancellation, the number of quantum gates in the quantum circuit to be decomposed is further reduced in order to optimize the quantum circuit to be decomposed.

[0161] Step S3 specifically includes the following steps:

[0162] S31: Define the set of quantum gates that can be exchanged;

[0163] This will include only single-qubit gates: P(λ) gate, RZ(λ) gate, S gate, and S... + Door, T-door, T + The set of gates, Z gates, is defined as G. c ;

[0164] Will only include single-qubit gates SX gate, SX + The set of gates, X-gates, and RX(θ) gates is defined as G. x ;

[0165] The set containing only single-qubit gates Y and RY(θ) is defined as G. y ;

[0166] This will include only single-qubit gates: P(λ) gate, RZ(λ) gate, S gate, and S... + Door, T-door, T + The set of gates, U1(λ) gates, and Z gates is defined as G. z ;

[0167] G is defined as a set containing only single-qubit gates (H gates). h ;

[0168] U in step S21 c and CU c They are all sets of quantum gates that can be exchanged;

[0169] As shown in Table 2;

[0170] Table 2. Set of quantum gates that can be exchanged.

[0171] <![CDATA[U c ]]> {X,Y,Z,H} <![CDATA[CU c ]]> {CX,CY,CZ,CH} <![CDATA[G c ]]> <![CDATA[{P(λ),RZ(λ),S,S + ,T,T + ,Z}]]> <![CDATA[G x ]]> <![CDATA[{SX,SX + ,X,RX(θ)}]]> <![CDATA[G y ]]> {Y,RY(θ)} <![CDATA[G z ]]> <![CDATA[{P(λ),RZ(λ),S,S + ,T,T + ,U1(λ),Z}]]> <![CDATA[G h ]]> {H}

[0172] S32: Define the commutation rules for quantum gates;

[0173] Definition of the commutation rule for quantum gates I: If a two-qubit gate belongs to CU c A gate set, where the single-qubit gate adjacent to this two-qubit gate is located on the control bit of this two-qubit gate, and this single-qubit gate belongs to G. c If the two-qubit gate and the single-qubit gate satisfy the above conditions, then their positions can be interchanged; if the two-qubit gate and the single-qubit gate do not satisfy the above conditions, then their positions cannot be interchanged.

[0174] Quantum gate commutation rule II: If a two-qubit gate is a CX gate, the adjacent single-qubit gate is located on the target qubit of the two-qubit gate, and this single-qubit gate belongs to the G category. x If the two quantum gates are a set of gates, then the positions of the two quantum gates can be interchanged; if the two quantum gates and the one quantum gate do not satisfy the above conditions, then the positions of the two quantum gates cannot be interchanged.

[0175] Quantum gate commutation rule III: If two identical two-qubit gates are adjacent and belong to the CU... c If two two-qubit gates are in a set such that the control bit of one of them is different from the target bit of the other, then the positions of the two two-qubit gates can be swapped; if the two two-qubit gates do not satisfy the above condition, then the positions of the two gates cannot be swapped.

[0176] In addition to the CX gate, the two-qubit gate can also be a CY gate, a CZ gate, or a CH gate;

[0177] Single-qubit gates belong to G x In addition to the gate collection, it can also provide G y Gate set or G z Gate set or G h Gate collection.

[0178] refer to Figure 6 As shown in (a), in a quantum circuit, there is a two-qubit gate belonging to CU. c A set (e.g., a CX gate), and a single-qubit gate adjacent to these two two-qubit gates and located on the control qubit of that two-qubit gate belongs to G. c A set (such as an S-gate) can have its two-qubit gate swapped with a single-qubit gate;

[0179] refer to Figure 6 As shown in (b), in the quantum circuit, there is a two-qubit gate called the CX gate, and the single-qubit gate adjacent to these two two-qubit gates and located on the target qubit of the two-qubit gate belongs to the G gate. x A set (such as an S-gate) can have its two-qubit gate swapped with its single-qubit gate; similarly, refer to... Figure 6 (c), Figure 6 (d), Figure 6 As shown in (e), under the above conditions, the CY gate and G... y Set, CZ gate and G z Sets, CH gates and G h Sets can also be exchanged;

[0180] refer to Figure 7 (a), Figure 7 As shown in (b), in a quantum circuit, there are two identical two-qubit gates adjacent to each other and belonging to the CU. c In a set (such as a CX gate), if the control bit of the preceding two-qubit gate is different from the target bit of the following two-qubit gate, and the control bit of the following two-qubit gate is different from the target bit of the preceding two-qubit gate, the positions of these two two-qubit gates can be swapped.

[0181] S33: The steps of cancellation after exchange in a quantum gate;

[0182] Traverse the quantum gate nodes in the DAG. At this point, there are no more two-qubit gate nodes that can directly cancel each other out. However, if there are two quantum gate nodes that represent quantum gates that satisfy quantum gate swapping rule I, quantum gate swapping rule II, or quantum gate swapping rule III, then the gate order of these two quantum gates can be swapped. If swapping the gate order of these two quantum gates generates new conditions that satisfy quantum gate cancellation, then swap the nodes representing these two quantum gates in the DAG and perform step S23. Repeat step S33 until there are no more quantum gate nodes in the DAG that can cancel each other out after swapping. At this point, the quantum gate swapping cancellation operation is complete.

[0183] refer to Figure 8 As shown in (a), in a quantum circuit, there are two identical two-qubit gates belonging to CU. c Gate sets (such as CX gates) where the control bits and target bits of the two two-qubit gates are identical, and there is a G gate between the two two-qubit gates. c The door is located in these two CUs c At this moment, on the control qubits of the gate, these two CUs c Since the doors are not adjacent, they cannot cancel each other out. However, if the first CU is checked first... c Door and Gc If the positions of the doors are swapped, then after the swap, the two CUs... c If the gates are adjacent and satisfy the cancellation condition, then a quantum gate cancellation operation can be performed; the result is that only one G remains. c Door;

[0184] refer to Figure 8 As shown in (b), in the quantum circuit, there are three identical two-qubit gates belonging to the CU. c Gate sets (such as CX gates), the first and last CUs c The control bits and target bits of the gate are the same, and the CU in the middle is the same. c With the other two CUs c The control bits of the gates are the same, but the target bits are different. At this time, the three CUs c There is no chance of mutual cancellation between the gates, but if the first CU is treated first... c Door and the second CU c If the positions of the doors are swapped, then the two CUs behind them will... c If the gate satisfies the cancellation condition, then quantum gate cancellation can be performed; the result is that only one CU remains. c Door.

[0185] Step S4: Define the set of quantum gates that can be merged and define the merging rules of quantum gates to perform the merging steps of quantum gates; by merging the quantum gates that can be merged in the quantum circuit to be decomposed, the number of quantum gates in the quantum circuit to be decomposed can be reduced, so as to optimize the quantum circuit to be decomposed.

[0186] Step S4 specifically includes the following steps:

[0187] S41: Define the set of quantum gates that can be merged;

[0188] The set containing all single-qubit gate SU(2) gates is defined as G. s ;

[0189] The set containing all two-qubit gate SU(4) gates is defined as G. d ;

[0190] The two-qubit gate resulting from the merging of quantum circuits will be defined as U. m ;

[0191] As shown in Table 3:

[0192] Table 3. Set of quantum gates that can be merged.

[0193] <![CDATA[G s ]]> {SU(2)} <![CDATA[G d ]]> {SU(4)} <![CDATA[U m ]]> Synthesized quantum gate

[0194] S42: Define the merging rules for quantum gates;

[0195] The merging rule for quantum gates is defined as follows: In a quantum circuit, if multiple consecutive two-qubit gates operate on only two qubits, and these two-qubit gates are surrounded only by single-qubit gates, with no multi-qubit gates operating on other qubits, then these quantum gates can be merged into an equivalent two-qubit gate, denoted as U. m ;

[0196] If no quantum gates satisfy the above conditions, then these quantum gates cannot be merged;

[0197] refer to Figure 9 As shown, in a quantum circuit, there are multiple consecutive two-qubit gates and single-qubit gates. These quantum gates operate only on two qubits; there are no multi-qubit gates that operate on other qubits. These quantum gates can be combined into an equivalent two-qubit gate U. m Door.

[0198] S43: The merging steps of quantum gates;

[0199] Traversing the quantum gate nodes in the DAG, there are no longer any quantum gate nodes that can be canceled or swapped to cancel each other out. However, if there are two or more consecutive quantum gate nodes, and the quantum gates represented by these nodes satisfy the merging rules defined for quantum gates, then these two-qubit gates and one-qubit gates can be merged. The result of the merger is denoted as U. m ;

[0200] U m It is a two-qubit gate, U m The matrix representation is the product of the matrix representation of the tensor product of the merged single-qubit gate and the single-qubit gate I gate and the matrix representation of the merged two-qubit gate multiplied in the order of action of the quantum gates;

[0201] In a DAG, the nodes representing these merged quantum gates are replaced with a new node, namely the synthesized two-qubit gate U. m Nodes;

[0202] Repeat step S43 until there are no more quantum gate nodes in the DAG that can be directly merged.

[0203] Step S5: Quantum gate exchange and merging step; By exchanging quantum gates, new quantum gate merging opportunities are generated in the quantum circuit to be decomposed. After the quantum gate exchange and merging, the number of quantum gates in the quantum circuit to be decomposed is further reduced in order to optimize the quantum circuit to be decomposed.

[0204] Step S5 specifically includes the following steps:

[0205] If there are two two-qubit gate nodes, and the two-qubit gates represented by these two two-qubit gate nodes satisfy the quantum gate exchange rule III, then the gate order of these two two-qubit gates can be exchanged.

[0206] If swapping the gate order of these two quantum gates results in new conditions for merging the quantum gates, then swap the nodes representing these two two-qubit gates in the DAG and proceed with step S43.

[0207] Repeat step S5 until there are no more quantum gate nodes in the entire DAG that meet the conditions for merging after exchanging; the quantum gate merging is complete.

[0208] refer to Figure 10 As shown in (a), in a three-qubit circuit, there are four consecutive two-qubit gates. The first and fourth gates are two-qubit gates G. d The gates, and the qubits involved are different; the second and third quantum gates are two-qubit gates CU. c Doors, of which the second door CU c Door and the fourth door G d The gates function with the same number of qubits, and the third gate CU c Door and the first door G d The gates have the same qubits, and the two CUs are identical. c The gates can be swapped; at this point, there are no quantum gates in the quantum circuit that can be directly merged, but if the second and third quantum gates CU are swapped... c The gate will create two opportunities for quantum gate merging, see reference. Figure 10 As shown in (b); the final quantum circuit will merge into two U... m Door, reference Figure 10 As shown in (c).

[0209] Step S6: Convert the DAG into a quantum circuit according to the order of the quantum gate nodes in the DAG, which is the preprocessed quantum circuit; because the DAG can determine the execution order of the quantum gates through topological sorting, ensuring that all dependencies are satisfied; convert the DAG into a preprocessed quantum circuit to complete the preprocessing of the quantum circuit.

[0210] Step S7: Convert the preprocessed quantum circuit into a preprocessed DAG; each node in the DAG is a quantum gate in the preprocessed quantum circuit, which contains information such as the type of the quantum gate, the qubits it operates on, and the corresponding matrix representation; the directed edges in the DAG are added according to the dependencies of all quantum gates in the quantum circuit to be decomposed; because the DAG can clearly represent the dependencies and execution order of quantum gates in the quantum circuit, the sequential relationship of quantum gate operations is more intuitive and clear; by converting the preprocessed quantum circuit into a DAG, the heuristic decomposition step of the preprocessed quantum circuit can be performed;

[0211] Step S8: Traverse the preprocessed DAG and create a decomposition task for each multi-qubit gate; because multi-qubit gates in a quantum circuit need to be decomposed into quantum gates contained in the quantum instruction set;

[0212] Step S8 specifically includes the following steps:

[0213] A decomposition task is created for each multi-qubit gate according to the topological order of the quantum gate nodes in the preprocessed DAG. The decomposition task is to decompose the multi-qubit gate to be decomposed into quantum circuits containing only the quantum gates contained in the quantum instruction set.

[0214] Step S9: Execute the quantum gate decomposition task in parallel; parallel execution allows the decomposition of multiple quantum gates to be processed simultaneously, rather than sequentially; this can significantly reduce the overall computation time.

[0215] Step S9 specifically includes the following steps:

[0216] For each decomposition task, the gate decomposition with different levels is verified iteratively. The Broyden–Fletcher–Goldfarb–Shanno algorithm (BFGS) is used to decompose each quantum gate with the fewest levels while satisfying the fidelity requirement of each quantum gate to be decomposed. The decomposition scheme with the lowest fidelity among all decomposition schemes at the decomposition level is recorded as the decomposition scheme of the quantum gate to be decomposed.

[0217] The BFGS decomposition method is used to decompose the quantum gate to be decomposed. The BFGS decomposition method uses the generated constraints and cost function to optimize through multiple attempts to obtain a smaller number of decomposition layers. By evaluating the fidelity and selecting the decomposition scheme with the best fidelity at the current number of decomposition layers, a decomposed quantum circuit is generated.

[0218] When all decomposition tasks have been completed, all multi-qubit gates in the quantum circuit have been decomposed into quantum circuits containing only the quantum gates included in the quantum instruction set.

[0219] Step S10: Create a storage DAG to store the decomposed quantum circuits; in order to store the decomposed quantum circuits, first store the decomposed quantum circuits in the DAG;

[0220] Step S10 specifically includes the following steps:

[0221] Add the quantum registers and classical registers from the preprocessed quantum circuit to the storage DAG;

[0222] For single-qubit gates in the preprocessed quantum circuit, they are added as nodes to the storage DAG;

[0223] For the two-qubit gate in the preprocessed quantum circuit, the quantum gates in the decomposed quantum circuit are added as nodes to the storage DAG.

[0224] Step S11: Merge the single-qubit gate nodes in the stored DAG; by merging the single-qubit gates that can be merged in the decomposed quantum circuit, the number of single-qubit gates in the decomposed quantum circuit can be reduced, so as to optimize the decomposed quantum circuit.

[0225] Step S11 specifically includes the following steps:

[0226] By traversing the quantum gate nodes in the DAG, if there are two or more single-qubit gate nodes representing consecutive single-qubit gates that act on the same qubit, then these single-qubit gates can be merged.

[0227] The result of merging is a parameterized single-qubit gate contained in a quantum instruction. The matrix representation of this synthesized parameterized single-qubit gate is the product of the matrix representations of the merged single-qubit gates multiplied in the order of action of the quantum gates.

[0228] In the storage DAG, the nodes representing these merged quantum gates are replaced with a new node, which is the node of the synthesized single-qubit gate;

[0229] Repeat step S11 until there are no single-qubit gate nodes in the stored DAG that can be directly merged.

[0230] Step S12: Convert the stored DAG into a quantum circuit according to the order of the quantum gate nodes in the stored DAG, which is the quantum circuit for heuristic decomposition. Convert the stored DAG into a preprocessed quantum circuit to complete the heuristic decomposition of the quantum circuit.

[0231] Example 2

[0232] Based on Example 1, after completing the above steps, the decomposition of the quantum circuit is completed, and the preprocessed quantum circuit will be decomposed into a quantum circuit containing only the quantum gates contained in the instruction set.

[0233] After designing an improved heuristic quantum circuit decomposition method for working with quantum instruction sets, it becomes possible to decompose quantum circuits.

[0234] The improved heuristic quantum circuit decomposition method, for Figure 11 The random two-qubit gate circuit (QV quantum circuit) in (a), if directly decomposed using the original heuristic method, would have the following instruction set: If there are gates and U3 gates, the decomposed circuit will contain 5... Door, like Figure 11 As shown in (b). However, if the QV line is preprocessed according to this invention, merging the two gates, a line containing only one 2Q gate can be obtained, as shown in [example]. Figure 11 As shown in (c). Then, if the quantum circuit is further decomposed, the decomposed circuit contains only 3... Door, like Figure 11 As shown in (d). By employing this method of the present invention, the depth of quantum circuits can be significantly reduced.

[0235] Example 3

[0236] Based on Example 1, if... Figure 12 The quantum circuit shown, containing six 2Q gates, undergoes the preprocessing of this invention, including the exchange cancellation and merging operations of the quantum gates, which simplifies the quantum circuit to two 2Q gates, as shown below. Figure 13 As shown, further decomposition of the quantum circuit significantly reduces its depth. In the decomposition... Figure 12 When decomposing quantum circuits, the gate count and fidelity of the decomposed quantum circuits were analyzed. This was compared with existing heuristic-based quantum circuit decomposition methods, assuming a fidelity of 1Q gates. The gate fidelity is 0.99, and the results are shown in Table 4.

[0237] Table 4 Decomposition Comparison

[0238]

[0239] First of all, the reduction in the number of quantum gates is directly related to preprocessing. For an n-qubit circuit, if there are g 2Q gates to be decomposed in the circuit, among which there are m redundant 2Q gates (m<g), generally one 2Q gate to be decomposed can be expressed by 2 to 3 2Q gates in the quantum instruction set. The number of 2Q gates in the quantum instruction set required by the heuristic quantum circuit decomposition method is 2g to 3g, while the improved heuristic quantum circuit decomposition method only requires 2(g-m) to 3(g-m) 2Q gates in the quantum instruction set. In terms of circuit fidelity, assuming that the fidelity of a 1Q gate is 1 and the fidelity of a 2Q gate is f(0<f<1), for the existing heuristic-based quantum circuit decomposition method, for the above circuit, the overall fidelity of the circuit is f 2g ~f 3g , while the fidelity of the improved decomposition method is f 2(g-m) ~f 3(g-m) . However, it should be noted that when there is an opportunity to eliminate redundant quantum gates in a quantum circuit, the present invention can improve the decomposition effect of the quantum circuit. The more redundant quantum gates there are in the quantum circuit, the better the decomposition effect of the present invention will be. Even if there is no redundant quantum gate in the quantum circuit, the present invention will not deteriorate the decomposition effect. Therefore, the present invention is superior to the existing heuristic-based quantum circuit decomposition methods.

[0240] Example 4

[0241] Based on Example 1, another example of a quantum circuit is given to prove the effectiveness of the above improved method. A randomly generated 3-qubit QV quantum circuit with a circuit depth of 10 is used, which contains 10 random two-qubit gates, as Figure 14 shown. For the above QV quantum circuit, a comparison of two decomposition methods is carried out. Nuop is a quantum circuit decomposition method based on the existing heuristic method, while the method in the present invention is an improved heuristic quantum circuit decomposition method with preprocessing added.

[0242] If the pre-improvement heuristic quantum circuit decomposition method Nuop is used for decomposition, where the instruction set includes gates and U3 gates, the decomposed circuit will have 21 gates, as Figure 15 shown. Before decomposing the quantum circuit, the improved heuristic quantum circuit decomposition method first preprocesses the quantum circuit. The preprocessing mainly performs prior optimization on the optimizable parts of the original quantum circuit, including gate cancellation and gate combination in the original quantum circuit, as well as gate cancellation and gate combination generated through exchange, Figure 14 the preprocessed quantum circuit of the quantum circuit shown in is shown in Figure 16 shown. After preprocessing, the heuristic quantum circuit decomposition method is performed, and the circuit will have 21 Door, like Figure 17 As shown.

[0243] The comparison results are shown in Table 5 (assuming the fidelity of the 1Q gate is 1). The door fidelity is 0.99.

[0244] Table 5 Decomposition Comparison

[0245]

[0246] This invention is applicable to any quantum circuit. Compared with Nuop, this invention not only considers the efficient decomposition of quantum gates, but also the optimization of the circuit itself. It can achieve efficient decomposition while reducing the amount of decomposition work, thereby reducing the number of quantum gates after decomposition and improving the overall circuit fidelity.

[0247] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A heuristic quantum circuit decomposition method based on quantum instruction sets, characterized in that, The method includes the following steps: Step S1: Convert the quantum circuit to be decomposed into a directed acyclic graph (DAG). Step S2: Define the set of quantum gates that can cancel each other out, and define the cancellation rules of the quantum gates to perform the cancellation steps of the quantum gates; Step S3: Define the set of quantum gates that can be exchanged, and define the exchange rules of the quantum gates to perform the quantum gate exchange cancellation step; Step S4: Define the set of quantum gates that can be merged, and define the merging rules of quantum gates to carry out the merging steps of quantum gates; Step S5: The quantum gate exchange and merging step; Step S6: Convert the DAG into a quantum circuit according to the order of the quantum gate nodes in the DAG, which is the preprocessed quantum circuit; Step S7: Convert the preprocessed quantum circuit into a preprocessed DAG; Step S8: Traverse the preprocessed DAG; Create a decomposition task for each multi-qubit gate; Step S9: Perform the quantum gate decomposition task in parallel; Step S10: Create a storage DAG to store the decomposed quantum circuits; Step S11: Merge the single-qubit gate nodes in the storage DAG; Step S12: Convert the stored DAG into a quantum circuit according to the order of the quantum gate nodes in the stored DAG, which is the quantum circuit that completes the heuristic decomposition.

2. The heuristic quantum circuit decomposition method based on quantum instruction sets according to claim 1, characterized in that, Step S2 specifically includes the following steps: S21: Define the set of quantum gates that can cancel each other out; The set containing only single-qubit gates X, Y, Z, and H is defined as U. c ; The set containing only two-qubit gates (CX, CY, CZ, and CH) is defined as CU. c ; The set containing only two-qubit SWAP gates is defined as G. sw ; S22: Define the cancellation rules for quantum gates; Definition of the cancellation rule for quantum gates I: If n adjacent two-qubit gates are identical and belong to CU c A set of n two-qubit gates, where the control bits and target bits of these n two-qubit gates are the same. If n is even, then these n two-qubit gates can cancel each other out. If n is odd, the first n-1 two-qubit gates can cancel each other out, leaving 1 two-qubit gate remaining. Definition of Quantum Gate Cancellation Rule II: If n adjacent two-qubit gates are identical and belong to G... sw A set of n two-qubit gates, where the two qubits acting on these n two-qubit gates are the same. If n is even, then these n two-qubit gates can cancel each other out. If n is odd, the first n-1 two-qubit gates can cancel each other out, leaving 1 two-qubit gate remaining. Where n≥2; S23: Cancellation step of quantum gate; Traverse the quantum gate nodes in the DAG. If there are n consecutive two-qubit gate nodes, these two-qubit gate nodes are directly connected by edges in the DAG, and the two-qubit gates represented by these nodes satisfy quantum gate cancellation rule I or quantum gate cancellation rule II. If n is even, these two-qubit gates can cancel each other out; If n is odd, the first n-1 quantum gates in these two-qubit gates can cancel each other out; In a DAG, the predecessor node of the first canceled two-qubit gate node in the topological order directly points to the successor node of the last canceled two-qubit gate node in the topological order. Deleting the node representing these canceled two-qubit gates completes the cancellation operation of these two-qubit gate nodes in the DAG. Repeat step S23 until there are no two-qubit gate nodes in the DAG that can be directly canceled; the cancellation operation of the quantum gates is complete. Where: n≥2.

3. The heuristic quantum circuit decomposition method based on quantum instruction sets according to claim 2, characterized in that, Step S3 specifically includes the following steps: S31: Define the set of quantum gates that can be exchanged; This will include only single-qubit gates: P(λ) gate, RZ(λ) gate, S gate, and S... + Door, T-door, T + The set of gates, Z gates, is defined as G. c ; Will only include single-qubit gates SX gate, SX + The set of gates, X gates, and RX(θ) gates is defined as G. x ; The set containing only single-qubit gates Y and RY(θ) is defined as G. y ; This will include only single-qubit gates: P(λ) gate, RZ(λ) gate, S gate, and S... + Door, T-door, T + The set of gates, U1(λ) gates, and Z gates is defined as G. z ; The set containing only single-qubit gates (H gates) is defined as G. h ; U in step S21 c and CU c They are all sets of quantum gates that can be exchanged; S32: Define the commutation rules for quantum gates; Definition of the commutation rule for quantum gates I: If a two-qubit gate belongs to CU c A gate set, where the single-qubit gate adjacent to this two-qubit gate is located on the control bit of this two-qubit gate, and this single-qubit gate belongs to G. c If the two-qubit gate and the single-qubit gate satisfy the above conditions, then their positions can be interchanged; if the two-qubit gate and the single-qubit gate do not satisfy the above conditions, then their positions cannot be interchanged. Quantum gate commutation rule II: If a two-qubit gate is a CX gate, the adjacent single-qubit gate is located on the target qubit of the two-qubit gate, and this single-qubit gate belongs to the G category. x If the two quantum gates are a set of gates, then the positions of the two quantum gates can be interchanged; if the two quantum gates and the one quantum gate do not satisfy the above conditions, then the positions of the two quantum gates cannot be interchanged. Quantum gate commutation rule III: If two identical two-qubit gates are adjacent and belong to the CU... c If two two-qubit gates are in a set such that the control bit of one of them is different from the target bit of the other, then the positions of the two two-qubit gates can be swapped; if the two two-qubit gates do not satisfy the above condition, then the positions of the two gates cannot be swapped. S33: The steps of cancellation after exchange in a quantum gate; Traverse the quantum gate nodes in the DAG. At this point, there are no more two-qubit gate nodes that can directly cancel each other out. However, if there are two quantum gate nodes that represent quantum gates that satisfy quantum gate swapping rule I, quantum gate swapping rule II, or quantum gate swapping rule III, then the gate order of these two quantum gates can be swapped. If swapping the gate order of these two quantum gates generates new conditions that satisfy quantum gate cancellation, then swap the nodes representing these two quantum gates in the DAG and perform step S23. Repeat step S33 until there are no more quantum gate nodes in the DAG that can cancel each other out after swapping. At this point, the quantum gate swapping cancellation operation is complete.

4. The heuristic quantum circuit decomposition method based on quantum instruction sets according to claim 1, characterized in that, Step S4 specifically includes the following steps: S41: Define the set of quantum gates that can be merged; The set containing all single-qubit gate SU(2) gates is defined as G. s ; The set containing all two-qubit gate SU(4) gates is defined as G. d ; The two-qubit gate resulting from the merging of quantum circuits will be defined as U. m ; S42: Define the merging rules for quantum gates; The merging rule for quantum gates is defined as follows: In a quantum circuit, if multiple consecutive two-qubit gates operate on only two qubits, and these two-qubit gates are surrounded only by single-qubit gates, with no multi-qubit gates operating on other qubits, then these quantum gates can be merged into an equivalent two-qubit gate, denoted as U. m ; If no quantum gates satisfy the above conditions, then these quantum gates cannot be merged; S43: The merging steps of quantum gates; Traversing the quantum gate nodes in the DAG, there are no longer any quantum gate nodes that can be canceled or swapped to cancel each other out. However, if there are two or more quantum gate nodes, and the quantum gates represented by these nodes satisfy the merging rules defined for quantum gates, then these two-qubit gates and one-qubit gates can be merged. The result of the merger is denoted as U. m ; U m It is a two-qubit gate, U m The matrix representation is the product of the matrix representation of the tensor product of the merged single-qubit gate and the single-qubit gate I gate and the matrix representation of the merged two-qubit gate multiplied in the order of action of the quantum gates; In a DAG, the nodes representing these merged quantum gates are replaced with a new node, which is the synthesized two-qubit gate U. m Nodes; Repeat step S43 until there are no more quantum gate nodes in the DAG that can be directly merged.

5. The heuristic quantum circuit decomposition method based on quantum instruction sets according to claim 3, characterized in that, Step S5 specifically includes the following steps: If there are two two-qubit gate nodes, and the two-qubit gates represented by these two two-qubit gate nodes satisfy the quantum gate exchange rule III, then the gate order of these two two-qubit gates can be exchanged. If swapping the gate order of these two quantum gates results in new conditions for merging the quantum gates, then swap the nodes representing these two two-qubit gates in the DAG and proceed with step S43. Repeat step S5 until there are no more quantum gate nodes in the entire DAG that meet the conditions for merging after exchanging; the quantum gate merging is complete.

6. The heuristic quantum circuit decomposition method based on quantum instruction sets according to claim 1, characterized in that, Step S8 specifically includes the following steps: A decomposition task is created for each multi-qubit gate according to the topological order of the quantum gate nodes in the preprocessed DAG. The decomposition task is to decompose the multi-qubit gate to be decomposed into quantum circuits containing only the quantum gates contained in the quantum instruction set.

7. The heuristic quantum circuit decomposition method based on quantum instruction sets according to claim 1, characterized in that, Step S9 specifically includes the following steps: For each decomposition task, the gate decomposition with different levels is verified iteratively. The Broyden–Fletcher–Goldfarb–Shanno algorithm (BFGS) is used to decompose each quantum gate with the fewest levels while satisfying the fidelity requirement of each quantum gate to be decomposed. The decomposition scheme with the lowest fidelity among all decomposition schemes at the decomposition level is recorded as the decomposition scheme of the quantum gate to be decomposed.

8. The heuristic quantum circuit decomposition method based on quantum instruction sets according to claim 1, characterized in that, Step S10 specifically includes the following steps: Add the quantum registers and classical registers from the preprocessed quantum circuit to the storage DAG; For single-qubit gates in the preprocessed quantum circuit, they are added as nodes to the storage DAG; For the two-qubit gate in the preprocessed quantum circuit, the quantum gates in the decomposed quantum circuit are added as nodes to the storage DAG.

9. The heuristic quantum circuit decomposition method based on quantum instruction sets according to claim 1, characterized in that, Step S11 specifically includes the following steps: By traversing the quantum gate nodes in the DAG, if there are two or more single-qubit gate nodes representing consecutive single-qubit gates that act on the same qubit, then these single-qubit gates can be merged. The result of merging is a parameterized single-qubit gate contained in a quantum instruction. The matrix representation of this synthesized parameterized single-qubit gate is the product of the matrix representations of the merged single-qubit gates multiplied in the order of action of the quantum gates. In the storage DAG, the nodes representing these merged quantum gates are replaced with a new node, which is the node of the synthesized parameterized single-qubit gate. Repeat step S11 until there are no single-qubit gate nodes in the stored DAG that can be directly merged.

10. The heuristic quantum circuit decomposition method based on quantum instruction sets according to claim 3, characterized in that, In step S32, the two-qubit gate can be a CX gate, or it can also be a CY gate, a CZ gate, or a CH gate; Single-qubit gates belong to G x In addition to the gate collection, it can also provide G y Gate set or G z Gate set or G h Gate collection.

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