A semiconductor device and a manufacturing method thereof
By designing alternating bitline structures and adding connection pads and isolation structures in semiconductor devices, the problems of top adhesion and leakage caused by miniaturization of bitline structures are solved, thereby improving the reliability and performance of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2024-08-23
- Publication Date
- 2026-06-16
Smart Images
Figure CN118829212B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology
[0002] With the trend towards miniaturization in various electronic products, the design of semiconductor devices must also meet the requirements of high aggregation and high density. For dynamic random access memory (DRAM) with a recessed gate structure, it can achieve a longer carrier channel length within the same semiconductor substrate, reducing leakage current caused by capacitor structures. Therefore, under the current mainstream development trend, it has gradually replaced DRAM with only planar gate structures. Generally, DRAM with a recessed gate structure consists of a large number of memory cells clustered into an array region to store information. Each memory cell can be composed of transistor components and capacitor components connected in series to receive voltage information from word lines (WL) and bit lines (BL). Due to product demands, the density of memory cells in the array region must continue to increase, leading to a growing risk of adhesion between the tops of adjacent bit line structures. Therefore, existing technologies or structures need further improvement to effectively enhance the performance and reliability of related memory devices. Summary of the Invention
[0003] The purpose of this invention is to provide a semiconductor device and its manufacturing method, so as to effectively avoid the problems of top adhesion and leakage caused by the miniaturization of semiconductor device size in the prior art midline structure, thereby improving the reliability and performance of the semiconductor device.
[0004] In a first aspect, to achieve the above objectives, the present invention provides a semiconductor device, which may include at least:
[0005] Base;
[0006] Multiple bit line structures are disposed on the substrate, including a conductive layer and an insulating capping layer stacked sequentially from bottom to top. The bit line structure includes a first bit line structure and a second bit line structure that are separated from each other in the horizontal direction and arranged alternately, and the top surface of the first bit line structure is higher than the top surface of the second bit line structure.
[0007] Multiple connecting pad structures are disposed between adjacent bit line structures and extend horizontally to cover a portion of the top surface of the bit line structures;
[0008] Multiple isolation structures are disposed between adjacent connection pad structures, including a first isolation structure located above the first bit line structure and a second isolation structure located above the second bit line structure.
[0009] In some optional examples, the top surfaces of the conductive layers of the first bit line structure and the conductive layers of the second bit line structure are at the same horizontal height.
[0010] In some alternative examples, the first isolation structure directly contacts the first bit line structure, and the second isolation structure is isolated from the second bit line structure.
[0011] In some alternative examples, the first isolation structure directly contacts the first bit line structure, and the second isolation structure directly contacts the second bit line structure.
[0012] In some alternative examples, the first isolation structure and the second isolation structure extend to different depths of the first bit line structure and the second bit line structure.
[0013] In some alternative examples, the bottom surface of the first isolation structure is lower than the bottom surface of the second isolation structure.
[0014] In some optional examples, the distance between the top surface of the first bit line structure and the top surface of the connecting pad structure may be less than the distance between the top surface of the second bit line structure and the top surface of the connecting pad structure.
[0015] In some optional examples, the semiconductor device of the present invention may further include:
[0016] A dielectric layer is disposed on the substrate and covers the top surface of the second bit line structure.
[0017] In some alternative examples, the dielectric layer and the top surface of the first bit line structure may be located at the same horizontal height.
[0018] In some optional examples, the semiconductor device of the present invention may further include:
[0019] Multiple contact structures are disposed under the connecting pad structure and electrically connected to the substrate.
[0020] Secondly, based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, which may include at least the following steps:
[0021] Provide a base;
[0022] Multiple mutually separated bit line structures are formed. The bit line structure is located on the substrate and includes a conductive layer and an insulating cap layer stacked sequentially from bottom to top. The bit line structure includes a first bit line structure and a second bit line structure that are mutually separated and alternately arranged in the horizontal direction, and the top surface of the first bit line structure is higher than the top surface of the second bit line structure.
[0023] Multiple connecting pad structures are formed, the connecting pad structures being located between adjacent bit line structures and extending horizontally to cover a portion of the top surface of the bit line structures;
[0024] Multiple isolation structures are formed, the isolation structures being located between adjacent connection pad structures and including a first isolation structure located above the first bit line structure and a second isolation structure located above the second bit line structure.
[0025] In some optional examples, the steps of forming the first bit line structure and the second bit line structure may include:
[0026] Multiple first-line structures are formed, and the multiple first-line structures are arranged on the substrate with horizontal separation between them;
[0027] An insulating material layer and a photoresist layer are formed sequentially, wherein the insulating material layer is located between adjacent first bit line structures, and the photoresist layer is located on the insulating material layer;
[0028] Using the photoresist layer as a mask, a portion of the height of the first bit line structure is removed to obtain a second bit line structure that alternates with the remaining first bit line structure in the horizontal direction.
[0029] In some optional examples, the top surfaces of the conductive layers of the first bit line structure and the conductive layers of the second bit line structure are at the same horizontal height.
[0030] In some alternative examples, the first isolation structure directly contacts the first bit line structure, and the second isolation structure is isolated from the second bit line structure.
[0031] In some alternative examples, the first isolation structure directly contacts the first bit line structure, and the second isolation structure directly contacts the second bit line structure.
[0032] In this invention, by setting multiple bit line structures in a semiconductor device to be arranged alternately in the horizontal direction as a first bit line structure and a second bit line structure with their top surfaces at different horizontal heights, the problems of top adhesion and leakage of adjacent bit line structures caused by the miniaturization of semiconductor device size, which are present in the prior art, are avoided. This aims to improve the reliability and performance of the semiconductor device. Attached Figure Description
[0033] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:
[0034] Figures 1 to 8 This is a schematic diagram of the structure of the semiconductor device manufacturing method provided in one embodiment of the present invention during the preparation process.
[0035] The attached figures are labeled as follows:
[0036] 100 - Substrate; 101 - Shallow trench isolation; 110 - Isolation layer; 120 - Bit line material layer; 121 - Semiconductor layer; 122 - Barrier layer; 123 - Conductive layer; 124 - Insulating cap layer; BL - Bit line structure; BL1 - First bit line structure; BL2 - Second bit line structure; 130 - Sidewall structure; 131 - First sidewall; 132 - Second sidewall; 140 - Insulating material layer; 150 - Photoresist layer; 160 - Dielectric layer; SNC - Contact structure. 170 - Silicate layer, 180 - Connector pad structure, 181 - First connector pad layer, 182 - Second connector pad layer, 190 - Isolation structure, 191 - First isolation structure, 192 - Second isolation structure, X - Horizontal direction, Y - Vertical direction, D1~D3 - Extension depth of the isolation structure on the bit line structure, H1 - Distance between the top surface of the first bit line structure and the top surface of the connector pad structure, H2 - Distance between the top surface of the second bit line structure and the top surface of the connector pad structure.
[0037] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation
[0038] The semiconductor device and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may be practiced in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.
[0039] For ease of understanding, the following text defines horizontal and vertical directions, where the horizontal direction is parallel to the surface of the substrate 100; and the vertical direction is perpendicular to the surface of the substrate 100. Figures 1 to 8The X and Y directions are defined, with the X direction corresponding to the horizontal direction and the Y direction corresponding to the vertical direction. Furthermore, the X and Y directions, as well as the horizontal and vertical directions, are all perpendicular to each other.
[0040] Please refer to Figure 7 As shown, Figure 7 This is a cross-sectional schematic diagram of the semiconductor device in the first embodiment of the present invention. Figure 7 As shown, the semiconductor device may include a substrate 100, multiple bit line structures BL, a dielectric layer 160, a connection pad structure 180, and an isolation structure 190. The substrate 100 can be any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto. Multiple shallow trench isolations (STIs) 101 are also provided within the substrate 100 to define multiple active areas (AA, not shown). Specifically, the shallow trench isolation 101 may include a single layer or multiple layers of dielectric material. Suitable dielectric materials may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or combinations of the above materials, but are not limited thereto. For example, the shallow trench isolation 101 in this embodiment may be elongated with its long axis extending along the Y direction. Furthermore, an isolation layer 110 is also provided on the substrate 100. Specifically, the isolation layer 110 may be a single-layer structure, such as a silicon oxide layer or a silicon nitride layer, or a composite layer, such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, but is not limited thereto.
[0041] In this embodiment, the bit line structure BL may include multiple first bit line structures BL1 and multiple second bit line structures BL2 with their top surfaces located at different horizontal heights. That is, the top surfaces of the multiple first bit line structures BL1 or the multiple second bit line structures BL2 are all coplanar, but the top surfaces of the multiple first bit line structures BL1 and the multiple second bit line structures BL2 are not coplanar. In other words, the multiple first bit line structures BL1 and the multiple second bit line structures BL2 have a height difference along the vertical direction (hereinafter referred to as the Y direction). This avoids the problems of top adhesion and leakage of adjacent bit line structures caused by the miniaturization of semiconductor device dimensions in the prior art (i.e., the top surfaces of all bit line structures are coplanar), thereby improving the reliability and performance of semiconductor devices.
[0042] Specifically, multiple first bit line structures BL1 and multiple second bit line structures BL2 are alternately and separated from each other along a horizontal direction (hereinafter referred to as the X direction) on the substrate 100. The first bit line structure BL1 and the second bit line structure BL2 have multiple bit line material layers, such as a bit line material layer 120 composed of a semiconductor layer 121, a barrier layer 122, a conductive layer 123, and an insulating capping layer 124 stacked sequentially from bottom to top. The semiconductor layer 121 may be made of crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon-germanium (SiGe), or other suitable semiconductor materials, but is not limited thereto. The barrier layer 122 may be made of metal, metal silicide, or metal nitride, such as titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), tungsten nitride (WN), but is not limited thereto. The conductive layer 123 may be made of tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metals, but is not limited thereto. The insulating capping layer 124 may be made of dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or combinations thereof, but is not limited thereto. For example, the semiconductor layer 121 is made of polycrystalline silicon, the barrier layer 122 is made of cobalt silicide (CoSi), the conductive layer 123 is made of tungsten (W), and the insulating capping layer 124 is made of silicon nitride (SiN).
[0043] In this embodiment, the top surface of the first bit line structure BL1 is higher than the top surface of the second bit line structure BL2. Specifically, the top surface of the insulating capping layer 124 in the first bit line structure BL1 is higher than the top surface of the insulating capping layer 124 in the second bit line structure BL2. However, the conductive layer 123, the barrier layer 122, and the semiconductor layer 121 in the first bit line structure BL1 are all at the same horizontal height as the top surfaces of the conductive layer 123, the barrier layer 122, and the semiconductor layer 121 in the second bit line structure BL2, respectively. Furthermore, the sidewall structures 130 located on both sides of the first bit line structure BL1 and the second bit line structure BL2 in this embodiment may also be provided. The sidewall structures 130 may also have a multilayer structure, for example... Figure 7 The first sidewall 131 and the second sidewall 132 are stacked sequentially along the X direction, and the first sidewall 131 is in direct contact with the sidewall of the first bit line structure BL1 or the second bit line structure BL2. Specifically, the first sidewall 131 and the second sidewall 132 may each include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but are not limited thereto. For example, the material of the first sidewall 131 is silicon oxide (SiO2), and the material of the second sidewall 132 is silicon nitride (SiN). It should be noted that since the bit line structure BL in this embodiment includes the first bit line structure BL1 and the second bit line structure BL2 with different heights along the Y direction, the height of the sidewall structure 130 located on the sidewall of the first bit line structure BL1 and the second bit line structure BL2 may also include the first sidewall structure and the second sidewall structure with different heights along the Y direction. For the sake of simplified drawing, the first sidewall structure and the second sidewall structure are labeled with the same reference numerals in this embodiment.
[0044] Continue to refer to Figure 7 As shown, in this embodiment, the dielectric layer 160 is specifically disposed on the substrate 100, and the dielectric layer 160 at least covers the top surface of the second bitline structure BL2, which has a lower top surface in the bitline structure BL. Specifically, the top surface of the dielectric layer 160 may be flush with the top surface of the second bitline structure BL2 in the bitline structure BL, or the top surface of the dielectric layer 160 may be flush with the top surface of the first bitline structure BL1 in the bitline structure BL, or the top surface of the dielectric layer 160 may be located between the top surface of the first bitline structure BL1 and the top surface of the second bitline structure BL2 in the bitline structure BL, but this is not a limitation. For example, in this embodiment, the top surface of the dielectric layer 160 is set to be flush with the top surface of the first bitline structure BL1 in the bitline structure BL, thereby covering the top surface of the second bitline structure BL2. The material of the dielectric layer 160 may include silicon oxide, polysilazane, or other suitable materials, but this is not a limitation.
[0045] Furthermore, the connection pad structure 180 in this embodiment is specifically disposed between adjacent bit line structures BL and extends along the X direction to cover a part of the top surface of the bit line structure BL. The isolation structure 190 including the first isolation structure 191 and the second isolation structure 192 that are separated from each other and alternately arranged along the X direction is specifically disposed between adjacent connection pad structures 180. Specifically, the connection pad structure 180 may include a first connection pad layer 181 and a second connection pad layer 182 that are stacked in sequence along the Y direction. Since there is a dielectric layer 160 with a top surface flush with the top surface of the first bit line structure BL1 between adjacent bit line structures BL in this embodiment, the first connection pad layer 181 in the connection pad structure 180 directly covers the top surface of the dielectric layer 160 and is in direct contact with the first bit line structure BL1. The top surfaces of the first isolation structure 191 and the second isolation structure 192 in the isolation structure 190 are flush with each other and are at the same horizontal height (i.e., coplanar) as the top surface of the second connection pad 182 in the connection pad structure 180. All the first isolation structures 191 pass through the connection pad structure 180, the dielectric layer 160 and are in direct contact with the first bit line structure BL1. A part of the second isolation structures 192 in the isolation structure 190 pass through the connection pad structure 180, the dielectric layer 160 and are in direct contact with the second bit line structure BL2, and the other part of the second isolation structures 192 pass through the connection pad structure 180, the dielectric layer 160 and are isolated from the second bit line structure BL2 through the dielectric layer 160.
[0046] In this embodiment, the first isolation structure 191 and the second isolation structure 192 in the isolation structure 190 may extend along the Y direction to different depths of the first bit line structure BL1 and the second bit line structure BL2, that is, the bottom surfaces of some of the first isolation structures 191 and some of the second isolation structures 192 are not coplanar. For example, the bottom surface of the first isolation structure 191 may be lower than the bottom surface of the second isolation structure 192. That is, the distances between the top and bottom surfaces (in the Y direction) of the multiple first isolation structures 191 in the isolation structure 190 may be different, the distances between the top and bottom surfaces of the multiple second isolation structures 192 may be different, and the distances between the top and bottom surfaces of the multiple first isolation structures 191 and the distances between the top and bottom surfaces of the multiple second isolation structures 192 may also be different. Exemplarily, as Figure 7 shown, if the extension depth of the isolation structure 190 on the bit line structure BL is D, that is, the extension depth of one of the first isolation structures 191 on the first bit line structure BL1 is D2, and the extension depths of the two second isolation structures 192 on the second bit line structure BL2 are D1 and D3 respectively, then D1 < D2 < D3, but this is not a limitation.
[0047] In this embodiment, the material of the first connecting pad 181 may include titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN) and other conductive barrier materials, but is not limited thereto. The material of the second connecting pad 182 may include metals, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys, and / or composite layers of the aforementioned materials, but is not limited thereto. The material of the isolation structure 190 may include nitrides, such as silicon nitride, or oxides, such as silicon oxide, but is not limited thereto. For example, the material of the first connecting pad 181 is titanium nitride (TiN), the material of the second connecting pad 182 is tungsten (W), and the material of the isolation structure 190 (including the first isolation structure 191 and the second isolation structure 192) is silicon nitride.
[0048] It is understandable that, viewed from the Y-direction perspective of the distance between the connecting pad structure 180 and the bit line structure BL, the distance between the top surface of the first bit line structure BL1 and the top surface of the connecting pad structure 180 (i.e., the top surface of the second connecting pad 182) in this embodiment is smaller than the distance between the top surface of the second bit line structure BL2 and the top surface of the connecting pad structure 180 (i.e., the top surface of the second connecting pad 182), but this is not a limitation. With this configuration, the first bit line structure BL1 and the second bit line structure BL2, with their top surfaces at different horizontal heights, achieve the goal of avoiding the problems of top adhesion and leakage of adjacent bit line structures caused by the miniaturization of semiconductor devices in the prior art, thereby improving the reliability and performance of semiconductor devices.
[0049] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device of this invention may have other forms and is not limited to those described above. Further descriptions will follow regarding other embodiments or variations of the semiconductor device of this invention. For simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.
[0050] Please refer to Figure 8 As shown, Figure 8This is a cross-sectional schematic diagram of a semiconductor device in the second embodiment of the present invention. The structure of the semiconductor device in this embodiment is largely the same as that of the semiconductor device in the first embodiment described above. For example, the semiconductor device also includes multiple bit line structures BL, and the bit line structures BL include multiple first bit line structures BL1 and multiple second bit line structures BL2 that are spaced apart from each other along the X direction and alternately disposed on the substrate 100 and whose top surfaces are not coplanar. The similarities will not be repeated here. The main difference between the semiconductor device in this embodiment and the first embodiment described above is that the semiconductor device does not have a dielectric layer 160, but includes multiple contact structures SNC disposed under the connection pad structure 180 and a silicide layer 170 located between the connection pad structure 180 and the contact structures SNC. The contact structures SNC extend vertically along the Y direction within the substrate 100 between adjacent bit line structures BL to be electrically connected to the substrate 100. Since this embodiment has contact structures SNC and does not have a dielectric layer 160, the cross-sectional shape of the connection pad structure 180 in this embodiment is also different from the cross-sectional shape of the connection pad structure 180 in the first embodiment described above.
[0051] Specifically, such as Figure 8As shown, in this embodiment, a contact structure SNC is formed respectively within the interval between adjacent first bit line structures BL1 and second bit line structures BL2. Its two sides are separated from the bit line structures 120 by sidewall structures 130 and do not directly contact, while the bottom directly contacts the end of the active region (substrate 100). Among them, the material of the contact structure SNC may include crystalline silicon, poly silicon, amorphous silicon, doped silicon, SiGe, or other suitable silicon-containing semiconductor materials, but is not limited thereto. Exemplarily, the material of the contact structure SNC is phosphorous-doped silicon (SiP). A silicide layer 170 is located above the contact structure SNC, and a connection pad structure 180 conformally covers the top surface of the contact structure SNC, the top surface of the sidewall structure 130, and the top surface of the bit line structures BL (including the first bit line structure BL1 and the second bit line structure BL2). Moreover, the connection pad structure 180 in this embodiment also includes a first connection pad 181 and a second connection pad 182 stacked in sequence from bottom to top. Therefore, the conformal coverage of the connection pad structure 180 specifically means that its first connection pad 181 wraps around the outer surfaces of the first bit line structure BL1 and the second bit line structure BL2, and its second connection pad 182 covers the first connection pad 181 and fills the gap between the adjacent first bit line structure BL1 and the second bit line structure BL2, and its top surface is higher than the top surface of the first bit line structure BL1. Exemplarily, when observing the relationship between the top surface of the connection pad structure 180 and the top surface of the bit line structure BL, if the distance between the top surface of the connection pad structure 180 and the top surface of the first bit line structure BL1 is H1, and the distance between the top surface of the connection pad structure 180 and the top surface of the second bit line structure BL2 is H2, then the distance H1 < H2, but is not limited thereto.
[0052] It should be particularly noted that the isolation structure 190 in this embodiment is still divided into a first isolation structure 191 and a second isolation structure 192, but at this time the first isolation structure 191 directly contacts the first bit line structure BL1, and the second isolation structure 192 also directly contacts the second bit line structure BL2. Of course, the first isolation structure 191 and the second isolation structure 192 in the isolation structure 190 in this embodiment can still extend along the Y direction to different depths of the first bit line structure BL1 and the second bit line structure BL2 in the bit line structure BL. Exemplarily, as Figure 8 shown, if the extension depth of the isolation structure 190 on the bit line structure BL is D, that is, the extension depth of one of the first isolation structures 191 on the first bit line structure BL1 is D2, and the extension depths of the two second isolation structures 192 on the second bit line structure BL2 are D1 and D3 respectively, then D2 < D1 < D3, but is not limited thereto.
[0053] Under this configuration, the first bit line structure BL1 and the second bit line structure BL2 with their top surfaces at different horizontal heights in this embodiment can also achieve the purpose of avoiding the problems of top adhesion and leakage of adjacent bit line structures caused by the miniaturization of semiconductor device size in the prior art when the top surfaces of bit line structures with the same horizontal height are located at the same horizontal height, thereby improving the reliability and performance of semiconductor devices.
[0054] It should be understood that "common" in the embodiments of the present invention refers to the construction of a continuous structural shape by utilizing the morphological similarity and correlation between two or more shapes.
[0055] In order to enable those skilled in the art to easily understand the manufacturing method of the semiconductor device in the embodiments of the present invention, the manufacturing method of the semiconductor device proposed in the present invention will be further described below with reference to the various structural schematic diagrams in the preparation process of the manufacturing method.
[0056] Please refer to Figures 1 to 8 As shown, Figures 1 to 8 This is a schematic diagram of the structure of the semiconductor device manufacturing method provided in the embodiments of the present invention during the preparation process.
[0057] like Figure 1As shown, a substrate 100 is first provided, and multiple shallow trenches are formed within the substrate 100 using an etching process. Then, an insulating material (such as silicon oxide, silicon nitride, etc.) is filled into the multiple shallow trenches using a deposition process, such as at least one of physical vapor deposition, chemical vapor deposition, or atomic layer deposition, to form multiple shallow trench isolations 101. These multiple shallow trench isolations 101 define multiple active regions within the substrate 100. Next, an isolation layer 110 (such as a silicon oxide layer or a silicon nitride layer) and a bit line material layer 120 located on the isolation layer 110 are formed on the substrate 100. Specifically, forming the bit line material layer 120 may include forming a semiconductor layer 121, a barrier layer 122, a conductive layer 123, and an insulating capping layer 124 sequentially from bottom to top on the substrate 100. For example, the semiconductor layer 121 is made of polysilicon, the barrier layer 122 is made of cobalt silicide (CoSi), the conductive layer 123 is made of tungsten (W), and the insulating capping layer 124 is made of silicon nitride (SiN). Subsequently, the multilayer structure of the bit line material layer 120 is sequentially etched along the Y direction using an etching process, thereby forming multiple mutually separated bit line structures BL therein. At this time, the top surfaces of the multiple bit line structures BL are all located on the same horizontal line (i.e., coplanar), and the height of the multiple bit line structures BL along the Y direction is consistent with the height of the first bit line structure BL1 along the Y direction, but not limited thereto. Then, sidewall structures 130, self-aligned to the sidewalls of the bit line structure 120, are formed on both sides of the bit line structure 120. Since the multiple bit line structures BL have the same height along the Y direction, the sidewall structures 130 formed in this step also have the same height along the Y direction. The sidewall structure 130 has a multilayer structure, for example, a first sidewall 131 (such as silicon oxide) and a second sidewall 132 (such as silicon nitride) are stacked sequentially along the X direction.
[0058] like Figure 2 As shown, an insulating material layer 140 (such as silicon oxide, silicon nitride, etc.) is then filled between adjacent bit line structures BL using at least one of the above deposition processes, or further subjected to a chemical mechanical polishing (CMP) process to make the top surface of the insulating material layer 140 flush with the top surface of the bit line structure BL. A photoresist layer 150 is then formed on the top surfaces of the insulating material layer 140 and the bit line structure BL. The photoresist layer 150 has an opening pattern, which is used to form a second bit line structure BL2 with a lower top surface among the multiple bit line structures BL.
[0059] like Figure 3 and Figure 4As shown, an etching process, such as at least one of dry etching or wet etching, is then used, with the photoresist layer 150 as a mask, to remove a portion of the height of the bit line structure BL below the opening pattern and a portion of the insulating material layer 140 on both sides. This forms multiple bit line structures BL with flush top surfaces into multiple first bit line structures BL1 and multiple second bit line structures BL2 with their top surfaces at different horizontal heights. Specifically, the multiple first bit line structures BL1 and multiple second bit line structures BL2 can be separated from each other and arranged alternately along the X direction. Then, the insulating material layer 140 and the photoresist layer 150 are further removed.
[0060] After that, if it is to form Figure 7 The semiconductor device shown, comprising multiple bit line structures BL, a dielectric layer 160, a connection pad structure 180, and an isolation structure 190, can be further referred to Figure 5 To form Figure 8 The aforementioned structure, comprising multiple bit line structures BL, multiple contact structures SNC, a silicide layer 170, a connecting pad structure 180, and an isolation structure 190, can be further referred to... Figure 6 The following description will follow the order of forming the semiconductor device in the first embodiment first, and then forming the semiconductor device in the second embodiment.
[0061] like Figure 5 As shown, a dielectric layer 160 (such as silicon oxide) can then be formed in the gap between adjacent first bit line structures BL1 and second bit line structures BL2 using a deposition process. The top surface of the dielectric layer 160 is configured to be flush with the top surface of the first bit line structure BL1 in the bit line structure BL, thereby covering the top surfaces of both the first bit line structure BL1 and the second bit line structure BL2. It should be understood that, in this embodiment of the invention, the top surface of the dielectric layer 160 may be flush with the top surface of the second bit line structure BL2 in the bit line structure BL, or the top surface of the dielectric layer 160 may be flush with the top surface of the first bit line structure BL1 in the bit line structure BL, or the top surface of the dielectric layer 160 may be located between the top surfaces of the first bit line structure BL1 and the second bit line structure BL2 in the bit line structure BL, but this is not a limitation. Figure 5 The diagram shown is merely an example of the positional relationship between the top surface of the dielectric layer 160 and the top surface of the first bit line structure BL1 in the bit line structure BL in an embodiment of the present invention.
[0062] like Figure 7As shown, after the dielectric layer 160 is formed, a first connecting pad layer 181 (e.g., titanium nitride) and a second connecting pad layer 182 (e.g., tungsten metal) can be further formed using the deposition process described above, at least along the Y direction, to form a connecting pad structure 180. Specifically, the first connecting pad layer 181 of the connecting pad structure 180 is located on the dielectric layer 160 and the bit line structure BL, so the first connecting pad layer 181 is in direct contact with the first bit line structure BL1 that is exposed through the dielectric layer 160. The second connecting pad layer 182 is located on the first connecting pad layer 181, and its bottom surface is higher than the top surface of the plurality of first bit line structures BL1. Next, a mask layer (not shown) is formed on the connector pad structure 180. This mask layer contains an isolation structure pattern. Using this mask layer as a mask, grooves (i.e., the area corresponding to the isolation structure 190) are formed along the Y direction on the mask layer, connector pad structure 180, and part of the bit line structure BL on one side of the bit line structure BL using an etching process, such as dry etching or wet etching, to expose part of the sidewall structure 130. At this time, multiple grooves divide the mask layer and connector pad structure 180 along the X direction. Then, an isolation material layer (such as silicon oxide or silicon nitride) is formed on the substrate 100, and the isolation material layer at least fills the multiple grooves to form the isolation structure 190 between adjacent connector pad structures 180. The isolation structure 190 includes a first isolation structure 191 and a second isolation structure 192 that are separated from each other and alternately arranged along the X direction. The bottom surface of the first isolation structure 191 extends to the first bit line structure BL1 to directly contact the corresponding first bit line structure BL1. A portion of the bottom surface of the second isolation structure 192 extends to the second bit line structure BL2 and directly contacts the corresponding second bit line structure BL1, while the top surface of the remaining portion is isolated from the second bit line structure BL2. That is, a dielectric layer 160 is provided between the bottom surface of a portion of the second isolation structure 192 and the top surface of the second bit line structure BL2, thus forming the semiconductor device in the aforementioned first embodiment.
[0063] It should be understood that, in order to form the semiconductor device in the aforementioned second embodiment, then in such a way... Figure 4 After forming multiple first bit line structures BL1 and multiple second bit line structures BL2 that are spaced apart from each other and alternately arranged along the X direction on the substrate 100, as shown, it can be done as follows: Figure 6As shown, firstly, on the substrate 100 between adjacent bit line structures BL1 and BL2, an etching process is used to etch downwards along the Y direction to form a memory node contact trench (not shown) on the outside of the sidewall structure 130 after removing the isolation layer 110 and part of the substrate 100. Then, a contact material layer (not shown) is formed to completely cover the substrate 100 and fill the memory node contact trench. Next, an etching or planarization process is used to remove the contact material layer outside the memory node contact trench until the top surfaces of the bit line structure BL and the sidewall structure 130 are exposed, thereby obtaining the contact structures SNC located in the memory node contact trenches. The contact material layer can be a silicon-containing semiconductor material, such as phosphorus-doped silicon. Then, a metal material layer (not shown) is deposited on the substrate 100, and the metal material layer and the substrate 100 are silicided to allow the top of the contact structure SNC, which is made of a silicon-containing semiconductor material such as phosphorus-doped silicon, to react with the metal material layer to form a silicide layer 170, resulting in... Figure 6 The structure shown.
[0064] Next, as Figure 8 As shown, using a deposition process, a first connection pad material layer (such as titanium nitride) and a second connection pad material layer (such as tungsten metal) of the connection pad structure 180 are deposited on a substrate 100, and then etched to form a first connection pad layer 181 that wraps around the surfaces of the silicide layer 170, the first bit line structure BL1, and the second bit line structure BL2, and a second connection pad layer 182 that fills the gap between adjacent first bit line structures BL1 and second bit line structures BL2 and whose top surface is higher than the top surface of the first bit line structure BL1. This forms a connection pad structure 180 including the first connection pad layer 181 and the second connection pad layer 182 arranged sequentially from bottom to top. Then, a mask layer (not shown) is formed on the connection pad structure 180, wherein the mask layer has an isolation structure pattern. Using this mask layer as a mask, using an etching process, an isolation structure 190 with its bottom surface in direct contact with the bit line structure BL is formed along the Y direction on the connection pad structure 180 on one side of the bit line structure BL and on part of the bit line structure BL. Specifically, the isolation structure 190 includes a first isolation structure 191 and a second isolation structure 192 that are separated from each other and alternately arranged along the X direction. The bottom surface of the first isolation structure 191 extends to the first bit line structure BL1 to directly contact the corresponding first bit line structure BL1, and the bottom surface of the second isolation structure 192 also extends to the second bit line structure BL2 to directly contact the corresponding second bit line structure BL2, thus forming the semiconductor device in the aforementioned second embodiment.
[0065] In summary, the semiconductor device provided in the embodiments of the present invention may specifically include: a substrate; a plurality of bit line structures disposed on the substrate, comprising a conductive layer and an insulating capping layer stacked sequentially from bottom to top; the bit line structures including a first bit line structure and a second bit line structure that are horizontally separated and alternately arranged, wherein the top surface of the first bit line structure is higher than the top surface of the second bit line structure; a plurality of connection pad structures disposed between adjacent bit line structures and extending horizontally to cover a portion of the top surface of the bit line structures; and a plurality of isolation structures disposed between adjacent connection pad structures, including a first isolation structure located above the first bit line structure and a second isolation structure located above the second bit line structure.
[0066] In this invention, by setting multiple bit line structures in a semiconductor device to be arranged alternately in the horizontal direction as a first bit line structure and a second bit line structure with their top surfaces at different horizontal heights, the problems of top adhesion and leakage of adjacent bit line structures caused by the miniaturization of semiconductor device size, which are present in the prior art, are avoided. This aims to improve the reliability and performance of the semiconductor device.
[0067] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0068] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, and computer-readable storage media are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.
[0069] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.
Claims
1. A semiconductor device, characterized in that, include: Base; Multiple bit line structures are disposed on the substrate, including a conductive layer and an insulating capping layer stacked sequentially from bottom to top. The bit line structure includes a first bit line structure and a second bit line structure that are separated from each other in the horizontal direction and arranged alternately, and the top surface of the first bit line structure is higher than the top surface of the second bit line structure. Multiple connecting pad structures are disposed between adjacent bit line structures and extend horizontally to cover a portion of the top surface of the bit line structures; Multiple contact points are arranged on both sides of the second bit line structure; A dielectric layer is disposed on the substrate and covers the top surface of the second bit line structure; Multiple isolation structures are disposed between adjacent connection pad structures, including a first isolation structure located above the first bit line structure and a second isolation structure located above the second bit line structure; wherein, a portion of the second isolation structure directly contacts the second bit line structure, and another portion of the second isolation structure is isolated from the second bit line structure through the dielectric layer.
2. The semiconductor device as claimed in claim 1, characterized in that, The top surfaces of the conductive layer of the first bit line structure and the conductive layer of the second bit line structure are at the same horizontal height.
3. The semiconductor device as described in claim 1, characterized in that, The first isolation structure is in direct contact with the first bit line structure.
4. The semiconductor device as claimed in claim 1, characterized in that, The first isolation structure and the second isolation structure extend to different depths of the first bit line structure and the second bit line structure.
5. The semiconductor device as claimed in claim 1, characterized in that, The bottom surface of the first isolation structure is lower than the bottom surface of the second isolation structure.
6. The semiconductor device as claimed in claim 1, characterized in that, The distance between the top surface of the first bit line structure and the top surface of the connecting pad structure is less than the distance between the top surface of the second bit line structure and the top surface of the connecting pad structure.
7. The semiconductor device as claimed in claim 1, characterized in that, The dielectric layer is at the same horizontal height as the top surface of the first bit line structure.
8. A semiconductor device, characterized in that, include: The substrate includes the active region defined by shallow trench isolation; Multiple bit line structures are disposed on the substrate, including a conductive layer and an insulating capping layer stacked sequentially from bottom to top. The bit line structure includes a first bit line structure and a second bit line structure that are separated from each other in the horizontal direction and arranged alternately, and the top surface of the first bit line structure is higher than the top surface of the second bit line structure. The dielectric layer directly contacts the sidewalls and top surface of the second bit line structure, and the dielectric layer is electrically isolated from the active region; Multiple connecting pad structures are disposed between adjacent bit line structures and extend horizontally to cover a portion of the top surface of the bit line structures; Multiple isolation structures are disposed between adjacent connecting pad structures, including a first isolation structure located above the first bit line structure and a second isolation structure located above the second bit line structure; In one part, the second isolation structure is in direct contact with the second bit line structure, while in another part, the second isolation structure and the second bit line structure are isolated from each other through the dielectric layer.
9. A method for manufacturing a semiconductor device, characterized in that, include: Provide a base; Multiple mutually separated bit line structures are formed. The bit line structure is located on the substrate and includes a conductive layer and an insulating cap layer stacked sequentially from bottom to top. The bit line structure includes a first bit line structure and a second bit line structure that are mutually separated and alternately arranged in the horizontal direction, and the top surface of the first bit line structure is higher than the top surface of the second bit line structure. Multiple connecting pad structures are formed, the connecting pad structures being located between adjacent bit line structures and extending horizontally to cover a portion of the top surface of the bit line structures; Multiple contact structures are formed, and the contact structures are disposed on both sides of the second bit line structure; A dielectric layer is formed, the dielectric layer being disposed on the substrate and covering the top surface of the second bit line structure; Multiple isolation structures are formed, the isolation structures being located between adjacent connection pad structures and including a first isolation structure located above the first bit line structure and a second isolation structure located above the second bit line structure; wherein, a portion of the second isolation structure directly contacts the second bit line structure, and another portion of the second isolation structure is isolated from the second bit line structure through the dielectric layer.
10. The method for manufacturing a semiconductor device as described in claim 9, characterized in that, The steps of forming the first bit line structure and the second bit line structure include: Multiple first-line structures are formed, and the multiple first-line structures are arranged on the substrate with horizontal separation between them; An insulating material layer and a photoresist layer are formed sequentially, wherein the insulating material layer is located between adjacent first bit line structures, and the photoresist layer is located on the insulating material layer; Using the photoresist layer as a mask, a portion of the height of the first bit line structure is removed to obtain a second bit line structure that alternates with the remaining first bit line structure in the horizontal direction.
11. The method for manufacturing a semiconductor device as described in claim 9, characterized in that, The top surfaces of the conductive layer of the first bit line structure and the conductive layer of the second bit line structure are at the same horizontal height.
12. The method for manufacturing a semiconductor device as described in claim 9, characterized in that, The first isolation structure is in direct contact with the first bit line structure.