A display panel

Abstract

This application discloses a display panel having a display area and a bonding area located on one side of the display area; the display panel includes an array substrate located in the display area and the bonding area, and a plurality of fan-out traces located on the array substrate; the array substrate includes a plurality of signal lines located in the display area; the plurality of fan-out traces are located in the display area and are electrically connected to at least a portion of the plurality of signal lines in a one-to-one correspondence; the fan-out traces overlap with a portion of the plurality of signal lines in a direction perpendicular to the array substrate. This application can reduce the parasitic capacitance generated between the fan-out traces and the signals in the display area.

Description

[0001] This application is a divisional application of application number 202210033044.9 filed on January 12, 2022, entitled "A Display Panel". Technical Field

[0002] This application relates to the field of display technology, specifically to a display panel. Background Technology

[0003] As the proportion of the display area in OLED (Organic Light Emitting Display) panels continues to increase, the design space left for the border is constantly being compressed, and the irregular design of the panel border makes the original conventional design no longer able to meet the requirements.

[0004] In border design, the portion occupying a significant portion of the space is the signal lines leading from the IC (integrated circuit) into the display area. These lines are typically distributed in a fan shape, also known as fanout traces. In conventional designs, these fanout traces are generally located in the non-display area. In recent years, to reduce the space required for these fanout traces, the trace width and spacing can be increased in the manufacturing process. However, due to limitations in process capability, different metal layers are sometimes used for the fanout traces.

[0005] Therefore, compressing the fanout traces entering the display area from the IC becomes crucial for border compression. This includes designing the fanout traces within the display area itself, meaning the fanout traces are distributed within the pixels of the display area. This design not only solves the problem of reduced design space caused by border compression but also avoids routing the fanout traces at chamfered borders, thus addressing the issue of insufficient space for irregularly shaped borders. However, placing the fanout traces within the display area also introduces some problems. For example, the parasitic capacitance generated between the fanout traces and the signal lines within the pixels leads to a larger signal loading, resulting in insufficient IC push and increased crosstalk risk. Summary of the Invention

[0006] This application provides a display panel that can reduce the parasitic capacitance between the fan-out traces and the signals in the sub-pixel area of ​​the display area, reduce the signal load in the sub-pixel area, avoid insufficient IC push, and reduce the risk of crosstalk, thereby improving the stability of the display panel.

[0007] This application provides a display panel having a display area and a bonding area located on one side of the display area; the display panel includes an array substrate located in the display area and the bonding area, and a plurality of fan-out traces located on the array substrate;

[0008] The array substrate includes multiple signal lines located in the display area and spaced apart in a first direction; each signal line extends along a second direction perpendicular to the first direction.

[0009] The plurality of fan-out traces are located in the display area and are electrically connected to at least a portion of the plurality of signal lines; each of the fan-out traces includes a first trace portion located near the bonding area and extending along the second direction, and a second trace portion connected to the end of the first trace portion away from the bonding area and extending along the first direction.

[0010] Each of the first trace portions overlaps with one of the plurality of signal lines in a direction perpendicular to the array substrate, and the end of the second trace portion away from the first trace portion is electrically connected to the corresponding signal line.

[0011] Optionally, the width of the first trace portion is less than or equal to the width of the corresponding signal line.

[0012] Optionally, the multiple signal lines form multiple signal line groups arranged sequentially adjacent to each other in the first direction, and each signal line group includes a data line and a power supply voltage signal line arranged adjacent to each other.

[0013] The multiple fan-out traces are electrically connected to the multiple data lines in a one-to-one correspondence; each of the first trace portions is arranged to overlap with a data line or a power supply voltage signal line in a direction perpendicular to the array substrate.

[0014] Optionally, the display panel further includes a shielding layer located on the side of the plurality of fan-out traces away from the plurality of signal lines and corresponding to the plurality of fan-out traces; the shielding layer is electrically connected to the power supply voltage signal lines.

[0015] Optionally, the shielding layer includes multiple shielding lines that correspond one-to-one with the multiple fan-out lines;

[0016] The width of the shielding trace is greater than or equal to the width of the corresponding fan-out trace, and less than or equal to the width of the corresponding signal line.

[0017] Optionally, the power supply voltage signal line includes a first sub-power supply voltage signal line and a second sub-power supply voltage signal line stacked in a direction perpendicular to the array substrate; wherein the first sub-power supply voltage signal line is electrically connected to the second sub-power supply voltage signal line; and the data line is disposed on the same layer as the second sub-power supply voltage signal line.

[0018] Optionally, the array substrate further includes a plurality of sub-pixel regions arranged in multiple rows and columns in the first direction and the second direction; each column of the sub-pixel regions is correspondingly arranged with one of the signal line groups;

[0019] The sub-pixel region includes a driving thin-film transistor located on the side of the power supply voltage signal line away from the fan-out trace and electrically connected to the power supply voltage signal line in the corresponding signal line group.

[0020] Optionally, multiple first wiring sections form multiple first wiring section groups arranged sequentially and adjacently in the first direction, and each first wiring section group includes two first wiring sections arranged adjacently.

[0021] The plurality of first trace groups are arranged to overlap with a portion of the plurality of signal line groups in a direction perpendicular to the array substrate.

[0022] Optionally, the array substrate includes a plurality of scan lines located in the display area and extending along the first direction;

[0023] Each of the second traces overlaps with one of the plurality of scan lines in a direction perpendicular to the array substrate.

[0024] Optionally, the display panel further includes an organic light-emitting layer located on the side of the plurality of fan-out lines away from the array substrate and electrically connected to the array substrate.

[0025] The display panel provided in this application places the first trace portion of the fan-out trace on the data lines and power supply voltage signal lines within the display area. The data lines and power supply voltage signal lines can form a shield between the fan-out trace and the driving circuit of the sub-pixel area, which can reduce the influence of the fan-out trace and various complex signals in the sub-pixel area. For example, it reduces the parasitic capacitance generated between the fan-out trace and various signals in the sub-pixel area, reduces the signal load in the sub-pixel area, avoids insufficient IC push, and reduces the risk of crosstalk, thereby improving the stability of the display panel. Attached Figure Description

[0026] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0027] Figure 1This is a schematic diagram of a partial wiring distribution of a display panel provided in an embodiment of this application.

[0028] Figure 2 This is a schematic cross-sectional view of a display panel provided in an embodiment of this application.

[0029] Figure 3 This is a top view of a portion of the wiring of a display panel provided in an embodiment of this application.

[0030] Figure 4 This is a schematic diagram of the cross-sectional structure of another display panel provided in an embodiment of this application.

[0031] Figure 5 A top view of a portion of the wiring of another display panel provided in an embodiment of this application.

[0032] Figure 6 This is a schematic diagram of the cross-sectional structure of another display panel provided in an embodiment of this application.

[0033] Figure 7 This is a schematic diagram of the cross-sectional structure of another display panel provided in an embodiment of this application. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0035] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0036] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0037] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0038] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0039] In existing designs that route fan-out traces within the pixel area of ​​the display area, the source fan-out traces from the source IC enter the display area and connect to the data lines via vias. Parasitic capacitances are generated between these fan-out traces and the complex signals within the pixel area, increasing the load on each signal and raising the risk of insufficient IC drive and crosstalk. Specifically, the fan-out traces within the display area form parasitic capacitances with the gate (Q-point) of the driving TFT (Thin Film Transistor), affecting the stability of the driving TFT and thus reducing the panel display quality.

[0040] This application optimizes the existing design of placing fan-out traces in the display area and proposes several different trace design schemes in the display area to reduce the parasitic capacitance generated by fan-out traces and various signals in the pixel area. For details, please refer to the description of the following embodiments.

[0041] Example 1

[0042] Combination Figure 1 and Figure 2 As shown, this application embodiment provides a display panel 1, which has a display area 2 and a bonding area 3 located on one side of the display area 2; the display panel 1 includes an array substrate 4 located in the display area 2 and the bonding area 3, a plurality of fan-out traces 5 located on the array substrate 4, and an organic light-emitting layer 6 located on the side of the plurality of fan-out traces 5 away from the array substrate 4 and electrically connected to the array substrate 4.

[0043] The array substrate 4 includes a plurality of signal lines 7 located in the display area 2 and spaced apart in a first direction (e.g., horizontal direction); each signal line 7 extends along a second direction (e.g., vertical direction) perpendicular to the first direction.

[0044] Specifically, such as Figure 2 As shown, the array substrate 4 also includes a substrate 8, a buffer layer 9 and a thin-film transistor layer 10 sequentially disposed on the substrate 8; multiple signal lines 7 are located on the thin-film transistor layer 10 and are electrically connected to the thin-film transistors in the thin-film transistor layer 10. In a specific embodiment, the substrate 8 is composed of a first PI (polyimide) substrate 11, a first glass substrate 12, a second PI substrate 13 and a second glass substrate 14 stacked sequentially.

[0045] Multiple fan-out traces 5 are located in the display area 2 and are electrically connected to at least a portion of multiple signal lines 7. For example... Figure 1 As shown, each fan-out trace 5 includes a first trace portion 15 disposed near the bonding area 3 and extending along a second direction, and a second trace portion 16 connected to the end of the first trace portion 15 away from the bonding area 3 and extending along a first direction. Each first trace portion 15 overlaps with one of the plurality of signal lines 7 in a direction perpendicular to the array substrate 4, and the end of the second trace portion 16 away from the first trace portion 15 is electrically connected to the corresponding signal line 7.

[0046] Understandably, an insulation layer is provided between the multiple fan-out cables 5 and the multiple signal cables 7.

[0047] It should be noted that the overlapping arrangement described in this application refers to the overlapping projections of two traces arranged on different layers (different layers) in a direction perpendicular to the array substrate 4.

[0048] Specifically, the second routing section 16 and the first routing section 15 can be arranged on the same layer or on different layers; this application does not impose any restrictions. When the second routing section 16 and the first routing section 15 are arranged on different layers, they are connected by vias.

[0049] Specifically, such as Figure 3 As shown, the width of the first trace portion 15 is less than or equal to the width of the corresponding signal line 7. In one specific embodiment, the width of the first trace portion 15 is the same as the width of the second trace portion 16.

[0050] In one specific implementation, such as Figure 1 and Figure 3 As shown, multiple signal lines 7 form multiple signal line groups 17 arranged sequentially and adjacently in a first direction. Each signal line group 17 includes a data line 18 and a power supply voltage signal line 19 arranged adjacently. Multiple fan-out traces 5 are electrically connected to multiple data lines 18 in a one-to-one correspondence. Each first trace portion 15 overlaps with a data line 18 or a power supply voltage signal line 19 in a direction perpendicular to the array substrate 4.

[0051] Understandably, the multiple signal lines 7 include multiple data lines (D1-Dn, where n is a positive integer) 18 and multiple power supply voltage signal lines 19 corresponding to the multiple data lines 18.

[0052] Specifically, power supply voltage signal line 19 includes the VDD trace. Understandably, the VDD trace is connected to the high-potential VDD signal.

[0053] Specifically, such as Figure 1 As shown, the bonding area 3 and the display area 2 are spaced apart in the second direction. The display panel 1 also includes a source IC 20 bonded to the bonding area 3. The first trace portion 15 of the multiple fan-out traces 5 extends to the side near the bonding area 3 and connects to the source IC 20 to transmit the electrical signals output by the source IC 20 to the data line 18.

[0054] Specifically, such as Figure 1As shown, multiple first trace portions 15 form multiple first trace portion groups 21 arranged sequentially and adjacently in a first direction. Each first trace portion group 21 includes two adjacent first trace portions 15. The multiple first trace portion groups 21 overlap with a portion of the signal line groups 17 in the multiple signal line groups 17 in the direction perpendicular to the array substrate 4. In one specific embodiment, the multiple signal line groups 17 that overlap with the multiple first trace portion groups 21 are located in the middle part of the display area 2 and are arranged sequentially and adjacently, which can effectively reduce the area of ​​the bonding area 3. Of course, the specific position of the multiple signal line groups 17 that overlap with the multiple first trace portion groups 21 can be adjusted according to the position of the bonding area 3. Understandably, the first trace portions 15 of multiple fan-out traces 5 are alternately overlapped with data lines 18 and power supply voltage signal lines 19. For example, an odd number of first trace portions 15 overlap with data lines 18, and an even number of first trace portions 15 overlap with power supply voltage signal lines 19. Furthermore, any two first trace portions 15 in any first trace portion group 21 overlap with adjacent data lines 18 and power supply voltage signal lines 19. Since the number of power supply voltage signal lines 19 is the same as the number of data lines 18, the number of first trace portions 15 overlapping with data lines 18 is half the number of data lines 18. This effectively reduces the area occupied by the multiple first trace portions 15, thereby reducing the area of ​​the bonding area 3.

[0055] Specifically, the array substrate 4 also includes a plurality of scan lines (not shown) located in the display area 2 and extending along a first direction. In one embodiment, each second trace portion 16 overlaps with one of the plurality of scan lines in a direction perpendicular to the array substrate 4. Of course, in other embodiments, the second trace portion 16 is arranged only parallel to the scan line.

[0056] Specifically, the array substrate 4 also includes a plurality of sub-pixel regions 22 arranged in multiple rows and columns in the first and second directions, and driving circuits (not shown in the figure) located in the sub-pixel regions 22. Each column of sub-pixel regions 22 is corresponding to a signal line group 17, and each row of sub-pixel regions 22 is corresponding to a scan line.

[0057] Specifically, the driving circuit includes a driving thin-film transistor 23 and a switching thin-film transistor (not shown in the figure) located in the thin-film transistor layer 10; wherein, the source of the driving thin-film transistor 23 is electrically connected to the power supply voltage signal line 19 in the corresponding signal line group 17, and the source of the switching thin-film transistor is electrically connected to the data line 18 in the corresponding signal line group 17.

[0058] In one specific implementation, such as Figure 2As shown, the driving thin-film transistor 23 includes a semiconductor layer 24 disposed on a buffer layer 9, a source electrode 25 and a drain electrode 26 located on both sides of the semiconductor layer 24, a first gate insulating layer 27 covering the semiconductor layer 24, the source electrode 25 and the drain electrode 26, a first gate electrode 28 disposed on the first gate insulating layer 27 and corresponding to the semiconductor layer 24, a second gate insulating layer 29 covering the first gate electrode 28 and the first gate insulating layer 27, a second gate electrode 30 disposed on the second gate insulating layer 29 and corresponding to the first gate electrode 28, an interlayer insulating layer 31 covering the second gate electrode 30 and the second gate insulating layer 29, a via penetrating the first gate insulating layer 27, the second gate insulating layer 29 and the interlayer insulating layer 31 and respectively connected to the source electrode 25 and the drain electrode 26, and a connector 32 filled in the via. Specifically, the connector 32 connected to the source electrode 25 of the driving thin-film transistor 23 is connected to the power supply voltage signal line 19.

[0059] In one specific embodiment, the source 25 and drain 26 are made of polysilicon. However, this application does not limit the materials used for the source 25 and drain 26. The scan line can be disposed on the same layer as the first gate 28 and / or the second gate 30; this application also does not limit this.

[0060] It should be noted that in this embodiment, the data line 18 is connected to the source of the switching thin-film transistor. In one specific embodiment, the source of the switching thin-film transistor and the source 25 of the driving thin-film transistor 23 can be disposed on the same layer and made of the same material. Of course, this embodiment does not limit the position of the source of the switching thin-film transistor, nor does it limit the structure of the switching thin-film transistor.

[0061] Specifically, such as Figure 2 As shown, the display panel 1 also includes a first planarization layer 33 covering the data lines 18 and the power supply voltage signal lines 19, and a second planarization layer 34 covering the multiple fan-out traces 5. Understandably, the multiple fan-out traces 5 are located on the first planarization layer 33.

[0062] Specifically, such as Figure 2 As shown, the organic light-emitting layer 6 is disposed on the second planarization layer 34. Specifically, the organic light-emitting layer 6 includes an anode layer 35, a pixel definition layer 36, a light-emitting functional layer 37, a support layer 38, and a cathode layer 39. The anode layer 35 is located on the second planarization layer 34, and the pixel definition layer 36 is located on the second planarization layer 34 and has multiple pixel openings, with the pixel openings corresponding to the anode layer 35. The light-emitting functional layer 37 is located on the anode layer 35 at the pixel openings; the support layer 38 is located on the pixel definition layer 36; and the cathode layer 39 at least covers the light-emitting functional layer 37.

[0063] Specifically, the anode layer 35 is electrically connected to the drain 26 of the driving thin-film transistor 23. In one embodiment, the display panel 1 further includes a first source / drain electrode block 40 disposed on the same layer as the data line 18 and the power supply voltage signal line 19, and a second source / drain electrode block 41 disposed on the same layer as the multiple fan-out traces 5. The second source / drain electrode block 41 is electrically connected to the first source / drain electrode block 40 through a through-hole penetrating the first planarization layer 33; the first source / drain electrode block 40 is electrically connected to the drain 26 of the driving thin-film transistor 23 through a connector 32; and the anode layer 35 is also electrically connected to the second source / drain electrode block 41 through a through-hole penetrating the second planarization layer 34.

[0064] Understandably, the first source / drain electrode block 40 and the connector 32 are integrally formed.

[0065] It should be noted that this application is also applicable to the gate fanout routing design of display products using gate ICs as drivers. The focus of the embodiments in this application is that the source fanout (i.e., data fanout) routing design is on the data lines and power supply voltage signal lines in the display area, while the gate can be a conventional design driven by a GOA, which will not be described in detail in this application.

[0066] In this embodiment, the first trace portion 15 of the fan-out trace 5 is distributed on the data line 18 and the power supply voltage signal line 19 within the display area 2. The data line 18 and the power supply voltage signal line 19 can form a shield between the fan-out trace 5 and the driving circuit of the sub-pixel area 22, which can reduce the influence of complex signals in the sub-pixel area 22 on the fan-out trace 5. For example, it reduces the parasitic capacitance between the signals in the sub-pixel area 22 and the fan-out trace 5, reduces the signal load in the sub-pixel area 22, avoids insufficient IC drive, and reduces the risk of crosstalk. In particular, this embodiment can reduce the parasitic capacitance between the fan-out trace 5 and the gates (e.g., the first gate 28 and the second gate 30) of the driving thin-film transistor 23 in the sub-pixel area 22, increase the stability of the driving thin-film transistor 23, and thus improve the stability of the display panel 1.

[0067] Example 2

[0068] like Figure 1 , Figure 4 and Figure 5 As shown, this application embodiment also provides a display panel 1. The difference from the above embodiment 1 is that the display panel 1 in this application embodiment further includes a shielding layer 42 located on the side of the multiple fan-out routing lines 5 away from the multiple signal lines 7 and corresponding to the multiple fan-out routing lines 5; the shielding layer 42 is electrically connected to the power supply voltage signal line 19.

[0069] Specifically, such as Figure 5As shown, the shielding layer 42 includes multiple shielding traces 43, each corresponding to one of the multiple fan-out traces 5. The width of each shielding trace 43 is greater than or equal to the width of the corresponding fan-out trace 5, and less than or equal to the width of the corresponding signal line 7. It is understood that each shielding trace 43 is connected to a VDD signal.

[0070] Specifically, such as Figure 4 As shown, the shielding layer 42 is located on the second planarization layer 34. The display panel 1 also includes a third planarization layer 44 located between the shielding layer 42 and the organic light-emitting layer 6, and a third source / drain electrode block 45 disposed on the same layer as the shielding layer 42. The third source / drain electrode block 45 is electrically connected to the second source / drain electrode block 41 through a through-hole penetrating the second planarization layer 34; the anode layer 35 is electrically connected to the third source / drain electrode block 45 through a through-hole penetrating the third planarization layer 44.

[0071] Specifically, the shielding trace 43 is electrically connected to the corresponding power supply voltage signal line 19 through a via passing through the first planarization layer 33 and the second planarization layer 34, so as to access the high-potential VDD signal.

[0072] In this embodiment, a metal layer 42 is added to the fan-out traces 5 distributed on the data line 18 and the power supply voltage signal line 19 as a shielding layer. This shielding layer 42 is connected to a high-potential VDD signal, which can further reduce the parasitic capacitance between the fan-out traces 5 and the signals in the sub-pixel region 22, especially the parasitic capacitance between the fan-out traces 5 and the gate of the driving thin-film transistor 23, thereby increasing the stability of the driving thin-film transistor 23. Therefore, this embodiment further reduces the signal load in the sub-pixel region 22, avoids insufficient IC push, reduces the risk of crosstalk, and improves the stability of the display panel 1.

[0073] Example 3

[0074] like Figure 1 and Figure 6 As shown, this application embodiment also provides a display panel 1. Unlike the first embodiment described above, the power supply voltage signal line 19 in this application embodiment includes a first sub-power supply voltage signal line 46 and a second sub-power supply voltage signal line 47 stacked in opposite layers in a direction perpendicular to the array substrate 4; wherein the first sub-power supply voltage signal line 46 and the second sub-power supply voltage signal line 47 are electrically connected; and the data line 18 is disposed on the same layer as the second sub-power supply voltage signal line 47. It is understood that an insulating layer, namely the first planarization layer 33 hereinafter referred to as the first sub-power supply voltage signal line 46 and the second sub-power supply voltage signal line 47, is provided between them.

[0075] Specifically, such as Figure 6As shown, the display panel 1 in this embodiment further includes a source electrode block 48 disposed on the same layer as the first sub-power supply voltage signal line 46 and corresponding to the data line 18. In this embodiment, a first planarization layer 33 is disposed between the first sub-power supply voltage signal line 46 and the second sub-power supply voltage signal line 47, and a second planarization layer 34 is disposed between multiple signal lines 7 and multiple fan-out traces 5. A first source / drain electrode block 40 is disposed on the same layer as the first sub-power supply voltage signal line 46, and a second source / drain electrode block 41 is disposed on the same layer as the second sub-power supply voltage signal line 47. The second sub-power supply voltage signal line 47 is electrically connected to the first sub-power supply voltage signal line 46 through a through-hole penetrating the first planarization layer 33.

[0076] Specifically, the display panel 1 in this embodiment further includes a third planarization layer 44 disposed between the fan-out trace 5 and the organic light-emitting layer 6, and a third source / drain electrode block 45 disposed on the same layer as the fan-out trace 5; the third source / drain electrode block 45 is electrically connected to the second source / drain electrode block 41 through a through hole penetrating the second planarization layer 34, and the anode layer 35 is electrically connected to the third source / drain electrode block 45 through a through hole penetrating the third planarization layer 44.

[0077] In this embodiment, the power supply voltage signal line 19 is composed of a first sub-power supply voltage signal line 46 and a second sub-power supply voltage signal line 47, forming a double-layer routing structure. This increases the spacing between the fan-out routing line 5 and the data line 18 and the signal lines (e.g., the gates of the driving thin-film transistors 23) within the sub-pixel area 22, thereby further reducing parasitic capacitance. Furthermore, the double-layer routing structure of the power supply voltage signal line 19 reduces the problem of excessive VDD signal load, thereby increasing the display uniformity of the display panel 1. Therefore, this embodiment further reduces the signal load and VDD signal load within the sub-pixel area 22, avoiding insufficient IC thrust, reducing crosstalk risk, and improving the stability and display uniformity of the display panel 1.

[0078] Example 4

[0079] like Figure 1 and Figure 7 As shown, this application embodiment also provides a display panel 1. The difference from the above embodiment three is that the display panel 1 in this application embodiment further includes a shielding layer 42 located on the side of the multiple fan-out routing lines 5 away from the multiple signal lines 7 and corresponding to the multiple fan-out routing lines 5; the shielding layer 42 is electrically connected to the power supply voltage signal line 19, specifically to the second sub-power supply voltage signal line 47.

[0080] Specifically, the shielding layer 42 includes multiple shielding traces 43, each corresponding to one of the multiple fan-out traces 5. The width of each shielding trace 43 is greater than or equal to the width of the corresponding fan-out trace 5, and less than or equal to the width of the corresponding signal line 7. Understandably, each shielding trace 43 is connected to a VDD signal.

[0081] Specifically, in this embodiment, the third planarization layer 44 is disposed between the shielding layer 42 and the organic light-emitting layer 6. The display panel 1 in this embodiment also includes a passivation layer 49 disposed between the fan-out trace 5 and the shielding layer 42, and a fourth source / drain electrode block 50 disposed on the same layer as the shielding layer 42. The fourth source / drain electrode block 50 is electrically connected to the third source / drain electrode block 45 through a through-hole penetrating the passivation layer 49; the anode layer 35 is electrically connected to the fourth source / drain electrode block 50 through a through-hole penetrating the third planarization layer 44; and the shielding layer 42 is electrically connected to the second sub-power supply voltage signal line 47 through a through-hole penetrating the passivation layer 49 and the second planarization layer 34.

[0082] In this embodiment, a metal layer is added on top of the shielding layer 42, making the power supply voltage signal line 19 a double-layer routing structure composed of the first sub-power supply voltage signal line 46 and the second sub-power supply voltage signal line 47. This increases the spacing between the fan-out routing line 5 and the data line 18 and the signal lines (e.g., the gates of the driving thin-film transistors 23) in the sub-pixel area 22, thereby further reducing parasitic capacitance. Furthermore, the double-layer routing structure of the power supply voltage signal line 19 can reduce the problem of excessive VDD signal load, thereby increasing the display uniformity of the display panel 1. Therefore, this embodiment further reduces the signal load and VDD signal load in the sub-pixel area 22, avoids insufficient IC thrust, reduces crosstalk risk, and improves the stability and display uniformity of the display panel 1.

[0083] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0084] The above provides a detailed description of a display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, The display panel has a display area and a bonding area located on one side of the display area; the display panel includes an array substrate located in the display area and the bonding area, and multiple fan-out traces located on the array substrate; The array substrate includes multiple signal lines located in the display area; the multiple fan-out traces are located in the display area and are electrically connected to at least a portion of the multiple signal lines; the fan-out traces overlap with a portion of the multiple signal lines in a direction perpendicular to the array substrate; the multiple signal lines include at least one power supply voltage signal line, and at least one fan-out trace overlaps with the power supply voltage signal line; The display panel further includes a shielding layer located on the side of the plurality of fan-out traces away from the plurality of signal lines and corresponding to the plurality of fan-out traces; the shielding layer is electrically connected to the power supply voltage signal line; the shielding layer includes a plurality of shielding traces corresponding one-to-one with the plurality of fan-out traces; the width of the shielding trace is greater than or equal to the width of the corresponding fan-out trace and less than or equal to the width of the corresponding signal line.

2. The display panel according to claim 1, characterized in that, The fan-out routing includes a first routing portion disposed near the binding area and extending along a second direction, and a second routing portion connected to the end of the first routing portion away from the binding area and extending along a first direction; the first direction and the second direction are perpendicular to each other. The end of the second trace portion away from the first trace portion is electrically connected to the corresponding signal line; at least a portion of the first trace portion overlaps with a portion of the multiple signal lines.

3. The display panel according to claim 2, characterized in that, The plurality of signal lines also include a plurality of data lines spaced apart in the first direction and extending along the second direction, wherein the plurality of fan-out traces are electrically connected to the plurality of data lines in a one-to-one correspondence; the end of the second trace portion away from the first trace portion is electrically connected to the corresponding data line; the first trace portion overlaps with one of the plurality of data lines.

4. The display panel according to claim 2, characterized in that, At least a portion of the power supply voltage signal line extends along the second direction, and at least a portion of the first trace overlaps with the power supply voltage signal line extending along the second direction.

5. The display panel according to claim 2, characterized in that, The power supply voltage signal line includes a first sub-power supply voltage signal line and a second sub-power supply voltage signal line stacked in a direction perpendicular to the array substrate; the first sub-power supply voltage signal line and the second sub-power supply voltage signal line are electrically connected; at least one of the fan-out traces overlaps with the first sub-power supply voltage signal line and / or the second sub-power supply voltage signal line.

6. The display panel according to any one of claims 1 to 5, characterized in that, The width of the fan-out trace at the overlapping location is less than or equal to the width of the corresponding signal line.

7. The display panel according to claim 2, characterized in that, The array substrate includes multiple scan lines located in the display area and extending along the first direction; At least a portion of the second trace overlaps with one of the plurality of scan lines in a direction perpendicular to the array substrate.

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