Display substrate, manufacturing method thereof and display device

Abstract

A display substrate, its manufacturing method, and a display device are disclosed. The display substrate has a display area (AA) and a peripheral area (NA). The display area (AA) includes N pixel groups arranged along a first direction, each pixel group including at least one row of the pixel area. The display substrate includes: multiple first reset lines (RESET1) and multiple second reset lines (RESET2), each row of pixel area corresponding to one first reset line (RESET1) and one second reset line (RESET2); N+M first shift register units (GOA1) are arranged along the first direction, the i-th first shift register unit (GOA1)... The output of GOA1 is connected to the second reset line (RESET2) corresponding to the i-M row pixel area; the output of the j-th first shift register (GOA1) is connected to the first reset line (RESET1) corresponding to the j-th row pixel area through the signal transmission line (60); N is an integer greater than 2, M is a preset positive integer, M+1≤i≤N+M, 1≤j≤N, and i and j are both integers; the orthographic projection of the signal transmission line (60) on the substrate (100) overlaps with the orthographic projection of at least one first shift register unit (GOA1) on the substrate (100).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a display substrate and its manufacturing method, and a display device. Background Technology

[0002] A driving circuit is disposed in the peripheral area of ​​the display substrate to provide driving signals to the pixel units of the display area. Multiple pixel units are disposed in the display area of ​​the display device, and each pixel unit includes a pixel circuit. Each pixel circuit is electrically connected to the driving circuit in the peripheral area. The driving circuit provides scanning signals and light-emitting control signals to the pixel circuit to control the pixel circuit to provide driving current to the light-emitting device. Summary of the Invention

[0003] This disclosure provides a display substrate having a display area and a peripheral area. The display area includes N pixel groups arranged along a first direction, and each pixel group includes at least one row of the pixel area. The display substrate includes:

[0004] Substrate;

[0005] Multiple first reset lines and multiple second reset lines are disposed on the substrate, with each row of pixel area corresponding to one first reset line and one second reset line;

[0006] N+M first shift register units are disposed on the substrate and located in the peripheral area. The N+M first shift register units are arranged along the first direction. The output terminal of the i-th first shift register unit is connected to the second reset line corresponding to the iM-th row of pixels. The output terminal of the j-th first shift register is connected to the first reset line corresponding to the j-th row of pixels through a signal transmission line. N is an integer greater than 2, M is a preset positive integer, M+1≤i≤N+M, 1≤j≤N, and i and j are both integers.

[0007] Wherein, the orthographic projection of the signal transmission line on the substrate overlaps with the orthographic projection of at least one of the first shift register units on the substrate.

[0008] In some embodiments, the first shift register unit includes an output transistor connected to the output terminal of the first shift register unit, wherein the orthographic projection of the signal transmission line on the substrate overlaps with the orthographic projection of the output transistor of at least one of the first shift register units on the substrate.

[0009] In some embodiments, the orthographic projection of each of the signal transmission lines on the substrate overlaps with the orthographic projection of M-1 of the first shift register units on the substrate.

[0010] In some embodiments, the first shift register unit includes a storage capacitor, and the orthographic projection of the signal transmission line on the substrate does not overlap with the orthographic projection of the storage capacitor on the substrate.

[0011] In some embodiments, the signal transmission line includes a plurality of transmission line segments and a connecting line segment located between two adjacent transmission line segments, the transmission line segments extending along the first direction;

[0012] The signal transmission line has a start end and a tail end. The start end is connected to the output end of the first shift register unit, and the tail end is connected to the reset line. For two adjacent transmission segments in the same signal transmission line, the distance from the transmission segment closer to the start end to the display area is greater than the distance from the transmission segment farther from the start end to the display area.

[0013] In some embodiments, the connecting segment is a straight line segment, and the connecting segment forms an obtuse angle with the adjacent transmission segment.

[0014] In some embodiments, the connecting segments in the signal transmission lines to which the plurality of first shift register units are connected are divided into a plurality of first segment groups, the plurality of first segment groups being arranged along the first direction, and at least one first segment group including M-1 connecting segments.

[0015] Wherein, the center line connecting the M-1 connecting segments is a straight line, and the extension direction of the center line intersects the first direction and the extension direction of the first reset line;

[0016] Alternatively, the centers of the M-1 connecting segments are not on the same straight line.

[0017] In some embodiments, the center line connecting the M-1 connecting segments is a straight line, and the center connection and the connecting segments are inclined in different directions.

[0018] In some embodiments, the M-1 connecting segments are all of the same length;

[0019] Alternatively, at least the two connecting segments are of different lengths.

[0020] In some embodiments, the transmission line segments in the signal transmission lines connected to the plurality of first shift register units are divided into a plurality of second line segment groups, the plurality of second line segment groups are arranged along a second direction, each second line segment group includes a plurality of transmission line segments arranged along the first direction, and the plurality of transmission line segments in the same second line segment group are located on the same straight line.

[0021] In some embodiments, the distance between any two adjacent groups of second line segments is equal.

[0022] In some embodiments, the display substrate further includes:

[0023] Multiple scan lines, with one scan line corresponding to each row of pixel areas;

[0024] A plurality of second shift register units are located in the peripheral area, and the output of each second shift register unit is connected to one of the scan lines;

[0025] The power line has an orthographic projection on the substrate that overlaps with the orthographic projection of the second shift register unit on the substrate.

[0026] In some embodiments, the plurality of second shift register units are located on the side of the plurality of first shift register units closer to the display area.

[0027] In some embodiments, the display substrate further includes:

[0028] Multiple drive signal lines are provided to provide signals to the plurality of first shift register units, wherein at least one of the multiple drive signal lines has an orthographic projection on the substrate that overlaps with the orthographic projection of the plurality of first shift register units on the substrate.

[0029] In some embodiments, the orthographic projections of the drive signal line and the signal transmission line on the substrate do not overlap.

[0030] In some embodiments, at least one of the drive signal lines is disposed on the same layer as the signal transmission line.

[0031] In some embodiments, the display substrate further includes:

[0032] Multiple connection lines, each connection line corresponding to one first shift register unit, the first shift register unit being connected to the second reset line through the corresponding connection line; except for the last stage first shift register unit, each of the remaining first shift register units is also connected to the input terminal of the next stage first shift register unit through the connection line;

[0033] Multiple first adapters are provided, each first adapter corresponding to one signal transmission line. One end of the first adapter is connected to the connection line through a first via, and the other end is connected to the signal transmission line through a second via.

[0034] In some embodiments, the first shift register unit includes a plurality of transistors, and the orthogonal projections of the first via and the second via on the substrate do not overlap with the orthogonal projections of the transistors on the substrate.

[0035] In some embodiments, a plurality of the first adapters are arranged along the first direction.

[0036] In some embodiments, the connecting line is disposed on the same layer as the second reset line and is electrically connected.

[0037] In some embodiments, the signal transmission line is located on the side of the layer containing the first adapter away from the substrate.

[0038] In some embodiments, the display substrate further includes:

[0039] The second adapter has one end connected to the signal transmission line through a third via, and the other end connected to the first reset line through a fourth via.

[0040] The first shift register unit includes multiple transistors, and the orthogonal projections of the third via and the fourth via on the substrate do not overlap with the orthogonal projections of the transistors on the substrate.

[0041] In some embodiments, the plurality of second adapters are arranged along a first direction.

[0042] This disclosure also provides a display device, which includes the display substrate described above.

[0043] This disclosure also provides a method for manufacturing a display substrate, the display substrate having a display area and a peripheral area, the display area including N rows of pixel areas arranged along a first direction, wherein the manufacturing method includes:

[0044] Multiple first reset lines and multiple second reset lines are formed on the substrate, and each row of the pixel area corresponds to one first reset line and one second reset line;

[0045] N+M first shift register units are formed on the substrate at positions corresponding to the peripheral region; wherein, the N+M first shift register units are arranged along the first direction, the output terminal of the i-th first shift register unit is connected to the second reset line corresponding to the iM-th row of pixels; the output terminal of the j-th first shift register is connected to the first reset line corresponding to the j-th row of pixels through a signal transmission line; N is an integer greater than 2, M is a preset positive integer, M+1≤i≤N+M, 1≤j≤N, and i and j are both integers;

[0046] Wherein, the orthographic projection of the signal transmission line on the substrate overlaps with the orthographic projection of at least one of the first shift register units on the substrate.

[0047] In some embodiments, the manufacturing method further includes:

[0048] Multiple drive signal lines are formed, which are used to provide signals to the multiple first shift register units. At least one of the multiple drive signal lines has an orthographic projection on the substrate that overlaps with the orthographic projection of the multiple first shift register units on the substrate.

[0049] At least one of the drive signal lines is formed synchronously with the signal transmission line. Attached Figure Description

[0050] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0051] Figure 1 This is a plan view of the display substrate provided in some embodiments.

[0052] Figure 2 The diagram shows the circuit schematics of the pixel circuits and light-emitting devices provided in some embodiments.

[0053] Figure 3 for Figure 2 Timing diagram of the pixel circuit in the image.

[0054] Figure 4 This is a timing diagram of some signals from the pixel circuits in the nth and (n+1)th rows.

[0055] Figure 5 This is a plan view of a display substrate provided in some embodiments of this disclosure.

[0056] Figure 6 This is a schematic diagram showing the correspondence between the first shift register unit, the second shift register unit, and the N rows of pixel areas provided in some embodiments of this disclosure.

[0057] Figure 7 This is a circuit schematic of a first shift register unit provided in some embodiments of this disclosure.

[0058] Figure 8A This is a partial schematic diagram of a display substrate provided in some embodiments of this disclosure.

[0059] Figure 8B This is a partial schematic diagram of the region where the first-stage shift register unit is located, provided in some embodiments of this disclosure.

[0060] Figure 9 for Figure 8A A schematic diagram of the semiconductor layer.

[0061] Figure 10 for Figure 8AA schematic diagram of the first gate metal layer.

[0062] Figure 11 for Figure 8A A schematic diagram of the second gate metal layer.

[0063] Figure 12 for Figure 8A A schematic diagram of the first source / drain metal layer.

[0064] Figure 13 for Figure 8A A schematic diagram of the second source / drain metal layer.

[0065] Figure 14 for Figure 8A A schematic diagram of the via distribution.

[0066] Figure 15 This is a plan view of the first shift register unit and signal lines provided in some other embodiments of this disclosure.

[0067] Figure 16 This is a partial schematic diagram of the surrounding area provided in some other embodiments of this disclosure. Detailed Implementation

[0068] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0069] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0070] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0071] It should be noted that the film layers in the embodiments of this disclosure are for illustrative purposes only and do not represent the actual thickness of the film layers.

[0072] It should also be noted that "same-layer arrangement" in the embodiments of this disclosure means that two or more structures are formed by the same material layer through a patterning process, so these two or more structures are in the same layer in terms of stacking relationship; however, this does not mean that the distance between the two or more structures and the substrate 100 is necessarily the same.

[0073] Furthermore, each transistor involved in the embodiments of this disclosure can be independently selected from one of polycrystalline silicon thin-film transistors, amorphous silicon thin-film transistors, oxide thin-film transistors, and organic thin-film transistors. In this disclosure, the "first electrode" specifically refers to the source electrode of the transistor, and the corresponding "second electrode" specifically refers to the drain electrode of the transistor. Of course, those skilled in the art should understand that the "first electrode" and "second electrode" are interchangeable. Additionally, transistors are divided into N-type transistors and P-type transistors. In the embodiments of this disclosure, the operating level signal refers to the signal that controls the transistor to conduct; the non-operating level signal refers to the signal that controls the transistor to turn off. For N-type transistors, the operating level signal is a high-level signal, and the non-operating level signal is a low-level signal; for P-type transistors, the operating level signal is a low-level signal, and the non-operating level signal is a high-level signal.

[0074] Figure 1 Here is a plan view of the display substrate provided in some embodiments, such as Figure 1 As shown, the display substrate includes a display area AA and a peripheral area NA located around the display area AA. The display area AA includes multiple pixel areas arranged in an array. Each pixel area is provided with a light-emitting device 20 and a pixel circuit 10 for providing driving current to the light-emitting device 20.

[0075] Figure 2 The following are circuit schematics of pixel circuits and light-emitting devices provided in some embodiments, such as... Figure 2 As shown, the pixel circuit 10 includes: a first reset transistor T1', a second reset transistor T7', a driving transistor T3', a data writing transistor T4', a first light-emitting control transistor T5', a second light-emitting control transistor T6', a compensation transistor T2', and a storage capacitor Cst. The two ends of the storage capacitor Cst are connected to the first power supply line VDD and the gate of the driving transistor T3', respectively. The gate of the first reset transistor T1' is connected to the first reset line RESET1, the first electrode of the first reset transistor T1' is connected to the gate of the driving transistor T3', and the second electrode of the first reset transistor T1' is connected to the first initialization signal line Vinit1. The gate of the second reset transistor T7' is connected to the gate line, the first electrode of the second reset transistor T7' is connected to the first electrode of the light-emitting device 20, and the second electrode of the second reset transistor T7' is connected to the second initialization signal line Vinit2. The gate of the data writing transistor T4' is connected to the scan line GL, the first electrode of the data writing transistor T4' is connected to the first electrode of the driving transistor T3', and the second electrode of the data writing transistor T4' is connected to the data line. The gate of compensation transistor T2' is connected to the second reset line RESET2, the first electrode of compensation transistor T2' is connected to the gate of driving transistor T3', and the second electrode of compensation transistor T2' is connected to the second electrode of driving transistor T3'. The gate of the first light-emitting control transistor T5' is connected to the light-emitting control line EM, the first electrode of the first light-emitting control transistor T5' is connected to the first power supply line VDD, and the second electrode of the first light-emitting control transistor T5' is connected to the first electrode of driving transistor T3'. The gate of the second light-emitting control transistor T6' is connected to the light-emitting control line EM, the first electrode of the second light-emitting control transistor T6' is connected to the second electrode of driving transistor T3', and the second electrode of the second light-emitting control transistor T6' is connected to the first electrode of light-emitting device 20. The second electrode of light-emitting device 20 is connected to the second power supply line VSS. The first electrode of light-emitting device 20 can be an anode, and the second electrode can be a cathode.

[0076] In this configuration, the first reset transistor T1' in the pixel circuit 10 located in the same row is connected to the same first reset line RESET1; the compensation transistor T2' in the pixel circuit 10 located in the same row is connected to the same second reset line RESET2; the first light-emitting control transistor T5' and the second light-emitting control transistor T6' in the pixel circuit 10 located in the same row are connected to the same light-emitting control line EM; the data writing transistor T4' in the pixel circuit 10 located in the same row is connected to the same scan line GL; and the data writing transistor T4' in the pixel circuit 10 located in the same column is connected to the same data line DL.

[0077] In one example Figure 2 The transistors in the pixel circuit 10 shown are P-type transistors. At this time, the low-level signal controls each transistor to turn on. Figure 3 for Figure 2 Timing diagram of the pixel circuit in the image, such as Figure 3 As shown, the operation of the pixel circuit 10 includes: a reset phase t1, a data writing and compensation phase t2, and a light-emitting phase t3. In the reset phase t1, the first reset line RESET1 provides a low-level signal, thereby controlling the first reset transistor T1' to conduct; subsequently, the second reset line RESET2 provides a valid level signal, thereby controlling the compensation transistor T2' to conduct. In the data writing and compensation phase t2, the scan line GL and the second reset line RESET2 provide low-level signals, thereby controlling the data writing transistor T4' and the compensation transistor T2' to conduct. The data signal on the data line DL and the threshold voltage of the driving transistor T3' are written into the storage capacitor Cst. In the light-emitting phase t3, the signal on the light-emitting control line EM is a low-level signal, thereby controlling the first light-emitting control transistor T5' and the second light-emitting control transistor T6' to conduct, and the driving transistor T3' provides driving current to the light-emitting device.

[0078] The time between the rising edge of the signal on the scan line GL and the emission stage t3 is the threshold compensation time.

[0079] It should be noted that, Figure 2 The pixel circuit 10 in the example is for illustrative purposes only. In other examples, the pixel circuit may also adopt other structures, such as 8T1C, etc.

[0080] like Figure 1As shown, the peripheral area NA is equipped with a first driving circuit 30, a second driving circuit 40, and a third driving circuit 50. The first driving circuit 30 includes multiple cascaded first shift register units GOA1, the second driving circuit 40 includes multiple cascaded second shift register units GOA2, and the third driving circuit 50 includes multiple cascaded third shift register units GOA3. Each third shift register unit GOA3 is connected to a light emission control line EM, each second shift register unit GOA2 is connected to a scan line GL, and each first shift register unit GOA1 is connected to a first reset line RESET1 and a second reset line RESET2. For example, the display area AA includes N rows of pixel areas, and the first driving circuit 30 includes N+M cascaded first shift register units GOA1. The i-th first shift register unit GOA1 is connected to the second reset line RESET2 corresponding to the iM-th pixel area; the j-th first shift register unit GOA1 is connected to the first reset line RESET1 corresponding to the j-th pixel area via signal transmission line 60. N is an integer greater than 2, M is a preset positive integer, M+1≤i≤N+M, 1≤j≤N, and i and j are both integers. In this way, all the first reset lines RESET1 and second reset lines RESET2 are controlled by the same driving circuit, which helps to reduce the bezel width of the display product. Furthermore, a larger M value increases the threshold compensation time, thereby improving image quality.

[0081] Assuming M=2 and N=2480, the number of first shift register units GOA1 is 2482. The first first shift register unit GOA1 is connected to the first reset line RESET1 corresponding to the first row of pixels via signal transmission line 60; the second first shift register unit GOA1 is connected to the first reset line RESET1 corresponding to the second row of pixels via signal transmission line 60; the third first shift register unit GOA1 is connected to the second reset line RESET2 corresponding to the first row of pixels, and is also connected to the first reset line RESET1 corresponding to the third row of pixels via signal transmission line 60; the fourth first shift register unit GOA1 is connected to the first reset line RESET1 corresponding to the second row of pixels. The second reset line RESET2 corresponding to the second row of pixels is connected, and is connected to the first reset line RESET1 corresponding to the fourth row of pixels through signal transmission line 60; similarly, the 2481st first shift register unit GOA1 is connected to the second reset line RESET2 corresponding to the 2479th row of pixels, and is connected to the first reset line RESET1 corresponding to the 2480th row of pixels through signal transmission line 60; the 2481st first shift register unit GOA1 is connected to the second reset line RESET2 corresponding to the 2480th row of pixels.

[0082] It should be noted that the connection between the first shift register unit GOA1 and the first reset line RESET1 (or the second reset line RESET2) in this disclosure refers to the connection between the output terminal of the first shift register unit GOA1 and the first reset line RESET1 (or the second reset line RESET2).

[0083] It should also be noted that in this embodiment of the disclosure, the multi-row pixel area is scanned row by row and then displayed row by row. "The nth row" and "the nth element" refer to the nth row and the nth element arranged along the scanning direction.

[0084] In the above embodiments, the first reset line RESET1 corresponding to different pixel areas is connected to different first shift register units GOA1, and the second reset line RESET2 corresponding to different pixel areas is connected to different first shift register units GOA1. This connection structure is simply referred to as a "one-to-one" structure. In other embodiments, the two first reset lines RESET1 corresponding to every two rows of pixel areas are connected to the same first shift register unit GOA1, and the two second reset lines RESET2 corresponding to every two rows of pixel areas are connected to the same first shift register unit GOA1. This connection structure is simply referred to as a "one-to-two" structure. When using the "one-to-two" structure, assuming that the two first reset lines RESET1 corresponding to the nth and n+1th row pixel areas are connected to the same first shift register unit GOA1, and the two second reset lines RESET2 corresponding to the nth and n+1th row pixel areas are connected to the same first shift register unit GOA1, then the timing diagrams of some signals of the nth row pixel circuit and the n+1th row pixel circuit are as follows. Figure 4 As shown, Figure 4 As shown, the threshold compensation time of the nth row pixel circuit 10 and the (n+1)th row pixel circuit 10 differs significantly, which may lead to obvious differences in the display of odd and even row pixel areas.

[0085] To reduce the display difference between adjacent rows of pixels, in some embodiments, multiple rows of pixels are divided into multiple pixel groups. When a "one-to-two" structure is adopted, each pixel group includes two rows of pixels. The i-th first shift register unit GOA1 is connected to the second reset line RESET2 corresponding to the iM-th pixel group; the j-th first shift register unit GOA1 is connected to the first reset line RESET1 corresponding to the j-th pixel group through the signal transmission line 60; N is an integer greater than 2, M is a preset positive integer, M+1≤i≤N+M, 1≤j≤N, and i and j are both integers. The above M can be set to an integer greater than 1, such as 7 or 8, thereby increasing the threshold compensation time of each row of pixel circuits 10, and thus reducing the display difference between odd and even rows of pixels.

[0086] However, regardless of whether a "one-to-one" or "one-to-two" structure is adopted, the output of the first shift register unit GOA1 and the first reset line RESET1 need to be connected through a signal transmission line 60. The signal transmission line 60 is set between the first drive circuit 30 and the display area AA. The signal transmission line 60 has a certain width, and there needs to be a certain gap between different signal transmission lines 60. Therefore, when M is set to a large value, the setting of multiple signal transmission lines 60 will increase the bezel width of the display product, which is not conducive to the realization of a narrow bezel.

[0087] Figure 5 This is a plan view of a display substrate provided in some embodiments of the present disclosure, such as... Figure 5 As shown, the display substrate includes a display area AA and a peripheral area NA. The display area AA includes N pixel groups arranged along a first direction, each pixel group includes at least one row of pixel areas, and each pixel area includes multiple pixel areas arranged along a second direction. The display substrate includes a substrate 100, and disposed on the substrate 100 are: multiple first reset lines RESET1, multiple second reset lines RESET2, and N+M first shift register units GOA1.

[0088] At least a portion of the first reset line RESET1 and the second reset line RESET2 are located in the display area, with each row of pixels corresponding to one first reset line RESET1 and one second reset line RESET2. The first shift register unit GOA1 is located in the peripheral area NA, and N+M first shift register units GOA1 are arranged along the first direction. The output of the i-th first shift register unit GOA1 is connected to the second reset line RESET2 corresponding to the iM-th pixel group; the output of the j-th first shift register unit GOA1 is connected to the first reset line RESET1 corresponding to the j-th pixel group via signal transmission line 60. N is an integer greater than 2, M is a preset positive integer, M+1≤i≤N+M, 2≤M, 1≤j≤N, and i and j are both integers. Wherein, the output terminal of the first shift register unit GOA1 is connected to the first reset line RESET1 (or the second reset line RESET2) corresponding to a certain pixel group, which means that the output terminal of the first shift register unit GOA1 is connected to the first reset line RESET1 (or the second reset line RESET2) corresponding to each row of pixel areas in the pixel area.

[0089] Each pixel group can include one row of pixel areas to achieve the "one-to-one" structure described above. Alternatively, each pixel group can include two rows of pixel areas to achieve the "one-to-two" structure described above. Of course, each pixel area can also include other numbers. In the following embodiments, each pixel group comprising one row of pixel areas will be used as an example for explanation.

[0090] Figure 6 This is a schematic diagram illustrating the correspondence between the first shift register unit, the second shift register unit, and the N rows of pixel areas provided in some embodiments of this disclosure. It should be noted that... Figure 6 The arrows in the diagram represent signal flow only and do not indicate the actual signal line arrangement. Figure 6 Taking an example where each pixel group comprises one row of pixels, M=8, N=2480, the number of the first shift register unit GOA1 is 2488. Combined with... Figure 5 and Figure 6 As shown, the first first shift register unit GOA1_1 is connected to the first reset line RESET1 corresponding to the first row of pixels via signal transmission line 60; the second first shift register unit GOA1_2 is connected to the first reset line RESET1 corresponding to the second row of pixels via signal transmission line 60; and so on, the eighth first shift register unit GOA1 is connected to the first reset line RESET1 corresponding to the eighth row of pixels via signal transmission line 60. The 9th first shift register unit GOA1_9 is connected to the second reset line RESET2 corresponding to the 1st row pixel area, and is connected to the first reset line RESET1 corresponding to the 9th row pixel area through signal transmission line 60; the 10th first shift register unit GOA1_10 is connected to the second reset line RESET2 corresponding to the 2nd row pixel area, and is connected to the first reset line RESET1 corresponding to the 10th row pixel area through signal transmission line 60; and so on, the 2480th first shift register unit GOA1 is connected to the second reset line RESET2 corresponding to the 2472nd row pixel area, and is connected to the first reset line RESET1 corresponding to the 2480th row pixel area through signal transmission line 60; the 2481st to 2488th first shift register units GOA1 are respectively connected to the second reset lines RESET2 corresponding to the 2473rd to 2480th rows pixel areas.

[0091] In this embodiment of the present disclosure, the orthographic projection of the signal transmission line 60 on the substrate 100 overlaps with the orthographic projection of at least one first shift register unit GOA1 on the substrate 100. In this case, the signal transmission line 60 will not occupy the space between the first shift register unit GOA1 and the display area, thereby reducing the bezel width of the display substrate and facilitating the realization of a narrow bezel.

[0092] The signal transmission line 60 can be located on the side of the first shift register unit GOA1 away from the substrate 100, or it can be located between the first shift register unit GOA1 and the substrate 100. In the embodiments described below, the example of the signal transmission line 60 being located on the side of the first shift register unit GOA1 away from the substrate will be used for illustration.

[0093] Figure 7 Here is a circuit schematic of the first shift register unit provided in some embodiments of this disclosure, such as... Figure 7 As shown, the first shift register unit GOA1 includes: an input sub-circuit ISC, an output sub-circuit OSC, a first processing sub-circuit PSC1, a second processing sub-circuit PSC2, a third processing sub-circuit PSC3, a first voltage regulator sub-circuit SSC1, and a second voltage regulator sub-circuit SSC2.

[0094] In some embodiments, the output sub-circuit OSC is configured to provide a voltage of either the third power line VGH or the fourth power line VGL to the output terminal OUT in response to the voltages of the fourth node N4 and the first node N1. Optionally, the output sub-circuit OSC includes two output transistors, a ninth transistor T9 and a tenth transistor T10. The ninth transistor T9 is connected between the third power line VGH and the output terminal OUT. The gate of the ninth transistor T9 is connected to the fourth node N4. The ninth transistor T9 can be turned on or off depending on the voltage of the fourth node N4. When the ninth transistor T9 is turned on, the voltage of the third power line VGH is provided to the output terminal OUT. The tenth transistor T10 is connected between the output terminal OUT and the fourth power line VGL. The gate of the tenth transistor T10 is connected to the first node N1. The tenth transistor T10 can be turned on or off depending on the voltage of the first node N1. When the tenth transistor T10 is turned on, the voltage of the fourth power line VGL is provided to the output terminal OUT.

[0095] In some embodiments, the input sub-circuit ISC is configured to control the voltage of the first node N1 in response to signals provided to the first input terminal IN and the first clock signal terminal CK, respectively. Optionally, the input sub-circuit ISC includes a first transistor T1. The gate of the first transistor T1 is connected to the first clock signal terminal CK, the first terminal of the first transistor T1 serves as the aforementioned first input terminal IN, and the second terminal of the first transistor T1 is connected to the first node N1.

[0096] In some embodiments, the first processing sub-circuit PSC1 is configured to control the voltage of the fourth node N4 in response to the voltage of the first node N1. Optionally, the first processing sub-circuit PSC1 includes an eighth transistor T8 and a second capacitor C2. The eighth transistor T8 is connected between the third power line VGH and the fourth node N4. The gate of the eighth transistor T8 is connected to the first node N1. The second capacitor C2 is connected between the third power line VGH and the fourth node N4. Optionally, the second capacitor C2 is configured to charge the voltage applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.

[0097] In some embodiments, the second processing sub-circuit PSC2 is connected to the fifth node N5 and configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing sub-circuit PSC2 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1. The first terminal of the first capacitor C1 is connected to the fifth node N5, and the second terminal of the first capacitor C1 is connected to the third node N3, which is a common node between the sixth transistor T6 and the seventh transistor T7. The sixth transistor T6 is connected between the third node N3 and the fifth node N5. The gate of the sixth transistor T6 is connected to the fifth node N5. The seventh transistor T7 is connected between the fourth node N4 and the third node N3. The gate of the seventh transistor T7 is connected to the second clock signal terminal CB.

[0098] In some embodiments, the third processing sub-circuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing sub-circuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3. The fifth transistor T5 is connected between the third power supply line VGH and the fourth transistor T4. The gate of the fifth transistor T5 is connected to the second node N2. The fourth transistor T4 is connected between the fifth transistor T5 and the second clock signal terminal CB. The gate of the fourth transistor T4 is connected to the gate of the tenth transistor T10. The second terminal of the fourth transistor T4 is connected to the second terminal of the fifth transistor T5. The second transistor T2 is connected between the second node N2 and the first clock signal terminal CK, and the gate of the second transistor T2 is connected to the first node N1. The third transistor T3 is connected between the second node N2 and the fourth power supply line VGL, and the gate of the third transistor T3 is connected to the first clock signal terminal CK. The third capacitor C3 is connected between the tenth transistor T10 and the fifth transistor T5. The second terminal of the third capacitor C3 is connected to the second terminal of the fifth transistor T5 and the first terminal of the fourth transistor T4. The first plate of the third capacitor C3 is connected to the gate of the fourth transistor T4 and the gate of the tenth transistor T10.

[0099] Optionally, in some embodiments, the third processing sub-circuit PSC3 is configured to control the voltage of the second node N2. The second terminal of the fourth transistor T4 is connected to the second terminal of the fifth transistor T5, the first terminal of the fourth transistor T4 is connected to the second clock signal terminal CB, and the gate of the fourth transistor T4 is connected to the first node N1.

[0100] In some embodiments, the first voltage regulator sub-circuit SSC1 includes an eleventh transistor T11. The eleventh transistor T11 is connected between the second node N2 and the fifth node N5, and its gate is connected to the fourth power supply line VGL. Since the voltage supplied by the fourth power supply line VGL is the operating level voltage of the eleventh transistor T11, the eleventh transistor T11 can remain on continuously. Therefore, the second node N2 and the fifth node N5 can maintain the same voltage and operate essentially as the same node.

[0101] In some embodiments, a second voltage regulator subcircuit SSC2 is connected between the first node N1 and the output subcircuit OSC. The second voltage regulator subcircuit SSC2 is configured to limit the voltage drop width of the first node N1. Optionally, the second voltage regulator subcircuit SSC2 includes a twelfth transistor T12. The twelfth transistor T12 is connected between the first node N1 and the gate of the tenth transistor T10. The gate of the twelfth transistor T12 is connected to a fourth power supply line VGL, and the twelfth transistor T12 can remain on. Therefore, the gates of the first node N1 and the tenth transistor T10 can be maintained at the same voltage.

[0102] In some embodiments, each of the first to twelfth transistors T1 to T12 may be formed of a p-type transistor. In some embodiments, the operating voltage of the first to twelfth transistors T1 to T12 may be set to a low level voltage, and the non-operating voltage may be set to a high level voltage.

[0103] Figure 8A This is a partial schematic diagram of a display substrate provided in some embodiments of this disclosure. Figure 8A The diagram shows two first shift register units GOA1 and multiple signal transmission lines 60 and multiple drive signal lines in their respective areas. The drive signal lines provide drive signals to the first shift register units GOA1. For example, the multiple drive signal lines include: a third power supply line, a fourth power supply line, a first clock signal line, a second clock signal line, and a frame start signal line. At least one drive signal line can be configured on the same layer as the signal transmission lines 60. Figures 8A to 14 This explanation uses the example of the third power line and signal transmission line 60 being arranged on the same layer. Figure 9 for Figure 8A A schematic diagram of the middle semiconductor layer. Figure 10 for Figure 8A A schematic diagram of the first gate metal layer. Figure 11 for Figure 8A A schematic diagram of the second gate metal layer. Figure 12 for Figure 8A A schematic diagram of the first source / drain metal layer. Figure 13 for Figure 8A A schematic diagram of the second source / drain metal layer. Figure 14 for Figure 8A A schematic diagram of the via distribution.

[0104] like Figures 8A to 14 As shown, the semiconductor layer Poly includes: active layers T1_a to T12a of each transistor T1 to T12 and doped region patterns. The active layers and doped region patterns of each transistor in the same first pixel circuit are integrally formed. For the same transistor, doped region patterns are provided on both sides of the active layer, and the doped region patterns on both sides of the active layer can serve as the first and second electrodes of the transistor, respectively. Optionally, the active layers T9_a of the ninth transistor T9 and T10_a of the tenth transistor T10 are arranged along a first direction. The semiconductor layer Poly can be formed by patterning a semiconductor material, which can be an oxide semiconductor material, such as IGZO.

[0105] The first gate metal layer G1 is disposed on the side of the semiconductor layer away from the substrate 100. The first gate metal layer G1 may include, for example, metals, metal alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. For example, the first gate metal layer may include gold (Au), gold alloys, silver (Ag), silver alloys, aluminum (Al), aluminum alloys, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloys, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloys, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The first gate metal layer G1 may have a single layer or multiple layers.

[0106] like Figure 10 As shown, the first gate metal layer G1 includes: gates T1_g to T12_g of each transistor T1 to T12, the first plate of the first capacitor C1, the first plate of the second capacitor C2, and the first plate of the third capacitor C3. The gate of the fourth transistor T3 and the first plate C31 of the third capacitor C3 can be connected as a single structure. The gate T1_g of the first transistor T1 and the gate T3_g of the third transistor T3 can be connected as a single structure. The gate T2_g of the second transistor T2 and the gate T8_g of the eighth transistor T8 can be connected as a single structure. The gate T6_g of the sixth transistor T6 and the first plate C11 of the first capacitor C1 are formed as a single structure.

[0107] The second gate metal layer G2 is disposed on the side of the first gate metal layer away from the substrate 100, and the material of the second gate metal layer G2 may be selected from the materials of the first gate metal layer listed above. In some embodiments, such as Figure 10 As shown, the second gate metal layer G2 includes: a connection line 70, a second plate C12 of the first capacitor C1, a second plate C22 of the second capacitor C2, and a second plate C32 of the third capacitor C3. Each connection line 70 corresponds to a first shift register unit GOA1, and the first shift register unit GOA1 is connected to the corresponding second reset line RESET2 via the corresponding connection line 70.

[0108] Optionally, except for the last-stage first shift register unit GOA1, each of the remaining first shift register units GOA1 is also connected to the input terminal of the next-stage first shift register unit GOA1 via a corresponding connection line 70. The input terminal of each first shift register unit GOA1 can be the first terminal of the first transistor T1, and one end of the connection line is connected to the first terminal of the first transistor T1 through a via. For example, the connection line 70 includes a first portion 71 extending along a first direction and a second portion 72 extending along a second direction. One end of the second portion 72 is connected to the first terminal of the first transistor T1 through a via, and the other end of the second portion 72 is connected to one end of the second portion 72. The other end of the first portion 71 is connected to the corresponding second reset line RESET2. The first portion 71 and the second reset line RESET2 can be arranged on the same layer and electrically connected. It should be noted that the "electrical connection" in this embodiment can be a direct connection or an indirect connection.

[0109] In some embodiments, the second gate metal layer G2 further includes a clock signal adapter 80 for each stage of the first shift register unit GOA1.

[0110] like Figure 12 As shown, the first source / drain metal layer SD1 is located on the side of the second gate metal layer G2 away from the substrate 100. The first source / drain metal layer SD1 includes: multiple adapters, a fourth power line VGL, a first clock signal line CKL, a second clock signal line CBL, and a frame start signal line STV. The fourth power line VGL, the first clock signal line CKL, the second clock signal line CBL, and the frame start signal line STV all extend along a first direction. The multiple adapters include: a first adapter E1 to a sixteenth adapter E16.

[0111] There are multiple first adapters E1, and each first adapter E1 corresponds to a first shift register unit GOA1. Combined with... Figure 8A , Figure 12 , Figure 14 As shown, one end of each first adapter E1 is connected to the connecting line 70 via a first via V1, and the other end is connected to the signal transmission line 60 via a second via V2. In some examples, multiple first adapters E1 are arranged along a first direction.

[0112] There are multiple second adapters E2, each corresponding to a first shift register unit GOA1. One end of each second adapter E2 is connected to the signal transmission line 60 through a third via V3, and the other end is connected to the first reset line RESET1 through a fourth via V4. In some embodiments, the multiple second adapters E2 can be arranged along a first direction.

[0113] In some embodiments, the orthographic projections of the first via V1, the second via V2, the third via V3, and the fourth via V4 on the substrate 100 do not overlap with the orthographic projections of each transistor on the substrate 100, so as to prevent the transistors from being affected during the via fabrication process.

[0114] Combination Figure 8A , Figure 12 , Figure 14 As shown, the third adapter E3 is connected to the second terminal of the tenth transistor T10 through the fifth via V5, and to the second terminal of the ninth transistor T9 through the sixth via V6; in addition, the third connector E3 is also connected to the second part 72 of the connecting line 70 through the seventh via V7. The connection node between the second terminal of the ninth transistor T9, the second terminal of the tenth transistor T10, the third adapter E3 and the connecting line 70 can serve as the output terminal of the first shift register unit GOA1.

[0115] The fourth adapter E4 is connected to the first terminal of the tenth transistor T10 through the eighth via V8, and to the gate of the twelfth transistor T12 through the ninth via V9. It is also connected to the first terminal of the third transistor T3 through the tenth via V10. The gate of the twelfth transistor T12 is connected to the fourth power line VGL.

[0116] The fifth adapter E5 is connected to the first terminal of the ninth transistor T9 through the eleventh via V11, and to the second plate C22 of the second capacitor C2 through the twenty-seventh via V27, and to the first terminal of the fifth transistor T5 through the twelfth via V12.

[0117] The sixth adapter E6 is connected to the first plate C21 of the second capacitor C2 through the thirteenth via V13, and to the first terminal of the eighth transistor T8 through the fourteenth via V14. The seventh connector E7 is connected to the second terminal of the fourth transistor T4 through the fifteenth via V15, to the gate of the seventh transistor T7 through the sixteenth via V16, to the first terminal of the sixth transistor T6 through the forty-fifth via V45, and to the clock signal adapter cable 80 through the forty-second via V42.

[0118] The eighth adapter E8 is connected to the gate of the fourth transistor T4 through the seventeenth via V17, and to the second terminal of the twelfth transistor T12 through the eighteenth via V18.

[0119] The ninth adapter E9 is connected to the first terminal of the seventh transistor T7 through the nineteenth via V19, to the second terminal of the sixth transistor T6 through the twentieth via V20, and to the second plate C12 of the first capacitor C1 through the twenty-first via V21. The number of twenty-first vias V21 can be one or more; for example, two twenty-first vias V21 can be used to improve connection stability.

[0120] The tenth adapter E10 is connected to the second plate C32 of the third capacitor C3 through the twenty-second via V22, to the second terminal of the fourth transistor T4 through the twenty-third via V23, and to the second terminal of the fifth transistor T5 through the twenty-fourth via V24.

[0121] The eleventh adapter E11 is connected to the first terminal of the twelfth transistor T12 through the twenty-fifth via V25, and to the gate of the eighth transistor T8 through the twenty-sixth via V26.

[0122] The twelfth adapter E12 is connected to the second terminal of the third transistor T3 through the twenty-eighth via V28, to the gate of the fifth transistor T5 through the twenty-ninth via V29, and to the first terminal of the eleventh transistor T11 through the thirtieth via V30.

[0123] The thirteenth adapter E13 is connected to the gate of the third transistor T3 through the thirty-first via V31, and to the second terminal of the second transistor T2 through the thirty-second via V32.

[0124] The fourteenth adapter E14 is connected to the gate of the second transistor T2 through the thirty-third via V33, and to the second terminal of the first transistor T1 through the thirty-fourth via V34.

[0125] The fifteenth adapter E15 is connected to the first terminal of the first transistor T1 through the thirty-fifth via V35. In addition, each stage of the first shift register unit GOA1 corresponds to a fifteenth adapter E15. The fifteenth adapter E15 corresponding to the first stage of the first shift register unit GOA1 can be connected to the frame start signal line STV. Except for the first stage, the fifteenth adapter E15 corresponding to the other first shift register units GOA1 are also connected to the connection line 70 corresponding to the previous stage first shift register unit GOA1 through the thirty-sixth via V36.

[0126] The sixteenth adapter E16 is connected to the second terminal of the eleventh transistor T11 through the thirty-seventh via V37, and to the gate of the sixth transistor T6 through the thirty-eighth via V38.

[0127] The first clock signal line CKL is connected to the gate of the third transistor T3 in the odd-level first shift register unit GOA1 via via V48, and to the clock signal adapter line 80 in the even-level first shift register unit GOA1 via via V49. The second clock signal line CBL is connected to the gate of the third transistor T3 in the even-level first shift register unit GOA1 via via V50, and to the clock signal adapter line 80 in the odd-level first shift register unit GOA1 via via V51. The clock signal adapter line 80 of each first shift register unit GOA1 is used to connect to the seventh adapter E7. The number of vias V48 to V50 can be one or more; for example, two vias V48 to V50 can be used to improve connection stability.

[0128] The fourth power line VGL is connected to the gate of the twelfth transistor T12 through the fortieth via V40, and to the gate of the eleventh transistor T11 through the fortieth via V41. There can be one or more fortieth vias V40 and V41; for example, there can be two fortieth vias V40 and two fortieth vias V41, thereby improving connection stability.

[0129] In some examples, the first clock signal line CKL is located on the side of the fourth power line VGL away from the display area, the second clock signal line CBL is located on the side of the first clock signal line CKL away from the display area, and the frame start signal line STV is located on the side of the second clock signal line CBL away from the display area.

[0130] In one example, the orthographic projections of the first clock signal line CLK, the second clock signal line CBL, the frame start signal line STV, and the fourth power supply line VGL on the substrate 100 do not overlap with the orthographic projections of the active layers of each transistor in the first shift register unit GOA1 on the substrate 100.

[0131] In some embodiments, the second source / drain metal layer SD2 includes multiple signal transmission lines 60 and a third power line VGH. The third power line VGH extends along a first direction. For example, the orthographic projection of the third power line VGH on the substrate 100 may overlap with the orthographic projections of the third capacitor C3, the fourth transistor T4, and the eighth transistor T8 on the substrate 100. The third power line VGH can be connected to the fifth adapter E5 through a thirty-ninth via V39. To improve connection stability, each fifth adapter E5 can be connected to the third power line VGH through multiple thirty-ninth vias V39.

[0132] Figure 8B This is a partial schematic diagram of the region where the first-stage shift register unit is located, as provided in some embodiments of this disclosure. Figure 8BThe diagram shows a partial structure of the first-stage shift register unit, including the first clock signal line CKL, the second clock signal line CBL, the frame start signal line STV, the third power supply line VGH, and the fourth power supply line VGL. As described above, each first-stage shift register unit GOA corresponds to a fifteenth adapter E15. The fifteenth adapter E15 is connected to the first terminal of the first transistor T1 via a thirty-fifth via V35. The E15 corresponding to the first-stage shift register unit GOA is also connected to one end of the frame start signal adapter line 90 via a via. The other end of the frame start signal adapter line 90 is connected to the frame start signal line STV via a via. The frame start signal adapter line 90 is located in the second gate metal layer G2, but it can also be located in the first gate metal layer G1.

[0133] Combination Figures 8A to 12 As shown, signal transmission line 60 has a start end and a stop end. The start end of signal transmission line 60 is connected to the first adapter E1 through the second via V2, thereby connecting to the output terminal of the first shift register unit GOA1 through the first adapter E1. The stop end of signal transmission line 60 is connected to the second adapter E2 through the fourth via V4, thereby connecting to the second reset line RESET2 through the second adapter E2. The orthographic projection of signal transmission line 60 on the substrate 100 overlaps with the orthographic projection of at least one output transistor of at least one first shift register unit GOA1 on the substrate 100. For example, in Figure 7 The first shift register unit GOA1 shown includes two output transistors, namely the ninth transistor T9 and the tenth transistor T10. At this time, the orthographic projection of each signal transmission line 60 can overlap with the orthographic projection of at least one of the ninth transistors T9 and the tenth transistor T10 of the first shift register unit GOA1.

[0134] In some embodiments, the orthographic projection of each signal transmission line 60 on the substrate 100 overlaps with the orthographic projections of the M-1 first shift register units GOA1 on the substrate 100. For example, the orthographic projection of each signal transmission line 60 on the substrate 100 overlaps with the orthographic projections of the ninth transistor T9 and the tenth transistor T10 of the M-1 first shift register units GOA1 on the substrate 100.

[0135] like Figure 8A As shown, the orthographic projection of the signal transmission line 60 on the substrate 100 does not overlap with the orthographic projection of the storage capacitors (such as the first capacitor C1, the second capacitor C2, and the third capacitor C3 mentioned above) on the substrate 100, so as to prevent parasitic capacitance from being generated between the signal transmission line 60 and the storage capacitor, which would cause signal interference between the storage capacitor and the signal transmission line 60.

[0136] like Figure 13As shown, the signal transmission line 60 has a bent structure, comprising multiple transmission segments 61 and connecting segments 62 located between adjacent transmission segments 61. The transmission segments 61 extend along a first direction. The signal transmission line 60 has a starting end and a ending end. The starting end is connected to the output of the first shift register unit GOA1, and the ending end is connected to the first reset line RESET1. The signal transmission line 60 is located on the side of the third power line VGH closest to the display area (for...). Figure 13 In this context, the display area is located to the left of the signal transmission line 60. For two adjacent transmission segments 61 within the same signal transmission line 60, the distance from the transmission segment 61 closer to the beginning to the display area is greater than the distance from the transmission segment 61 farther from the beginning to the display area. The orthographic projection of the signal transmission line 60 onto the substrate 100 lies between the display area and the orthographic projection of the storage capacitor onto the substrate 100. From the beginning to the end of the signal transmission line 60, the signal transmission line 60 bends multiple times towards the display area, thereby reducing the width of the area occupied by multiple signal transmission lines 60.

[0137] Among them, such as Figure 13 As shown, the connecting segment 62 is a straight line segment, and an obtuse angle is formed between the connecting segment 62 and the adjacent transmission segment 61. This obtuse angle can be between 95° and 160°, for example, 95°, 100°, 120°, 145°, 150°, or 160°. Of course, in other embodiments, the connecting segment 62 can also be an arc segment, thereby forming a rounded corner structure with the adjacent transmission segment 61.

[0138] like Figure 13 As shown, the connecting segments 62 in the signal transmission lines 60 to which multiple first shift register units GOA1 are connected are divided into multiple first segment groups 62g. These multiple first segment groups 62g are arranged along a first direction. At least some of the first segment groups 62g include M-1 connecting segments 62. In some examples, the center line connecting these M-1 connecting segments 62 is a straight line, and the extension direction of the center line intersects both the first and second directions. Of course, in other examples, the center lines connecting the M-1 connecting segments 62 may not be on the same straight line.

[0139] like Figure 13 As shown, the center line connecting the M-1 connecting segments 62 is a straight line, and the center line and the connecting segment 62 are inclined in different directions. For example, as Figure 13 In the middle, the center line connecting the M-1 connecting segments 62 adopts the slant of "\", and the connecting segment 62 adopts the slant of " / ".

[0140] like Figure 13As shown, in the first segment group 62g with M-1 connecting segments 62, the lengths of each connecting segment 62 are the same, or at least two connecting segments 62 have different lengths.

[0141] Optionally, the slant of the connecting line segment 62 in the corresponding areas of two adjacent first shift register units may differ. For example, the connecting line segment 62 of the signal transmission line 60 corresponding to the output terminal of the first first shift register unit GOA1_1 may use a slant of "\"; while the connecting line segment 62 of the signal transmission line 60 corresponding to the output terminal of the second first shift register unit GOA1_2 may use a slant of " / ".

[0142] like Figure 8A and Figure 13 As shown, in the first line segment group 62g, the orthographic projection of at least one connecting line segment 62 on the substrate 100 overlaps with the orthographic projection of the tenth transistor T10 on the substrate 100.

[0143] like Figure 13 As shown, the transmission line segments 61 in the signal transmission lines 60 connected to the multiple first shift register units GOA1 are divided into multiple second line segment groups 61g. The multiple second line segment groups 61g are arranged along the second direction. Each second line segment group 61g includes multiple transmission line segments 61 arranged along the first direction. The multiple transmission line segments 61 in the same second line segment group 61g are located on the same straight line.

[0144] like Figure 13 As shown, the transmission line segments 61 in the signal transmission lines 60 connected to the multiple first shift register units GOA1 are divided into multiple second segment groups 61g. The multiple second segment groups 61g are arranged along the second direction. Each second segment group 61g includes multiple transmission line segments 61 arranged along the first direction. The multiple transmission line segments 61 in the same second segment group are located on the same straight line, thereby making the area width occupied by the multiple signal transmission lines 60 as a whole smaller.

[0145] Optionally, each of the transmission segments 61 in the second segment group 61g is connected to a different shift register unit.

[0146] Among them, the distance between any two adjacent second line segment groups 61g is equal.

[0147] In one example, the widths of transmission segment 61 and connecting segment 62 can be approximately the same. "Approximately the same" in this embodiment means that the difference between the two values ​​is less than 10%, or 5%, or they are exactly equal. The distance between two adjacent second segment groups 61g can be less than 1.5 times the width of transmission segment 61. In one example, the width of transmission segment 61 and the distance between two adjacent second segment groups 61g are both less than or equal to 10 μm. For example, the width of transmission segment 61 and the distance between two adjacent second segment groups 61g are both 3 μm, or 5 μm, or 7 μm, or 9 μm, or 10 μm.

[0148] exist Figures 8A to 14 In the illustrated embodiment, the orthographic projections of the drive signal lines and signal transmission lines 60 on the substrate 100 do not overlap. The orthographic projections of the drive signal lines, such as the fourth power line VGL, the first clock signal line CK, and the second clock signal line CB, on the substrate 100 do not overlap with the orthographic projections of the active layers of the transistors in the first shift register unit GOA1 on the substrate 100. However, in other embodiments, the orthographic projection of at least one drive signal line on the substrate 100 overlaps with the active layer of the transistors in the first shift register unit GOA1. The drive signal lines that overlap with the active layers of the transistors in the first shift register unit GOA1 are disposed in the same layer as the signal transmission lines 60, and are all located in the second source-drain metal layer SD2.

[0149] Figure 15 Plan views of the first shift register unit and signal lines provided in other embodiments of this disclosure, such as... Figure 15 As shown, the orthographic projections of the first clock signal line CKL, the second clock signal line CBL, and the frame start signal line STV on the substrate 100 all overlap with the orthographic projections of the active layers of the transistors in the first shift register unit GOA1 on the substrate 100. For example, the orthographic projection of the first clock signal line CKL on the substrate 100 overlaps with the orthographic projections of the active layers of the second transistor T2 and the third transistor T3 on the substrate 100. The orthographic projection of the second clock signal line CBL on the substrate 100 overlaps with the orthographic projection of the active layer of the first transistor T1 on the substrate 100.

[0150] exist Figure 15 In the illustrated embodiment, the orthographic projections of the drive signal line and the signal transmission line 60 on the substrate 100 do not overlap. The fourth power line VGL is located in the first source-drain metal layer. The first clock signal line CKL, the second clock signal line CBL, the frame start signal line STV, and the third power line VGH are all disposed in the same layer as the signal transmission line 60, and are all located in the second source-drain metal layer. However, the orthographic projection of the frame start signal line STV on the substrate may overlap with the orthographic projection of the fourth power line VGL on the substrate.

[0151] like Figure 15 As shown, the first clock signal line CKL is located on the side of the third power line VGH that is furthest from the display area, the second clock signal line CBL is located on the side of the first clock signal line CKL that is furthest from the display area, and the frame start signal line STV is located on the side of the second clock signal line CBL that is furthest from the display area.

[0152] It should be noted that, Figure 15 The example described uses the first clock signal line CKL, the second clock signal line CBL, the frame start signal line STV, and the third power line VGH arranged on the same layer. In other embodiments, the first clock signal line CKL, the second clock signal line CBL, the frame start signal line STV, and the third power line VGH may be arranged on different layers, for example, on two or more layers. Alternatively, the signal transmission line 60 and any one of the drive signal lines may be arranged on different layers. For example, the third power line may be arranged in the first source-drain metal layer, the signal transmission line 60 in the second source-drain metal layer, and the first clock signal line CKL, the second clock signal line CBL, the frame start signal line STV, and the third power line VGH on the side of the second source-drain metal layer away from the substrate 100.

[0153] In some embodiments, such as Figure 15 As shown, when the first clock signal line CKL, the second clock signal line CBL, the frame start signal line STV, and the third power line VGH are arranged on the same layer, the first clock signal line CKL is connected to the thirteenth adapter E13 of the odd-level first shift register unit GOA1 through the forty-third via V43, and the second clock signal line is connected to the thirteenth adapter E13 of the even-level first shift register unit GOA1 through the forty-fourth via V44. Additionally, in Figure 15 In the embodiment shown, no clock signal connector is required in the second gate metal layer. In this case, the first clock signal line CKL is directly connected to the seventh adapter E7 of the odd-level first shift register unit GOA1 through a via, and the second clock signal line CBL is directly connected to the seventh adapter E7 of the even-level first shift register unit GOA1 through a via.

[0154] In some embodiments, when the frame start signal line STV is located in the second source-drain metal layer, the frame start signal line STV can have orthographic overlap with the first terminal of the first transistor T1 in the first-stage first shift register unit GOA. In this case, the frame start signal STV can be directly connected to the first terminal of the first transistor T1 in the first-stage shift register unit GOA through a via, without the need for setting... Figure 8B The frame start signal adapter cable 90 in the middle.

[0155] It should be noted that the display substrate also includes multiple insulating layers disposed on the substrate 100. These insulating layers include, for example, a first gate insulating layer, a second gate insulating layer, an interlayer dielectric layer, and a passivation layer. Specifically, the first gate insulating layer is disposed between the semiconductor layer Poly and the first gate metal layer G1; the second gate insulating layer is disposed between the first and second gate metal layers; the interlayer dielectric layer is disposed between the second gate metal layer and the first source / drain metal layer; and the passivation layer is disposed between the first and second source / drain metal layers. In this embodiment, when two conductive structures are connected via a via, the via penetrates the insulating layer between the two conductive structures.

[0156] Furthermore, in this embodiment, the transistors in the first shift register unit and the transistors in the pixel circuit can have the same structure and be disposed on the same layer. For example, the gates of the transistors in the first shift register unit and the gates of the transistors in the pixel circuit can be disposed on the same layer, and the active layers of the transistors in the first shift register unit and the active layers of the transistors in the pixel circuit can be disposed on the same layer. In addition, in some examples, a planarization layer can be disposed on the side of the second source / drain metal layer SD2 away from the substrate 100, and the light-emitting devices in the display area are disposed on the side of the planarization layer away from the substrate.

[0157] In some examples, the materials for the first gate insulating layer, the second gate insulating layer, the interlayer dielectric layer, and the passivation layer can all be selected from: silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The first gate insulating layer, the second gate insulating layer, the interlayer dielectric layer, and the passivation layer can all be formed as a single layer or multiple layers. The material of the planarization layer can include organic materials.

[0158] Figure 16 This is a partial schematic diagram of the surrounding area provided in some other embodiments of this disclosure, in conjunction with... Figure 5 and Figure 16 As shown, the display substrate further includes: multiple scan lines GL disposed on the substrate 100 and a second driving circuit 40. At least a portion of the scan lines GL are located in the display area AA, and the second driving circuit 40 is located in the peripheral area NA. Each row of pixel areas corresponds to one scan line GL. The second driving circuit 40 includes multiple cascaded second shift register units GOA2. The output of each second shift register unit GOA2 is connected to one scan line GL to provide a scan signal for the scan line GL. The second driving circuit 40 may be located on the side of the first driving circuit 30 closer to the display area AA.

[0159] The second driving circuit 40 can be disposed on one side of the display area AA, or on both opposite sides of the display area AA. The structure of the second shift register unit GOA2 is similar to that of the first shift register unit GOA1, both including multiple transistors and storage capacitors. The first driving circuit 30 is located on the side of the second driving circuit 40 away from the display area AA. Of course, in other embodiments, the first driving circuit 30 can also be located on the side of the second driving circuit 40 closer to the display area AA.

[0160] The display substrate also includes a second power line VSS, which provides an electrical signal to the second electrode of the light-emitting device 20 in the display area AA. The orthographic projection of the second power line VSS onto the substrate 100 overlaps with the orthographic projection of the second shift register unit GOA2 onto the substrate 100, thereby reducing the width of the bezels on both sides of the display area AA.

[0161] like Figure 16 As shown, the second power line VSS has multiple cutouts Va to reduce the parasitic capacitance between the second power line VSS and the conductive structures in the second shift register unit GOA2. The conductive structures in the second shift register unit GOA2 may include the first terminal, second terminal, and gate of each transistor in the second shift register unit GOA2, as well as the two plates of the storage capacitor. The shape of the cutouts Va is not limited; for example, it can be rectangular, circular, triangular, elliptical, or other shapes.

[0162] In some embodiments, the second power line VSS can be disposed on the same layer as the signal transmission line 60, thereby enabling the second power line VSS and the signal transmission line 60 to be fabricated simultaneously, simplifying the fabrication process. Additionally, the first clock signal line CKL, the second clock signal line CBL, and the frame start signal line STV are also disposed on the same layer as the signal transmission line 60, further simplifying the fabrication process.

[0163] It should be noted that the second power line VSS may also be located on a different layer from the signal transmission line 60. For example, the second power line VSS may be located on the side of the layer where the signal transmission line 60 is located that is away from the substrate 100.

[0164] Optionally, the second power line VSS is located on the side of the layer containing the signal transmission line 60 away from the substrate 100, and the second power line VSS at least partially overlaps with the signal transmission line 60. For example, the second power line VSS is made of the same conductive layer as the first electrode (e.g., anode) of the light-emitting device 20 in the display area AA.

[0165] In some embodiments, the display substrate further includes a first signal adapter cable 81, a second signal adapter cable 82, a third signal adapter cable 83, and a fourth signal adapter cable 84 disposed in the peripheral area.

[0166] Signal transmission line 60 can be connected to the first end of the first signal adapter line 81. The second end of the first signal adapter line 81 is connected to the first end of the second signal adapter line 82, and the second end of the second signal adapter line 82 is connected to the first reset line RESET1. The connection line connecting the ninth transistor T9 and the tenth transistor T10 can be connected to the first end of the third signal adapter line 83. The second end of the third signal adapter line 83 is connected to the first end of the fourth signal adapter line 84, and the second end of the fourth signal adapter line 84 is connected to the second reset line RESET2. The output end of the second shift register unit is connected to the first end of the fifth signal adapter line 85. The second end of the fifth signal adapter line 85 is connected to the first end of the sixth signal adapter line 86, and the second end of the sixth signal adapter line 86 is connected to the scan line.

[0167] Among them, the first reset line RESET1 and the second reset line RESET2 can both be located in the first gate metal layer, the first signal adapter line 81, the third signal adapter line 83 and the fifth signal adapter line 85 can all be located in the second gate metal layer, and the second signal adapter line 82, the fourth signal adapter line 84 and the sixth signal adapter line 86 can all be located in the first source-drain metal layer.

[0168] In addition, in the embodiments disclosed herein, such as Figure 5 As shown, the display substrate also includes a third driving circuit 50 and multiple light-emitting control lines EM. The third driving circuit 50 is located in the peripheral area NA and includes multiple cascaded third shift register units GOA3. At least a portion of the light-emitting control lines EM are located in the display area AA, and each third shift register unit GOA3 is connected to one light-emitting control line EM.

[0169] This disclosure also provides a method for manufacturing the above-described display substrate. The display substrate has a display area and a peripheral area, wherein the display area includes N rows of pixels arranged along a first direction. The method for manufacturing the display substrate includes:

[0170] S1. Multiple first reset lines and multiple second reset lines are formed on the substrate, with each row of the pixel area corresponding to one first reset line and one second reset line.

[0171] S2. N+M first shift register units are formed on the substrate at positions corresponding to the peripheral area; wherein, the N+M first shift register units are arranged along the first direction, the output terminal of the i-th first shift register unit is connected to the second reset line corresponding to the iM-th row of pixels; the output terminal of the j-th first shift register is connected to the first reset line corresponding to the j-th row of pixels through a signal transmission line; N is an integer greater than 2, M is a preset positive integer, M+1≤i≤N+M, 1≤j≤N, and i and j are both integers.

[0172] Wherein, the orthographic projection of the signal transmission line on the substrate overlaps with the orthographic projection of at least one of the first shift register units on the substrate.

[0173] The first reset line and the second reset line can be located in the first gate metal layer, and they can be fabricated synchronously with a portion of the structure in the first shift register unit. For example, the first reset line and the second reset line can be fabricated synchronously with the gates of each transistor in the first shift register unit.

[0174] In some embodiments, the fabrication method further includes: forming a plurality of driving signal lines, the plurality of driving signal lines being used to provide signals to the plurality of first shift register units, wherein the orthographic projection of at least one of the plurality of driving signal lines on the substrate overlaps with the orthographic projection of the plurality of first shift register units on the substrate. At least one of the driving signal lines is formed synchronously with the signal transmission line.

[0175] For example, multiple drive signal lines include: a first clock signal line, a second clock signal line, a frame start signal line, a third power signal line, and a fourth power signal line. In some embodiments, the third power line, the first clock signal line, the second clock signal line, and the frame start signal line are formed synchronously with the signal transmission lines. In other embodiments, the third power line is formed synchronously with the signal transmission lines.

[0176] This disclosure also provides a display device, including the display substrate described in the above embodiments. The display device can be any product or component with display functionality, such as electronic paper, OLED panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0177] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display substrate having a display area and a peripheral area, the display area comprising N pixel groups arranged along a first direction, each pixel group comprising at least one row of pixel areas, the display substrate comprising: Substrate; Multiple first reset lines and multiple second reset lines are disposed on the substrate, with each row of pixel area corresponding to one first reset line and one second reset line; N+M first shift register units are disposed on the substrate and located in the peripheral area. The N+M first shift register units are arranged along the first direction. The output terminal of the i-th first shift register unit is connected to the second reset line corresponding to the iM-th row of pixels. The output terminal of the j-th first shift register is connected to the first reset line corresponding to the j-th row of pixels through a signal transmission line. N is an integer greater than 2, M is a preset positive integer, M+1≤i≤N+M, 1≤j≤N, and i and j are both integers. Wherein, the orthographic projection of the signal transmission line on the substrate overlaps with the orthographic projection of at least one of the first shift register units on the substrate.

2. The display substrate according to claim 1, wherein, The first shift register unit includes an output transistor connected to the output terminal of the first shift register unit, and the orthographic projection of the signal transmission line on the substrate overlaps with the orthographic projection of the output transistor of at least one of the first shift register units on the substrate.

3. The display substrate according to claim 1, wherein, The orthographic projection of each of the signal transmission lines on the substrate overlaps with the orthographic projection of the M-1 first shift register units on the substrate.

4. The display substrate according to any one of claims 1 to 3, wherein, The first shift register unit includes a storage capacitor, and the orthographic projection of the signal transmission line on the substrate does not overlap with the orthographic projection of the storage capacitor on the substrate.

5. The display substrate according to any one of claims 1 to 3, wherein, The signal transmission line includes multiple transmission line segments and a connecting line segment located between two adjacent transmission line segments, and the transmission line segments extend along the first direction; The signal transmission line has a start end and a tail end. The start end is connected to the output end of the first shift register unit, and the tail end is connected to the first reset line. For two adjacent transmission segments in the same signal transmission line, the distance from the transmission segment closer to the start end to the display area is greater than the distance from the transmission segment farther from the start end to the display area.

6. The display substrate according to claim 5, wherein, The connecting line segment is a straight line segment, and the connecting line segment forms an obtuse angle with the adjacent transmission line segment.

7. The display substrate according to claim 5, wherein, The connecting segments in the signal transmission lines to which the multiple first shift register units are connected are divided into multiple first segment groups, which are arranged along the first direction. At least one first segment group includes M-1 connecting segments. Wherein, the center line connecting the M-1 connecting segments is a straight line, and the extension direction of the center line intersects the first direction and the extension direction of the first reset line; Alternatively, the centers of the M-1 connecting segments are not on the same straight line.

8. The display substrate according to claim 7, wherein, The center line connecting the M-1 connecting segments is a straight line, and the center line and the connecting segments are inclined in different directions.

9. The display substrate according to claim 7, wherein, In the M-1 connecting segments, each connecting segment has the same length; Alternatively, at least two connecting segments have different lengths.

10. The display substrate according to claim 5, wherein, The transmission line segments in the signal transmission lines connected to the plurality of first shift register units are divided into a plurality of second line segment groups, the plurality of second line segment groups are arranged along a second direction, each second line segment group includes a plurality of transmission line segments arranged along the first direction, and the plurality of transmission line segments in the same second line segment group are located on the same straight line.

11. The display substrate according to claim 10, wherein, The distance between any two adjacent second line segment groups is equal.

12. The display substrate according to any one of claims 1 to 3, wherein, The display substrate further includes: Multiple scan lines, with one scan line corresponding to each row of pixel areas; A plurality of second shift register units are located in the peripheral area, and the output of each second shift register unit is connected to one of the scan lines; The power line has an orthographic projection on the substrate that overlaps with the orthographic projection of the second shift register unit on the substrate.

13. The display substrate according to claim 12, wherein, Multiple second shift register units are located on the side of multiple first shift register units closer to the display area.

14. The display substrate according to any one of claims 1 to 3, wherein, The display substrate further includes: Multiple drive signal lines are provided to provide signals to multiple first shift register units, and at least one of the multiple drive signal lines has an orthographic projection on the substrate that overlaps with the orthographic projection of the multiple first shift register units on the substrate.

15. The display substrate according to claim 14, wherein, The driving signal line and the signal transmission line do not overlap in their orthogonal projections on the substrate.

16. The display substrate according to claim 14, wherein, At least one of the drive signal lines is disposed on the same layer as the signal transmission line.

17. The display substrate according to any one of claims 1 to 3, wherein, The display substrate further includes: Multiple connection lines, each connection line corresponding to one first shift register unit, the first shift register unit being connected to the second reset line through the corresponding connection line; except for the last stage first shift register unit, each of the remaining first shift register units is also connected to the input terminal of the next stage first shift register unit through the connection line; Multiple first adapters are provided, each first adapter corresponding to one signal transmission line. One end of the first adapter is connected to the connection line through a first via, and the other end is connected to the signal transmission line through a second via.

18. The display substrate according to claim 17, wherein, The first shift register unit includes a plurality of transistors, and the orthogonal projections of the first via and the second via on the substrate do not overlap with the orthogonal projections of the transistors on the substrate.

19. The display substrate according to claim 17, wherein, Multiple first adapters are arranged along the first direction.

20. The display substrate according to claim 17, wherein, The connecting line is disposed on the same layer as the second reset line and is electrically connected.

21. The display substrate according to claim 17, wherein, The signal transmission line is located on the side of the layer containing the first adapter that is away from the substrate.

22. The display substrate according to any one of claims 1 to 3, wherein, The display substrate further includes: The second adapter has one end connected to the signal transmission line through a third via, and the other end connected to the first reset line through a fourth via. The first shift register unit includes multiple transistors, and the orthogonal projections of the third via and the fourth via on the substrate do not overlap with the orthogonal projections of the transistors on the substrate.

23. The display substrate according to claim 22, wherein, The number of the second adapters is multiple, and the multiple second adapters are arranged along the first direction.

24. A display device, wherein, The display substrate includes any one of claims 1 to 23.

25. A method for manufacturing a display substrate, the display substrate having a display area and a peripheral area, the display area comprising N rows of pixel areas arranged along a first direction, wherein... The manufacturing method includes: Multiple first reset lines and multiple second reset lines are formed on the substrate, and each row of the pixel area corresponds to one first reset line and one second reset line; N+M first shift register units are formed on the substrate at positions corresponding to the peripheral region; wherein, the N+M first shift register units are arranged along the first direction, the output terminal of the i-th first shift register unit is connected to the second reset line corresponding to the iM-th row of pixels; the output terminal of the j-th first shift register is connected to the first reset line corresponding to the j-th row of pixels through a signal transmission line; N is an integer greater than 2, M is a preset positive integer, M+1≤i≤N+M, 1≤j≤N, and i and j are both integers; Wherein, the orthographic projection of the signal transmission line on the substrate overlaps with the orthographic projection of at least one of the first shift register units on the substrate.

26. The manufacturing method according to claim 25, wherein, The manufacturing method further includes: Multiple drive signal lines are formed, which are used to provide signals to multiple first shift register units. At least one of the multiple drive signal lines has an orthographic projection on the substrate that overlaps with the orthographic projection of the multiple first shift register units on the substrate. At least one of the drive signal lines is formed synchronously with the signal transmission line.

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