Semiconductor structure and method of fabricating the same

Abstract

The present disclosure relates to a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a substrate; a first contact layer disposed on the substrate; a gate structure disposed on the first contact layer; an isolation layer disposed on the gate structure; a conductive channel disposed on the first contact layer through the isolation layer and the gate structure; an insulating layer disposed on the inner side of the conductive channel; an etching stop layer located between the conductive channel and the insulating layer, the height of the etching stop layer is different from the height of the insulating layer in the direction perpendicular to the substrate; a second contact layer disposed on the etching stop layer and the insulating layer and connected with the conductive channel, the structure and performance of the semiconductor structure are complete, which is conducive to improving the yield of products, and is suitable for the development demand of semiconductor structure to smaller feature size.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the development of semiconductor technology, integrated circuits are moving towards miniaturization, which requires higher integration density and smaller feature size. This means that as many semiconductor devices as possible should be placed on a smaller substrate to achieve higher performance.

[0003] However, the miniaturization of semiconductor devices has almost reached its limit. The miniaturization of semiconductor devices increases the difficulty of manufacturing processes and may affect the performance and product yield of semiconductor devices. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a semiconductor structure, including:

[0006] Substrate;

[0007] A first contact layer is disposed on the substrate;

[0008] A gate structure is disposed on the first contact layer;

[0009] An isolation layer is disposed on the gate structure;

[0010] A conductive channel penetrates the isolation layer, and the gate structure is disposed on the first contact layer;

[0011] An insulating layer is disposed on the inner side of the conductive channel;

[0012] An etch stop layer is located between the conductive channel and the insulating layer, and in a direction perpendicular to the substrate, the height of the etch stop layer is different from the height of the insulating layer;

[0013] The second contact layer is disposed on the etch stop layer and the insulating layer, and is connected to the conductive channel.

[0014] Optionally, the top surface of the etch stop layer and the top surface of the insulating layer are lower than the top surface of the conductive channel, and the top surface of the insulating layer is not lower than the top surface of the gate structure;

[0015] The bottom wall of the insulating layer and at least a portion of the sidewalls of the insulating layer are in contact with the etch stop layer; the second contact layer is disposed inside the conductive channel.

[0016] Optionally, the etch rate of the etch stop layer is different from the etch rate of the insulating layer.

[0017] Optionally, the interface between the top surface of the etch stop layer and the top surface of the insulating layer has a recess, and a portion of the second contact layer is disposed in the recess.

[0018] Optionally, the top surface of the etch stop layer is lower than the top surface of the insulating layer, and the recess is provided on the etch stop layer.

[0019] Optionally, the top surface of the insulating layer is lower than the top surface of the etch stop layer, and the recess is provided on the insulating layer.

[0020] Optionally, the etch rate of the etch stop layer is less than the etch rate of the insulating layer.

[0021] Secondly, methods for fabricating semiconductor structures include:

[0022] Provide substrate;

[0023] A first contact layer, a gate structure, an isolation layer, and a channel material layer are formed. The first contact layer is disposed on the substrate, the gate structure is disposed on the first contact layer, the isolation layer is disposed on the gate structure, the channel material layer covers the isolation layer and forms a conductive channel, the conductive channel penetrates the isolation layer, and the gate structure is disposed on the first contact layer.

[0024] An etch stop layer is formed, covering the conductive channel and the isolation layer;

[0025] An insulating layer is formed to cover the etch stop layer and fill the conductive channel, wherein the etch rate of the insulating layer is different from that of the etch stop layer;

[0026] The insulating layer is ground using the etching stop layer as a stop layer;

[0027] The etch stop layer and the insulating layer are etched into the conductive channel, and the height of the etch stop layer is different from the height of the insulating layer in the direction perpendicular to the substrate;

[0028] A second contact layer is formed on the etch stop layer and the insulating layer, and is connected to the conductive channel.

[0029] Optionally, after etching the etch stop layer and the insulating layer into the conductive channel, the top surface of the etch stop layer and the top surface of the insulating layer are lower than the top surface of the conductive channel, and the top surface of the insulating layer is not lower than the top surface of the gate structure.

[0030] Optionally, the etch rate of the etch stop layer is less than the etch rate of the insulating layer;

[0031] After the etch stop layer and the insulating layer are etched into the conductive channel, the top surface of the etch stop layer and the top surface of the insulating layer are at different heights. The connection surface between the top surface of the etch stop layer and the top surface of the insulating layer has a recess, and a portion of the second contact layer is disposed in the recess.

[0032] Optionally, the etch rate of the etch stop layer is less than the etch rate of the insulating layer;

[0033] After the etch stop layer and the insulating layer are etched into the conductive channel, the top surface of the etch stop layer is lower than the top surface of the insulating layer, and the recess is provided on the etch stop layer.

[0034] Optionally, after etching the etch stop layer and the insulating layer into the conductive channel, the top surface of the insulating layer is lower than the top surface of the etch stop layer, and the recess is provided on the insulating layer.

[0035] Optionally, the manufacturing method further includes:

[0036] The channel material layer is etched to expose the top surface of the isolation layer, and the channel material layer located in the channel trench forms the conductive channel.

[0037] The semiconductor structure and fabrication method disclosed herein have the following beneficial effects:

[0038] The semiconductor structure disclosed herein adds an etch stop layer between the insulating layer and the inner wall of the conductive channel. The etch stop layer is made of a different material than the insulating layer. During the fabrication of the semiconductor structure, the etch stop layer can protect the isolation layer, preventing damage to the isolation layer during the removal of the insulating layer above the conductive channel, thus avoiding problems such as short circuits between devices. This ensures the structural and performance integrity of the semiconductor structure, which is beneficial for improving product yield and is suitable for the development needs of semiconductor structures towards smaller feature sizes.

[0039] The semiconductor structure fabrication method disclosed herein forms an etch stop layer before filling the conductive channel with an insulating layer. The etch stop layer covers the inner wall surface of the conductive channel and the top surface of the isolation layer, thus protecting the isolation layer. This process avoids damage to the isolation layer and exposure of the gate structure during the grinding process that removes the insulating layer from the top surface of the conductive channel. It also prevents the second contact layer formed by subsequently filling conductive material from short-circuiting with the gate structure, ensuring the structural and performance integrity of the formed semiconductor structure. This method is beneficial for improving product yield and is suitable for the development needs of semiconductor structures towards smaller feature sizes. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of a semiconductor structure provided in one embodiment;

[0042] Figure 2 for Figure 1 A cross-sectional view of the semiconductor structure along line AA;

[0043] Figure 3 for Figure 1 A schematic diagram of the insulating layer and etch stop layer in a semiconductor structure;

[0044] Figure 4 This is a schematic diagram of a semiconductor structure provided in one embodiment;

[0045] Figure 5 for Figure 4 A cross-sectional view of the semiconductor structure along line AA;

[0046] Figure 6 for Figure 4 A schematic diagram of the insulating layer and etch stop layer in a semiconductor structure;

[0047] Figure 7 A process flow diagram of a method for fabricating a semiconductor structure according to one embodiment;

[0048] Figure 8 A schematic diagram of the structure after a channel material layer is formed in a channel trench, provided as an embodiment of a method for fabricating a semiconductor structure;

[0049] Figure 9 This is a schematic diagram of the structure after forming an etch stop layer and an insulating layer, as provided in one embodiment.

[0050] Figure 10 This is a schematic diagram of the structure after grinding an insulating layer with an etch stop layer as the stop layer, according to one embodiment.

[0051] Figure 11 This is a schematic diagram of the structure after the etch stop layer and the insulating layer have been etched into the conductive channel, as provided in one embodiment.

[0052] Figure 12 This is a schematic diagram of the structure after the etch stop layer and the insulating layer are etched into the conductive channel, as provided in one embodiment.

[0053] Explanation of reference numerals in the attached figures:

[0054] 10. Substrate; 11. Oxide layer; 111. Conductive region; 12. Electrical connector; 20. First contact layer; 21. Source metal electrode; 211. First source barrier layer; 212. Source conductive layer; 213. Second source barrier layer; 30. Gate structure; 31. Gate conductive layer; 32. Gate dielectric layer; 40. Isolation layer; 50. Conductive channel; 50a. Channel material layer; 60. Etch stop layer; 70. Insulating layer; 80. Channel trench; 90. Second contact layer; 141. Recess; 181. First dielectric layer; 182. Second dielectric layer; 183. Third dielectric layer; 184. Fourth dielectric layer; 185. Fifth dielectric layer; 190. Connection surface;

[0055] D1, first direction; D2, second direction D2. Detailed Implementation

[0056] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0058] According to an exemplary embodiment, this embodiment provides a semiconductor structure, such as... Figure 1 , Figure 2 , Figure 3 As shown, or refer to Figure 4 , Figure 5 , Figure 6As shown, the semiconductor structure includes a substrate 10, a first contact layer 20, a gate structure 30, an isolation layer 40, a conductive channel 50, an insulating layer 70, an etch stop layer 60, and a second contact layer 90. The first contact layer 20 is disposed on the substrate 10; the gate structure 30 is disposed on the first contact layer 20; the isolation layer 40 is disposed on the gate structure 30; the conductive channel 50 penetrates the isolation layer 40 and the gate structure 30 is disposed on the first contact layer 20; the insulating layer 70 is disposed inside the conductive channel 50; the etch stop layer 60 is located between the conductive channel 50 and the insulating layer 70, and in the direction perpendicular to the substrate 10, the height of the etch stop layer 60 is different from the height of the insulating layer 70; the second contact layer 90 is disposed on the etch stop layer 60 and the insulating layer 70, and is connected to the conductive channel 50. It will be understood that when an element is referred to as being “connected” or “coupled” to another element or “on” another element, the element may be directly connected or coupled to the other element or “on” another element, or there may be intermediate elements present. Conversely, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as being “in contact” with another element or “in contact with” another element, there are no intermediate elements at the point of contact. Other terms used to describe relationships between elements should be interpreted in a similar manner (e.g., “between” vs. “directly between”, “adjacent” vs. “directly adjacent”, etc.).

[0059] The substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, or a fully depleted silicon-on-insulator substrate, but is not limited to these. In this embodiment, an oxide layer 11 is also formed on the substrate 10. (Refer to...) Figure 1 or Figure 4 The oxide layer 11 has multiple conductive regions 111. At least one dielectric layer is stacked on the oxide layer 11. The at least one dielectric layer includes a stacked structure composed of different material layers, such as a stacked structure composed of an oxide layer and a nitride layer, or it may be a single material layer, such as an oxide layer or a nitride layer, and is not limited thereto.

[0060] An electrical connector 12 is also provided on the substrate 10. The electrical connector 12 penetrates at least one dielectric layer and is connected to the gate structure 30 so that the gate structure 30 is electrically connected to the substrate 10.

[0061] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5A first contact layer 20, a gate structure 30, and a second contact layer 90 are stacked vertically on a substrate 10 in sequence, with the first contact layer 20 and the substrate 10 separated by at least one dielectric layer. The first contact layer 20 extends along a first direction D1, and a source metal electrode 21 extending along the first direction D1 is disposed below the first contact layer 20. The bottom surface of the first contact layer 20 is in contact with the source metal electrode 21 to reduce the contact resistance of the source metal electrode 21. The second contact layer 90 is spaced apart along a second direction D2, and a drain metal electrode may be stacked on top of the second contact layer 90. The second contact layer 90 is used to reduce the contact resistance of the drain metal electrode (not shown in the figure).

[0062] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5 A conductive channel 50 penetrates the gate structure 30 and connects to the first contact layer 20. The projection of the conductive channel 50 onto a plane perpendicular to the substrate 10 is U-shaped, with the opening of the U-shape facing away from the substrate 10. The conductive channel 50 covers the gate dielectric layer 32 and the first contact layer 20, and is in contact with the first contact layer 20. An isolation layer 40 is disposed on the gate structure 30, and the top surface of the isolation layer 40 is flush with the top surface of the conductive channel 50.

[0063] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5 The gate structure 30 includes a gate conductive layer 31 and a gate dielectric layer 32 surrounding the outer wall of the conductive channel 50. The conductive channel 50 and the gate conductive layer 31 are separated by the gate dielectric layer 32. The material of the conductive channel 50 may include doped polysilicon. The gate conductive layer 31 includes a gate barrier layer (e.g., TiN) and a gate metal layer (e.g., W) stacked sequentially from bottom to top. Alternatively, the gate structure 30 may also include a gate semiconductor layer (e.g., doped polysilicon) and / or a gate metal silicide (e.g., WSi) layer. The gate semiconductor layer may be located on the gate metal layer. In other embodiments, the gate metal silicide layer may be located on the gate semiconductor layer or the gate metal layer.

[0064] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5 The etch stop layer 60 covers a portion of the inner wall surface of the conductive channel 50, and the insulating layer 70 is disposed inside the etch stop layer 60. The second contact layer 90 is disposed above the etch stop layer 60 and the insulating layer 70, and is in contact with the inner wall surface of the conductive channel 50 located above the etch stop layer 60 and the insulating layer 70.

[0065] The etch stop layer 60 may comprise a single layer or a multilayer structure stacked sequentially, and the insulating layer 70 may comprise a single layer or a multilayer structure stacked sequentially. The material of the etch stop layer 60 is different from the material of the insulating layer 70.

[0066] For example, the material of the etch stop layer 60 may include at least one of silicon nitride (SiN), silicon oxynitride (SiNO), silicon oxycarbide (SiNC), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), and silicon oxycarbide (SiOC).

[0067] The material of the insulating layer 70 may include a low-k dielectric material or silicon oxide. The low-k dielectric material may be a material having a lower dielectric constant than silicon oxide. The low-k dielectric material may include one or more of the following: flowable oxide (FOX), TOSZ, undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate-phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high-density plasma (HDP) oxide, plasma-enhanced oxide (PEOX), or flowable CVD (FCVD) oxide.

[0068] In one example, the etch stop layer 60 is made of silicon nitride and the insulating layer 70 is made of silicon oxide; in another example, the etch stop layer 60 is made of silicon oxide nitride and the insulating layer 70 is made of borosilicate glass; in yet another example, the etch stop layer 60 is made of borosilicate silicon oxynitride and the insulating layer 70 is made of high-density plasma (HDP) oxide. However, these examples are not limiting.

[0069] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5 The top surfaces of the etch stop layer 60 and the insulating layer 70 have different heights. In one example, the top surface of the etch stop layer 60 is higher than the top surface of the insulating layer 70; in another example, the top surface of the insulating layer 70 is higher than the top surface of the etch stop layer 60.

[0070] In this embodiment of the semiconductor structure, an etch stop layer 60 is added between the insulating layer 70 and the inner wall of the conductive channel 50. The etch stop layer 60 is made of a different material than the insulating layer 70. During the fabrication of the semiconductor structure, the etch stop layer 60 can protect the isolation layer 40, avoiding damage to the isolation layer 40 during the removal of the insulating layer above the conductive channel 50, which could lead to short circuits between devices. This ensures the integrity of the semiconductor structure's structure and performance, improves product yield, and is suitable for the development needs of semiconductor structures towards smaller feature sizes.

[0071] In some embodiments, refer to Figure 1 , Figure 2 , Figure 4 , Figure 5 The top surface of the etch stop layer 60 and the top surface of the insulating layer 70 are lower than the top surface of the conductive channel 50, while the top surface of the insulating layer 70 is not lower than the top surface of the gate structure 30. The bottom wall and at least a portion of the sidewalls of the insulating layer 70 are in contact with the etch stop layer 60. The second contact layer 90 is disposed inside the conductive channel 50. This design, on the one hand, helps to reduce the parasitic capacitance of the semiconductor structure and improve its response speed; on the other hand, it ensures a large contact area between the second contact layer 90 and the conductive channel 50, which helps to reduce the contact resistance between the second contact layer 90 and the conductive channel 50 and improve the electrical performance of the semiconductor structure.

[0072] In some embodiments, the etch rate of the etch stop layer 60 is different from the etch rate of the insulating layer 70. (Refer to...) Figure 1 , Figure 2 , Figure 3 , or refer to Figure 4 , Figure 5 , Figure 6 The connection surface 190 between the top surface of the etch stop layer 60 and the top surface of the insulating layer 70 (refer to...) Figure 3 , Figure 6 (As indicated by the dashed line at position 190 in the diagram), there is a recess 141, and a portion of the second contact layer 90 is disposed in the recess 141.

[0073] It is understood that the etch stop layer 60 and the insulating layer 70 are etched to the top surface of the etch stop layer 60 in the same etching process. The top surface of the insulating layer 70 is lower than the top surface of the conductive channel 50, and the top surface of the insulating layer 70 is not lower than the top surface of the gate structure 30. The difference in etching rate between the etch stop layer 60 and the insulating layer 70 results in a difference in the height of the top surfaces of the etch stop layer 60 and the insulating layer 70.

[0074] In some embodiments, refer to Figure 1 , Figure 2 , Figure 3 The top surface of the etch stop layer 60 is lower than the top surface of the insulating layer 70, and the recess 141 is provided on the etch stop layer 60. That is, recesses 141 are formed on both sides of the etch stop layer 60, and the bottom sides of the second contact layer 90 protrude towards the substrate 10 and are respectively embedded in the recesses 141 on both sides of the etch stop layer 60. In this way, the area of ​​the inner sidewall of the top of the conductive channel 50 that is not covered by the etch stop layer 60 is larger, which increases the contact area between the second contact layer 90 and the inner sidewall of the conductive channel 50, thereby reducing the contact resistance between the second contact layer 90 and the conductive channel 50 and improving the electrical performance of the semiconductor structure.

[0075] In some embodiments, refer to Figure 4 , Figure 5 , Figure 6 The top surface of the insulating layer 70 is lower than the top surface of the etch stop layer 60, and the recess 141 is provided on the insulating layer 70. Thus, the middle region of the bottom of the second contact layer 90 protrudes towards the substrate 10 and is embedded in the recess 141. This increases the size of the second contact layer 90, which helps to reduce the overall resistance of the second contact layer 90, improve the conductivity of the second contact layer 90, and thereby enhance the electrical performance of the semiconductor structure.

[0076] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments. Figure 7 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown, such as... Figure 7 The present disclosure provides a method for fabricating a semiconductor structure according to an exemplary embodiment, comprising the following steps:

[0077] Step S11: Provide a substrate;

[0078] Step S12: Form a first contact layer, a gate structure, an isolation layer and a channel material layer. The first contact layer is disposed on the substrate, the gate structure is disposed on the first contact layer, the isolation layer is disposed on the gate structure, the channel material layer covers the isolation layer and forms a conductive channel, the conductive channel penetrates the isolation layer, and the gate structure is disposed on the first contact layer.

[0079] Step S13: Form an etch stop layer to cover the conductive channel and the isolation layer;

[0080] Step S14: Form an insulating layer, cover the etch stop layer and fill the conductive channel. The etch rate of the insulating layer and the etch stop layer are different.

[0081] Step S15: Grind the insulating layer using the etch stop layer as the stop layer;

[0082] Step S16: Etch the etch stop layer and the insulating layer into the conductive channel. In the direction perpendicular to the substrate, the height of the etch stop layer is different from the height of the insulating layer.

[0083] Step S17: Form a second contact layer, which is disposed on the etch stop layer and the insulating layer and connected to the conductive channel.

[0084] The semiconductor structure fabrication method of this embodiment forms an etch stop layer before filling the conductive channel with an insulating layer. The etch stop layer covers the inner wall surface of the conductive channel and the top surface of the isolation layer. The etch stop layer protects the isolation layer and prevents damage to the isolation layer during the process of removing the insulating layer on the top surface of the conductive channel, thus exposing the gate structure. This also prevents the second contact layer formed by subsequently filling the conductive material from short-circuiting with the gate structure, ensuring the structural and performance integrity of the formed semiconductor structure. This is beneficial for improving product yield and is suitable for the development needs of semiconductor structures towards smaller feature sizes.

[0085] The following is combined Figures 8-12 And refer to Figures 1-6 The process of fabricating semiconductor structures is explained in detail for each step.

[0086] In step S11, refer to Figure 8 The substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate, but is not limited to these.

[0087] An oxide layer 11 is also formed on the substrate 10, and the oxide layer 11 has multiple conductive regions 111.

[0088] At least one dielectric layer is stacked on the oxide layer 11. The at least one dielectric layer includes a stacked structure composed of different material layers, such as a stacked structure composed of an oxide layer and a nitride layer, or it may be a single material layer, such as an oxide layer or a nitride layer, and is not limited thereto.

[0089] In this embodiment, a first dielectric layer 181 and a second dielectric layer 182 are sequentially stacked on the substrate 10.

[0090] In step S12, the following implementation method can be adopted:

[0091] First, refer to Figure 8 A third dielectric layer 183 is sequentially deposited on the second dielectric layer 182 using chemical vapor deposition (CVD) or atomic layer deposition (ALD). The third dielectric layer 183 is etched to form a first trench (not shown) extending along a first direction D1. A source metal electrode 21 and a first contact layer 20 are sequentially deposited in the first trench. In this embodiment, the source metal electrode 21 includes a first source barrier layer 211, a source conductive layer 212, and a second source barrier layer 213 stacked sequentially. For example, the materials of the first source barrier layer 211 and the second source barrier layer 213 may include titanium nitride, the material of the source conductive layer 212 may include tungsten, and the material of the first contact layer 20 may include a semiconductor material, such as doped polysilicon.

[0092] Then, refer to Figure 8A fourth dielectric layer 184 is formed by CVD or ALD deposition, covering the first contact layer 20 and the third dielectric layer 183. Through-holes (not shown) are etched to penetrate the fourth dielectric layer 184, the third dielectric layer 183, the second dielectric layer 182, and the first dielectric layer 181, exposing a portion of the top surface of the conductive region 111 on the substrate 10. Conductive material is deposited and filled into the through-holes to form an electrical connector 12. For example, the material of the electrical connector 12 may include titanium, copper, tantalum, or tungsten.

[0093] In some embodiments, refer to Figure 8 After forming the electrical connector 12, the fourth dielectric layer 184 is etched back to increase the area of ​​the exposed electrical connector 12 and increase the contact area between the electrical connector 12 and the subsequently formed gate structure 30.

[0094] Then, refer to Figure 8 and in conjunction with reference Figure 1 , Figure 2 , Figure 4 , Figure 5 A fifth dielectric layer 185 is formed by CVD deposition, covering the top surface of the first contact layer 20, the top surface of the electrical connector 12, and the top surface of the fourth dielectric layer 184. The material of the fifth dielectric layer 185 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. The fifth dielectric layer 185 is etched to form a gate trench (not shown) extending along the second direction D2, exposing a portion of the top surface of the first contact layer 20 and the top surface of the electrical connector 12.

[0095] A gate conductive layer 31 is deposited by CVD or ALD to fill the gate trench and cover the top surface of the electrical connector 12. The electrical connector 12 is electrically connected to the conductive region 111 on the substrate 10.

[0096] For example, the gate conductive layer 31 may include a gate barrier layer and a gate metal layer stacked sequentially from bottom to top. Alternatively, the gate structure 30 may also include a gate semiconductor layer and / or a gate metal silicide layer, wherein the gate semiconductor layer may be located on the gate metal layer and the gate metal silicide layer may be located on the gate semiconductor layer or the gate metal layer.

[0097] Next, refer to Figure 8 An isolation layer 40 is deposited using CVD or ALD, and the isolation layer 40 covers the gate conductive layer 31 and the fifth dielectric layer 185. The material of the isolation layer 40 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0098] Next, refer to Figure 8 The isolation layer 40 and the gate conductive layer 31 are etched to form a trench 80, which penetrates the isolation layer 40 and the gate conductive layer 31 to expose a portion of the top surface of the first contact layer 20.

[0099] A gate dielectric material layer and a channel material layer 50a are deposited to cover the channel trench 80. The gate dielectric material layer and the channel material layer 50a on the bottom wall of the channel trench 80 are removed to expose the top surface of the first contact layer 20, forming a gate dielectric layer 32 that covers the sidewalls of the channel trench 80. The gate conductive layer 31 and the gate dielectric layer 32 together form the gate structure 30.

[0100] Next, refer to Figure 8 A channel material layer 50a is deposited again using an ALD process. The channel material layer 50a covers the exposed first contact layer 20, gate dielectric layer 32, and top surface of the isolation layer 40 on the bottom wall of the channel trench 80. The channel material layer 50a located within the channel trench 80 forms a conductive channel 50, which contacts the gate dielectric layer 32 and the first contact layer 20. The material of the conductive channel 50 may include doped polysilicon.

[0101] In step S13, refer to Figure 9 An etch stop layer 60 can be formed by ALD deposition, and the etch stop layer 60 covers the channel material layer 50a.

[0102] For example, the material of the etch stop layer 60 may include at least one of silicon nitride (SiN), silicon oxynitride (SiNO), silicon oxycarbide (SiNC), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), and silicon oxycarbide (SiOC).

[0103] In step S14, refer to Figure 9 An insulating layer 70 is formed by CVD or ALD deposition. The insulating layer 70 fills the unfilled areas of the trench 80. The material of the etch stop layer 60 is different from that of the insulating layer 70.

[0104] Reference Figure 9 The material of the insulating layer 70 may include a low-k dielectric material or silicon oxide. The low-k dielectric material may be a material having a lower dielectric constant than silicon oxide. The low-k dielectric material may include one or more of the following: flowable oxide (FOX), TOSZ, undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate-phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high-density plasma (HDP) oxide, plasma-enhanced oxide (PEOX), or flowable CVD (FCVD) oxide.

[0105] The etch rates of insulating layer 70 and etch stop layer 60 are different, meaning that insulating layer 70 and etch stop layer 60 are made of different materials. Therefore, in subsequent etching steps, one or more etching process parameters can be selected, such as the chemical properties of the etchant gas. When etching both stop layer 60 and insulating layer 70 simultaneously, the etch rate of insulating layer 70 is greater than that of etch stop layer 60, meaning that the removal speed of insulating layer 70 is faster. It can be understood that, in the direction perpendicular to substrate 10, the thickness of insulating layer 70 that needs to be removed is much greater than the thickness of etch stop layer 60 that needs to be removed (see attached figure for thickness direction). Figure 9 (in the direction of the middle arrow H), therefore, within the same etching time, the insulating layer 70 requires a higher etching and / or polishing rate to prevent the isolation layer 40 from being damaged. This is because the etching rate of the etch stop layer 60 is slower. The etch stop layer 60 is located above the isolation layer 40 and can protect the isolation layer 40. In this way, the isolation layer 40 can be ensured to protect the gate conductive layer 31.

[0106] In one example, the etch stop layer 60 is made of silicon nitride, and the insulating layer 70 is made of silicon oxide; in another example, the etch stop layer 60 is made of silicon oxide nitride, and the insulating layer 70 is made of borosilicate glass; in yet another example, the etch stop layer 60 is made of silicon boron oxynitride, and the insulating layer 70 is made of high-density plasma (HDP) oxide. However, this is not a limitation. In step S15, refer to... Figure 10 Chemical mechanical polishing (CMP) is used to polish the insulating layer 70 to remove it from the channel material layer 50a, reducing the difficulty of subsequent etching. Since the insulating layer 70 and the etch stop layer 60 are made of different materials, in this embodiment, the top surface of the etch stop layer 60 is used as the polishing stop surface; that is, the polishing process stops after the top surface of the etch stop layer 60 is exposed. Using the top surface of the etch stop layer 60 as the polishing stop surface allows for precise control of the polishing endpoint, ensuring that the top surface of the isolation layer 40 remains a complete and flat plane after polishing. This avoids the defect of over-polishing causing the film layer on top of the isolation layer 40 to be removed, further preventing etching damage to the isolation layer 40 and creating pits on the top of the isolation layer 40 that affect the dimensional accuracy of the subsequent formation of the second contact layer 90. It also avoids irreparable defects such as the isolation layer 40 being damaged too much during polishing, exposing the top surface of the gate conductive layer 31. In other embodiments, etching can also be used to remove the insulating layer 70 from the channel material layer 50a.

[0107] In step S16, refer to Figure 11 or Figure 12Plasma co-etching can be used to etch the etch stop layer 60 and the insulating layer 70 into the conductive channel 50, exposing part of the inner sidewall of the top of the conductive channel 50, so as to increase the contact area between the conductive channel 50 and the subsequently formed second contact layer 90.

[0108] In step S17, a second contact layer 90 can be formed by CVD or ALD deposition. The second contact layer 90 covers the top surface of the remaining etch stop layer 60 and the top surface of the remaining insulating layer 70, and fills the unfilled area inside the conductive channel 50. The second contact layer 90 deposited on the outside of the conductive channel 50 is etched away, leaving the second contact layer 90 located inside the conductive channel 50. The second contact layer 90 is in contact with the inner wall of the top of the conductive channel 50. The material of the second contact layer 90 can include a semiconductor material, such as doped polysilicon.

[0109] Furthermore, after forming the second contact layer 90, a drain metal electrode is formed on the second contact layer 90, and the drain metal electrode is connected to the second contact layer 90. The drain metal electrode includes a first drain barrier layer, a drain conductive layer, and a second drain barrier layer stacked sequentially. For example, the materials of the first drain barrier layer and the second drain barrier layer may include titanium nitride, and the material of the drain conductive layer may include tungsten.

[0110] In some embodiments, refer to Figure 11 or Figure 12 After etching the etch stop layer 60 and the insulating layer 70 into the conductive channel 50, the top surface of the etch stop layer 60 and the top surface of the insulating layer 70 are lower than the top surface of the conductive channel 50, while the top surface of the insulating layer 70 is not lower than the top surface of the gate structure 30. This, on the one hand, helps reduce the parasitic capacitance of the semiconductor structure and improve its response speed; on the other hand, it ensures a large contact area between the second contact layer 90 and the conductive channel 50, which helps reduce the contact resistance between the second contact layer 90 and the conductive channel 50 and improves the electrical performance of the semiconductor structure.

[0111] In some embodiments, refer to Figure 11 or Figure 12 The etching rate of the etch stop layer 60 is less than that of the insulating layer 70. After the etch stop layer 60 and the insulating layer 70 are etched into the conductive channel 50, the top surface of the etch stop layer 60 and the top surface of the insulating layer 70 are at different heights. The connection surface 190 between the top surface of the etch stop layer 60 and the top surface of the insulating layer 70 has a recess 141, and a portion of the second contact layer 90 is disposed in the recess 141.

[0112] In some embodiments, refer to Figure 11 , Figure 1 , Figure 2 , Figure 3 The etching rate of the etch stop layer 60 is less than that of the insulating layer 70. After etching the etch stop layer 60 and the insulating layer 70 into the conductive channel 50, the top surface of the etch stop layer 60 is lower than the top surface of the insulating layer 70, and a recess 141 is formed on the etch stop layer 60. That is, recesses 141 are formed on both sides of the etch stop layer 60, and the bottom sides of the second contact layer 90 protrude towards the substrate 10 and are respectively embedded in the recesses 141 on both sides of the etch stop layer 60. In this way, the area of ​​the inner sidewall of the top of the conductive channel 50 that is not covered by the etch stop layer 60 is larger, which increases the contact area between the second contact layer 90 and the inner sidewall of the conductive channel 50, thereby reducing the contact resistance between the second contact layer 90 and the conductive channel 50 and improving the electrical performance of the semiconductor structure.

[0113] In some embodiments, refer to Figure 12 , Figure 4 , Figure 5 , Figure 6 After etching the etch stop layer 60 and the insulating layer 70 into the conductive channel 50, the top surface of the insulating layer 70 is lower than the top surface of the etch stop layer 60, and a recess 141 is provided on the insulating layer 70. Thus, the middle region of the bottom of the second contact layer 90 protrudes towards the substrate 10 and is embedded in the recess 141. This increases the size of the second contact layer 90, which helps to reduce the overall resistance of the second contact layer 90, improve the conductivity of the second contact layer 90, and thereby enhance the electrical performance of the semiconductor structure.

[0114] In some embodiments, the fabrication method further includes: step S18: etching the channel material layer 50a to expose the top surface of the isolation layer 40 and the gate dielectric layer 31.

[0115] The channel material layer 50a located on the top surface of the isolation layer 40 is etched away, leaving only the channel material layer 50a located in the channel trench 80 as the conductive channel 50.

[0116] In some other embodiments, the etching process to remove the channel material layer 50a from the top surface of the isolation layer 40 can be performed immediately after the formation of the channel material layer 50a. It is understood that, since the etch stop layer 60 is formed, it adequately protects the isolation layer 40 from etch damage. Therefore, removing the channel material layer 50a from the top surface of the isolation layer 40 after its formation will not affect the performance and quality of the fabricated semiconductor structure.

[0117] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A first contact layer is disposed on the substrate; A gate structure is disposed on the first contact layer; An isolation layer is disposed on the gate structure; A conductive channel penetrates the isolation layer and the gate structure, and is disposed on the first contact layer; An insulating layer is disposed on the inner side of the conductive channel; An etch stop layer is located between the conductive channel and the insulating layer. In a direction perpendicular to the substrate, the height of the etch stop layer is different from the height of the insulating layer. The etch rate of the etch stop layer is less than the etch rate of the insulating layer. The second contact layer is disposed on the etch stop layer and the insulating layer, and is connected to the conductive channel; The process of forming the etch stop layer includes: forming an etch stop layer in a trench, the etch stop layer extending to the isolation layer, and removing the etch stop layer on the isolation layer.

2. The semiconductor structure according to claim 1, characterized in that, The gate structure includes a gate conductive layer and a gate dielectric layer surrounding the outer wall surface of the conductive channel; The top surface of the etch stop layer and the top surface of the insulating layer are lower than the top surface of the conductive channel, and the top surface of the insulating layer is not lower than the top surface of the gate conductive layer; The bottom wall of the insulating layer and at least a portion of the sidewalls of the insulating layer are in contact with the etch stop layer; the second contact layer is disposed inside the conductive channel.

3. The semiconductor structure according to claim 1, characterized in that, The interface between the top surface of the etch stop layer and the top surface of the insulating layer has a recess, and a portion of the second contact layer is disposed in the recess.

4. The semiconductor structure according to claim 3, characterized in that, The top surface of the insulating layer is lower than the top surface of the etch stop layer, and the recess is provided on the insulating layer.

5. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A first contact layer, a gate structure, an isolation layer, and a channel material layer are formed. The first contact layer is disposed on the substrate, the gate structure is disposed on the first contact layer, the isolation layer is disposed on the gate structure, and the channel material layer covers the isolation layer and forms a conductive channel. The conductive channel penetrates the isolation layer and the gate structure and is disposed on the first contact layer. An etch stop layer is formed, covering the top surface of the conductive channel and the isolation layer; An insulating layer is formed to cover the etch stop layer and fill the conductive channel, wherein the etch rate of the etch stop layer is less than the etch rate of the insulating layer; The insulating layer is ground using the etching stop layer as a stop layer; The etch stop layer and the insulating layer are etched into the conductive channel, and the height of the etch stop layer is different from the height of the insulating layer in the direction perpendicular to the substrate; A second contact layer is formed on the etch stop layer and the insulating layer, and is connected to the conductive channel.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, After the etch stop layer and the insulating layer are etched into the conductive channel, the top surface of the etch stop layer and the top surface of the insulating layer are lower than the top surface of the conductive channel; The gate structure includes a gate conductive layer and a gate dielectric layer surrounding the outer wall of the conductive channel, wherein the top surface of the insulating layer is not lower than the top surface of the gate conductive layer.

7. The method for fabricating a semiconductor structure according to claim 5, characterized in that, After the etch stop layer and the insulating layer are etched into the conductive channel, the top surface of the etch stop layer and the top surface of the insulating layer are at different heights. The connection surface between the top surface of the etch stop layer and the top surface of the insulating layer has a recess, and a portion of the second contact layer is disposed in the recess.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, After the etch stop layer and the insulating layer are etched into the conductive channel, the top surface of the insulating layer is lower than the top surface of the etch stop layer, and the recess is provided on the insulating layer.

9. The method for fabricating a semiconductor structure according to claim 5, characterized in that, The manufacturing method further includes: The channel material layer is etched to expose the top surface of the isolation layer, and the remaining channel material layer forms the conductive channel.

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