Clock phase detector with gating function, high-speed analog-to-digital / digital-to-analog conversion system

Abstract

The present application relates to the technical field of integrated circuits, and discloses a clock phase detector with a gating function, and a high-speed analog-to-digital / digital-to-analog conversion system, wherein the clock phase detector comprises: a first clock gating logic, which receives low-frequency and high-frequency clock signals respectively and obtains the rising edge phase information of the high-frequency clock signal at the rising edge of the low-frequency clock signal, so that the high-frequency clock signal does not flip before the low level of the low-frequency clock signal arrives; a second clock gating logic, which is used to delay and output a first delayed low-frequency clock signal; a first and a second NAND gate, wherein the input end of the first NAND gate is coupled to the output end of the first clock gating logic and the output end of the second NAND gate, and the input end of the second NAND gate is coupled to the output end of the second clock gating logic and the output end of the first NAND gate; a first inverter, wherein the input end is coupled to the output end of the first NAND gate; a second inverter, wherein the input end is coupled to the output end of the second NAND gate; a trigger, wherein the data end is coupled to the output end of the first inverter, and the clock end receives the second delayed low-frequency clock signal. The present application can reduce the probability of misjudgment of the phase detector.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more specifically to a clock phase detector with a gating function, and a high-speed analog-to-digital / digital-to-analog conversion system. Background Art

[0002] A clock phase detector (PD) is a circuit or device used to detect and measure the phase difference between two input signals. It plays a vital role in many electronic and communication systems and is widely used in phase-locked loops (PLLs), frequency synthesis, data synchronization, etc. The main function of a clock phase detector is to compare the phases of two input signals and generate an output signal proportional to their phase difference.

[0003] Figure 1 The circuit system for synchronous reset of ultra-high-speed analog-to-digital / digital-to-analog converter (AD / DA) is presented. Since the AD / DA circuits in the entire circuit system may have different phases, timing mismatches and other working states, sometimes a single clock signal is needed to synchronously reset the AD / DA circuits of all channels so that their phases and working states are the same and they work in synchronous mode. The specific implementation process is as follows: First, the low-frequency clock signal (CKLF) used for system synchronization and the high-frequency clock signal (CKHF) of AD / DA are input into a phase detector with clock gating function to obtain the phase information between the two clocks, which is provided to the subsequent synchronous reset signal generator, thereby generating a reset signal with a fixed phase relationship with the AD / DA high-frequency clock, and resetting all ultra-high-speed AD / DA circuits that need to be synchronized to the same starting phase. The traditional clock phase detector directly processes two clock signal inputs with different frequencies, which is prone to misjudgment.

[0004] This section is intended to provide a background or context to the embodiments of the present application as recited in the claims. The description herein is not admitted to be prior art as disclosed by virtue of its inclusion in this section. Summary of the invention

[0005] The purpose of the present application is to provide a clock phase detector with a gating function, which regulates a high-frequency clock signal through a low-frequency clock so that the high-frequency clock no longer flips when performing phase comparison, thereby reducing the probability of misjudgment of the phase detector.

[0006] The purpose of the present application is also to provide a high-speed analog-to-digital / digital-to-analog conversion system including the above-mentioned clock phase detector.

[0007] The present application discloses a clock phase detector with a gating function, comprising:

[0008] a first clock gating logic, wherein the first clock gating logic receives a low-frequency clock signal and a high-frequency clock signal respectively and obtains rising edge phase information of the high-frequency clock signal at a rising edge of the low-frequency clock signal, and makes the high-frequency clock signal no longer flip before a low level of the low-frequency clock signal arrives;

[0009] a second clock gating logic, the second clock gating logic being used to delay and output a first delayed low-frequency clock signal;

[0010] First and second NAND gates, one input terminal of the first NAND gate is coupled to the output terminal of the first clock gating logic, and the other input terminal is coupled to the output terminal of the second NAND gate, one input terminal of the second NAND gate is coupled to the output terminal of the second clock gating logic, and the other input terminal is coupled to the output terminal of the first NAND gate;

[0011] a first inverter, wherein an input terminal of the first inverter is coupled to an output terminal of the first NAND gate;

[0012] a second inverter, an input terminal of the second inverter being coupled to an output terminal of the second NAND gate; and

[0013] A trigger, wherein a data terminal of the trigger is coupled to an output terminal of the first inverter, and a clock terminal of the trigger receives a second delayed low-frequency clock signal.

[0014] In a preferred example, it also includes: a first delay unit, the input end of which receives the low-frequency clock signal and outputs the second delayed low-frequency clock signal, wherein the delay amount of the second delayed low-frequency clock signal relative to the low-frequency clock signal is greater than the delay amount of the first delayed low-frequency clock signal relative to the low-frequency clock signal.

[0015] In a preferred example, the first clock gating logic and the second clock gating logic each include: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a third inverter, and a second delay unit;

[0016] The source of the first MOS transistor is coupled to a voltage source, the drain of the first MOS transistor is coupled to the source of the second MOS transistor, the gate of the first MOS transistor and the input of the second delay unit are both coupled to a gating signal, the gate of the second MOS transistor and the gate of the third MOS transistor are both coupled to a clock input signal, the drain of the second MOS transistor is connected to the drain of the third MOS transistor and coupled to the drain of the fourth MOS transistor and the input of the third inverter, the source of the third MOS transistor is coupled to the ground, the output of the second delay unit is coupled to the gate of the fourth MOS transistor, the source of the fourth MOS transistor is coupled to the ground, and the output of the third inverter outputs a clock output signal.

[0017] In a preferred example, the gating signal of the first clock gating logic receives the low-frequency clock signal, and the clock input signal receives the high-frequency clock signal; at the rising edge of the low-frequency clock signal, the first MOS transistor of the first clock gating logic is turned off, so that the first clock gating logic maintains the most recent rising edge transition of the high-frequency clock signal, and the output end of the third inverter of the first clock gating logic outputs a constant non-flipping signal until the gating signal has a falling edge transition.

[0018] In a preferred example, at the rising edge of the low-frequency clock signal, if the high-frequency clock signal has jumped from a low level to a high level, the drain of the second MOS transistor and the drain of the third MOS transistor output a low level and remain at a low level, and the output end of the third inverter of the first clock gating logic outputs a constant high-level signal that does not flip; if the high-frequency clock signal has jumped from a high level to a low level, the drain of the second MOS transistor and the drain of the third MOS transistor output a high level, and after a certain delay, the first and second NAND gates complete the phase comparison, the drain output of the third MOS transistor is pulled down by the fourth transistor and maintained at a low level, and the output end of the third inverter of the first clock gating logic outputs a constant high-level signal that does not flip.

[0019] In a preferred example, near the rising edge of the low-frequency clock signal, the output end of the third inverter of the first clock gating logic outputs a constant high-level signal that does not flip.

[0020] In a preferred example, the gating signal and the clock input signal of the second clock gating logic both receive the low-frequency clock signal, and the output end of the third inverter of the second clock gating logic outputs the first delayed low-frequency clock signal.

[0021] In a preferred example, the first MOS transistor and the second MOS transistor are PMOS transistors, and the third MOS transistor and the fourth MOS transistor are NMOS transistors.

[0022] The present application also discloses a high-speed analog-to-digital / digital-to-analog conversion system, comprising:

[0023] A clock phase detector with a gating function as described above;

[0024] a synchronous reset signal generator coupled to an output terminal of the clock phase detector; and

[0025] An analog-to-digital / digital-to-analog converter is coupled to the output terminal of the synchronous reset signal generator and the high-frequency clock signal.

[0026] In a preferred example, the analog-to-digital / digital-to-analog converter includes multiple channels of analog-to-digital / digital-to-analog conversion units.

[0027] In the implementation manner of the present application, the clock gating logic is used to obtain the phase of the high-frequency clock signal at the rising edge of the low-frequency clock signal, and to keep it at a high level and no longer flip, so that the high-frequency clock signal is approximately converted into a low-frequency clock signal with the same phase information. The same low-frequency signals output by the two clock gating logics are processed by a phase detector formed by cross-coupling of two NAND gates to obtain a result that characterizes the phase relationship of the signals, which can reduce the probability of misjudgment of the phase detector.

[0028] The specification of the present application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of the present application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been recorded because it is technically infeasible, and the solution of A+B+C+E should be regarded as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 A schematic diagram of the structure of an ultra-high-speed analog-to-digital / digital-to-analog conversion system is shown.

[0031] Figure 2 A schematic diagram of the structure of a clock phase detector with a gating function according to an embodiment of the present application is shown.

[0032] Figure 3 A schematic diagram of the structure of clock gating logic according to an embodiment of the present application is shown.

[0033] Figure 4 A schematic diagram showing the working process of the first clock gating logic according to an embodiment of the present application is shown.

[0034] Figure 5 A schematic diagram showing the working process of a clock phase detector with a gating function according to an embodiment of the present application is shown.

[0035] In each of the drawings, the symbols are as follows: {Indicate the symbols in each of the drawings}

[0036] 101- first clock gating logic;

[0037] 102-second clock gating logic;

[0038] 103-first NAND gate;

[0039] 104-second NAND gate;

[0040] 105- a first inverter;

[0041] 106- a second inverter;

[0042] 107-trigger;

[0043] 108-first delay unit;

[0044] 109- a third inverter;

[0045] 110 - second delay unit. DETAILED DESCRIPTION

[0046] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0047] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0048] One embodiment of the present application relates to a clock phase detector with a gating function, whose structure is as follows: Figure 2 As shown, the clock phase detector includes: a first clock gating logic 101 , a second clock gating logic 102 , a first NAND gate 103 , a second NAND gate 104 , a first inverter 105 , a second inverter 106 and a trigger 107 .

[0049] The first clock gating logic 101 receives the low-frequency clock signal CKLF and the high-frequency clock signal CKHF respectively, obtains the rising edge phase information of the high-frequency clock signal CKHF at the rising edge of the low-frequency clock signal CKLF, and makes the high-frequency clock signal CKHF no longer flip before the low level of the low-frequency clock signal CKLF arrives. The second clock gating logic 102 is used to delay and output the first delayed low-frequency clock signal. One input end of the first NAND gate 103 is coupled to the output end of the first clock gating logic 101, and the other input end is coupled to the output end of the second NAND gate 104. One input end of the second NAND gate 104 is coupled to the output end of the second clock gating logic 102, and the other input end is coupled to the output end of the first NAND gate 103. The input end of the first inverter 105 is coupled to the output end of the first NAND gate 103. The input end of the second inverter 106 is coupled to the output end of the second NAND gate 104. The data end of the trigger 107 is coupled to the output end of the first inverter 105, and the clock end receives the second delayed low-frequency clock signal.

[0050] In one embodiment, the clock phase detector with a gating function further includes: a first delay unit 108, wherein an input end of the first delay unit 108 receives the low-frequency clock signal CKLF and outputs a second delayed low-frequency clock signal CKLFD, wherein the delay amount of the second delayed low-frequency clock signal CKLFD relative to the low-frequency clock signal CKLF is greater than the delay amount of the first delayed low-frequency clock signal relative to the low-frequency clock signal CKLF.

[0051] The clock phase detector with gating function of the present application mainly includes two clock gating logics, two phase detectors formed by cross-coupling of NAND gates, two inverters, a trigger and a delay module for sampling output results. The clock gating logic (first clock gating logic) above is used to obtain the phase of the high-frequency clock signal at the rising edge of the low-frequency clock signal, and keep it at a high level and no longer flip, so that the high-frequency clock signal is approximately transformed into a low-frequency clock signal with the same phase information. The clock gating logic (second clock gating logic) below is used for delay matching. Therefore, the two same low-frequency signals of the output terminals N1 and N2 nodes of the two clock gating logics are then processed by the phase detector formed by cross-coupling of two NAND gates to obtain a result that characterizes the phase relationship of the signal. The two inverters are used to adjust the logic value and load matching, and finally the trigger is used to sample the result, and the delay module is used to obtain a suitable trigger sampling clock.

[0052] In one embodiment, the first clock gating logic 101 and the second clock gating logic 102 have the same circuit structure, each having a different gating signal GATE and a clock input signal CKIN, and outputting a corresponding clock output signal CLKOUT according to the gating signal GATE and the clock input signal CKIN. The gating signal GATE and the clock input signal CKIN of the first clock gating logic 101 receive the low-frequency clock signal CKLF and the high-frequency clock signal CKHF respectively, while the gating signal GATE and the clock input signal CKIN of the second clock gating logic 102 both receive the low-frequency clock signal CKLF.

[0053] like Figure 3 As shown, the first clock gating logic 101 and the second clock gating logic 102 each include: a first MOS transistor M1 , a second MOS transistor M2 , a third MOS transistor M3 , a fourth MOS transistor M4 , a third inverter 109 , and a second delay unit 110 . The source of the first MOS transistor M1 is coupled to the voltage source VDD, the drain of the first MOS transistor M1 is coupled to the source of the second MOS transistor M2, the gate of the first MOS transistor M1 and the input of the second delay unit 110 are coupled to the gate signal GATE, the gate of the second MOS transistor M2 and the gate of the third MOS transistor M3 are coupled to the clock input signal CKIN, the drain of the second MOS transistor M2 and the drain of the third MOS transistor M3 are connected and coupled to the drain of the fourth MOS transistor M4 and the input of the third inverter 109, the source of the third MOS transistor M3 is coupled to the ground, the output of the second delay unit 110 is coupled to the gate of the fourth MOS transistor M4, the source of the fourth MOS transistor M4 is coupled to the ground, and the output of the third inverter 109 outputs the clock output signal CLKOUT.

[0054] In one embodiment, the first MOS transistor M1 and the second MOS transistor M2 are PMOS transistors, and the third MOS transistor M3 and the fourth MOS transistor M4 are NMOS transistors.

[0055] In one embodiment, the gate signal GATE of the first clock gating logic 101 receives the low-frequency clock signal CKLF, and the clock input signal CKIN receives the high-frequency clock signal CKHF. At the rising edge of the low-frequency clock signal CKLF, the first MOS transistor M1 of the first clock gating logic 101 is turned off, so that the first clock gating logic 101 maintains the most recent rising edge transition of the high-frequency clock signal CKHF, and the output end of the third inverter 109 of the first clock gating logic 101 outputs a constant non-flipping signal until the gate signal GATE (i.e., the low-frequency clock signal CKLF) has a falling edge transition.

[0056] The clock input signal CKIN passes through an inverter with a gating function (ie, the second MOS transistor M2 and the third MOS transistor M3) to the A1 node, and the A1 node can be reset to a low level by the gating signal GATE, and finally outputs CLKOUT after adjusting the logic value through the third inverter 109.

[0057] Figure 4 The schematic diagram of the working process of the clock gating logic is shown. When the gate signal GATE jumps from low level "0" to high level "1", the pull-up channel of the clock input signal CKIN is cut off, thereby preventing the subsequent jump of the clock input signal CKIN from causing the rising edge jump at point A1. Therefore, the A1 node can only receive the jump of the clock input signal CKIN before the rising edge of the gate signal GATE arrives, and then is kept pulled down to "0" by the gate signal GATE. Finally, the clock output signal CKOUT will only have one rising edge jump near the rising edge of the gate signal GATE, thereby making the jump frequency of the clock input signal CKIN at a fixed time consistent with the gate signal GATE.

[0058] In one embodiment, at the rising edge of the low-frequency clock signal CKLF, if the high-frequency clock signal CKHF has changed from a low level to a high level, the drain of the second MOS transistor M2 and the drain of the third MOS transistor M3 of the first clock gating logic 101 output a low level and remain at a low level, and the output end of the third inverter 109 of the first clock gating logic 101 outputs a constant high level signal that does not flip. In another embodiment, if the high-frequency clock signal CKHF has changed from a high level to a low level, the drain of the second MOS transistor M2 and the drain of the third MOS transistor M3 of the first clock gating logic 101 output a high level, and after a certain delay, the first NAND gate and the second NAND gate complete the phase comparison, and the drain output of the third MOS transistor M3 of the first clock gating logic 101 is pulled down by the fourth transistor M4 and remains at a low level, and the output end of the third inverter 109 of the first clock gating logic 101 outputs a constant high level signal that does not flip.

[0059] In one embodiment, near the rising edge of the low-frequency clock signal CKLF, the output terminal of the third inverter 109 of the first clock gating logic 101 outputs a constant high-level signal that does not flip.

[0060] In one embodiment, both the gating signal GATE and the clock input signal CKIN of the second clock gating logic 102 receive the low-frequency clock signal CKLF, and the output terminal of the third inverter 109 of the second clock gating logic 102 outputs the first delayed low-frequency clock signal.

[0061] Figure 5 The working process diagram of the phase detector with clock gating function is shown. When the rising edge of the high-frequency clock signal CKHF takes precedence over the low-frequency clock signal CKLF, the input node N1 of the NAND gate type phase detector will flip from "0" to "1", while the N2 node remains at a low level. The NAND gate type phase detector will jump from the reset state to the comparison state, so that the N3 node jumps to "0", completing the phase detection, and the phase detection result "1" is obtained through the inverter. The output signal OUT is high level, which also means that the rising edge phase of the high-frequency clock signal CKHF takes precedence over the rising edge of the low-frequency clock signal CKLF, otherwise the result is low level.

[0062] When the rising edge of the high-frequency clock signal CKHF lags behind the low-frequency clock CKLF, the input node N1 of the NAND phase detector will flip from "1" to "0", while the N2 node remains at a low level and flips to "1" after the first delayed CKLF signal rising edge arrives. The N3 node of the NAND phase detector remains at "1", and the phase detection result "0" is obtained through the inverter. The output signal OUT is a low level, which also indicates that the rising edge phase of the high-frequency clock signal CKHF lags behind the rising edge of the low-frequency clock signal CKLF.

[0063] The present application also discloses a high-speed analog-to-digital / digital-to-analog conversion system, comprising: a clock phase detector with a gating function as described above, a synchronous reset signal generator, and an analog-to-digital / digital-to-analog converter. The synchronous reset signal generator is coupled to the output end of the clock phase detector. The analog-to-digital / digital-to-analog converter is coupled to the output end of the synchronous reset signal generator and the high-frequency clock signal. In one embodiment, the analog-to-digital / digital-to-analog converter includes multiple channels of analog-to-digital / digital-to-analog conversion units.

[0064] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0065] The term "coupled to" and its derivatives may be used herein. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

[0066] This specification includes combinations of the various embodiments described herein. Individual references to an embodiment (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated as mutually exclusive or it is clear to a person skilled in the art that they are mutually exclusive. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0067] All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

Claims

1. A clock phase detector with a gating function, characterized in that: include: a first clock gating logic, wherein the first clock gating logic receives a low-frequency clock signal and a high-frequency clock signal respectively and obtains rising edge phase information of the high-frequency clock signal at a rising edge of the low-frequency clock signal, and makes the high-frequency clock signal no longer flip before a low level of the low-frequency clock signal arrives; a second clock gating logic, the second clock gating logic being used to delay and output a first delayed low-frequency clock signal; First and second NAND gates, one input terminal of the first NAND gate is coupled to the output terminal of the first clock gating logic, and the other input terminal is coupled to the output terminal of the second NAND gate, one input terminal of the second NAND gate is coupled to the output terminal of the second clock gating logic, and the other input terminal is coupled to the output terminal of the first NAND gate; a first inverter, wherein an input terminal of the first inverter is coupled to an output terminal of the first NAND gate; a second inverter, wherein an input terminal of the second inverter is coupled to an output terminal of the second NAND gate; as well as A trigger, wherein a data terminal of the trigger is coupled to an output terminal of the first inverter, and a clock terminal of the trigger receives a second delayed low-frequency clock signal.

2. The clock phase detector according to claim 1, characterized in that: Also includes: A first delay unit, wherein an input end of the first delay unit receives the low-frequency clock signal and outputs a second delayed low-frequency clock signal, wherein a delay amount of the second delayed low-frequency clock signal relative to the low-frequency clock signal is greater than a delay amount of the first delayed low-frequency clock signal relative to the low-frequency clock signal.

3. The clock phase detector according to claim 1, characterized in that: The first clock gating logic and the second clock gating logic each include: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a third inverter, and a second delay unit; The source of the first MOS transistor is coupled to a voltage source, the drain of the first MOS transistor is coupled to the source of the second MOS transistor, the gate of the first MOS transistor and the input of the second delay unit are both coupled to a gating signal, the gate of the second MOS transistor and the gate of the third MOS transistor are both coupled to a clock input signal, the drain of the second MOS transistor is connected to the drain of the third MOS transistor and coupled to the drain of the fourth MOS transistor and the input of the third inverter, the source of the third MOS transistor is coupled to the ground, the output of the second delay unit is coupled to the gate of the fourth MOS transistor, the source of the fourth MOS transistor is coupled to the ground, and the output of the third inverter outputs a clock output signal.

4. The clock phase detector according to claim 3, characterized in that: The gating signal of the first clock gating logic receives the low-frequency clock signal, and the clock input signal receives the high-frequency clock signal; at the rising edge of the low-frequency clock signal, the first MOS transistor of the first clock gating logic is turned off, so that the first clock gating logic maintains the most recent rising edge transition of the high-frequency clock signal, and the output end of the third inverter of the first clock gating logic outputs a constant non-flipping signal until the gating signal has a falling edge transition.

5. The clock phase detector according to claim 4, characterized in that: At the rising edge of the low-frequency clock signal, if the high-frequency clock signal has jumped from a low level to a high level, the drain of the second MOS transistor and the drain of the third MOS transistor output a low level and remain at a low level, and the output end of the third inverter of the first clock gating logic outputs a constant high-level signal that does not flip; if the high-frequency clock signal has jumped from a high level to a low level, the drain of the second MOS transistor and the drain of the third MOS transistor output a high level, and after a certain delay, the first and second NAND gates complete the phase comparison, the drain output of the third MOS transistor is pulled down by the fourth transistor and remains at a low level, and the output end of the third inverter of the first clock gating logic outputs a constant high-level signal that does not flip.

6. The clock phase detector according to claim 5, characterized in that: Near the rising edge of the low-frequency clock signal, the output end of the third inverter of the first clock gating logic outputs a constant high-level signal that does not flip.

7. The clock phase detector according to claim 3, characterized in that: The gating signal and the clock input signal of the second clock gating logic both receive the low-frequency clock signal, and the output end of the third inverter of the second clock gating logic outputs the first delayed low-frequency clock signal.

8. The clock phase detector according to claim 3, characterized in that: The first MOS transistor and the second MOS transistor are PMOS transistors, and the third MOS transistor and the fourth MOS transistor are NMOS transistors.

9. A high-speed analog-to-digital / digital-to-analog conversion system, characterized in that: include: A clock phase detector with a gating function as claimed in any one of claims 1 to 8; a synchronous reset signal generator coupled to an output terminal of the clock phase detector; as well as An analog-to-digital / digital-to-analog converter is coupled to the output terminal of the synchronous reset signal generator and the high-frequency clock signal.

10. The high-speed analog-to-digital / digital-to-analog conversion system according to claim 9, characterized in that: The analog-to-digital / digital-to-analog converter includes multiple channels of analog-to-digital / digital-to-analog conversion units.

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