System and method for clock frequency monitoring

Abstract

The present disclosure relates to systems and methods for clock frequency monitoring. An apparatus can include a first circuit configured to receive a reference clock signal and provide a first signal in response to a first number of cycles of the reference clock signal, and a second circuit configured to receive a sample clock signal and provide a second signal in response to the first signal. The second signal indicates a second number of cycles of the sample clock signal that occur during the first number of cycles of the reference clock signal. The apparatus can also include a third circuit configured to determine a ratio of a first frequency of the reference clock signal to a second frequency of the sample signal using the second signal.

Description

Technical Field

[0001] This disclosure generally relates to systems and methods for clock monitoring, including but not limited to systems and methods for high-precision clock frequency calculation and tracking operations. Background Technology

[0002] Over the past few decades, the market for electronic devices has grown exponentially due to the use of portable devices and the increasing connectivity, data transmission, and data storage between various devices. Many modern electronic devices rely on clock signals. For example, a System-on-a-Chip (SoC) typically uses one or more clock signals to implement a wide range of functions and cover different operating modes. When data rates reach the gigabits per second range, the accuracy associated with clock signals (e.g., data clock signals) can affect system operation. For instance, poor accuracy related to the frequency of a clock signal can adversely affect communication performance and prevent the system from meeting performance specifications. Summary of the Invention

[0003] In one aspect, this disclosure provides an apparatus comprising: a first counter configured to receive a reference clock signal and provide a first signal in response to a first cycle number of the reference clock signal; a second counter configured to receive a sample clock signal and provide a second signal in response to the first signal, wherein the second signal indicates a second cycle number of the sample clock signal occurring during the first cycle number of the reference clock signal; and circuitry responsive to the first signal and the second signal to determine a ratio of a first frequency of the reference clock signal to a second frequency of the sample clock signal.

[0004] In another aspect, this disclosure provides a method comprising: providing a first signal in response to a first number of cycles of a reference clock signal; providing a second signal in response to the first signal, wherein the second signal indicates a second number of cycles of a sample clock signal occurring during the first number of cycles of the reference clock signal; determining a difference between a first sample of the second signal at a first time and a second sample of the second signal at a second time; and determining a ratio of a first frequency of the reference clock signal to a second frequency of the sample clock signal in response to the difference.

[0005] In another aspect, this disclosure provides an apparatus comprising: a first circuit configured to receive a reference clock signal and provide a first signal in response to a first number of cycles of the reference clock signal; a second circuit configured to receive a sample clock signal and provide a second signal in response to the first signal, wherein the second signal indicates a second number of cycles of the sample clock signal occurring during the first number of cycles of the reference clock signal; and a third circuit configured to use the second signal to determine a ratio of a first frequency of the reference clock signal to a second frequency of the sample clock signal. Attached Figure Description

[0006] The various objects, aspects, features, and advantages of this disclosure will become more apparent and better understood through a detailed description taken in conjunction with the accompanying drawings, wherein the same reference numerals identify corresponding elements throughout. In the drawings, the same reference numerals generally denote the same, functionally similar, and / or structurally similar elements.

[0007] Figure 1 It is a block diagram depicting an exemplary system including a clock frequency calculator according to one or more embodiments;

[0008] Figure 2 According to one or more embodiments Figure 1 A more detailed block diagram of the clock frequency calculator described in the document;

[0009] Figure 3 This illustrates, according to one or more embodiments, that when the reference clock frequency is lower than the target clock frequency, the following occurs: Figure 1 The waveform diagram of the ratio of the target clock signal frequency to the reference clock signal frequency calculated by the clock frequency calculator described in the text, relative to the number of cyclic samples.

[0010] Figure 4 This illustrates, according to one or more embodiments, that when the reference clock frequency is higher than the target clock frequency, the... Figure 1 The waveform of the ratio of the target clock signal frequency to the reference clock signal frequency calculated by the clock frequency calculator described in the text, relative to the number of cyclic samples.

[0011] Figure 5 This illustrates, according to one or more embodiments, the use of a varying target clock signal frequency, by Figure 1 The timing diagram of the ratio of the target clock signal frequency to the reference clock signal frequency calculated by the clock frequency calculator described in the text, relative to the number of cyclic samples.

[0012] Figure 6 It is a block diagram depicting an exemplary system according to one or more embodiments, the exemplary system including a clock frequency calculator disposed in the system.

[0013] Figure 7 It is a block diagram depicting an exemplary system according to one or more embodiments, the exemplary system including a clock frequency calculator disposed outside the system.

[0014] Details of various embodiments of the method and system are set forth in the accompanying drawings and the following description. Detailed Implementation

[0015] For the purpose of reading the description of the various embodiments described below, the following description of the sections of the specification and their corresponding contents may be helpful. According to some embodiments, the systems and methods described herein can be used in network environments, storage environments, communication environments, control environments, sensor environments, and / or computing environments that utilize clock signals. In some embodiments, the systems and methods for clock monitoring are used to ensure high-frequency, high-precision clock signals. Although this disclosure may refer to aspects of detailed design, performance, and specifications, this disclosure is by no means limited to these aspects.

[0016] In some embodiments, the system and method monitor the clock domain or signals of an integrated circuit (e.g., a packaged IC or a SoC). The system and method can be used in any clock monitoring application and can be applied to tracking processing, voltage, and temperature (PVT) changes. The system and method can be used to monitor the speed of an on-chip ring oscillator. The system and method can be used on IC dies, SoCs, printed circuit board assemblies, stand-alone devices, computing devices, etc.

[0017] In some embodiments, the system and method perform high-precision clock frequency measurement and continuous tracking of one or more signals. In some embodiments, the accuracy of a high-quality clock signal used in a communication system is monitored. For example, the correct frequency of a clock signal provided by an 18-bit resolution PLL used in coherent optical communication applications is monitored. In some embodiments, on-chip circuitry or a device accurately measures the clock frequency. In some embodiments, the system and method are used to continuously track on-chip or off-chip frequency drift and changes.

[0018] In some embodiments, the system and method provide greater accuracy than systems that directly compare a target clock signal to a known reference clock signal. In some embodiments, the system and method do not require prior knowledge of the frequency ratio between the target clock signal and the known reference clock signal. In some embodiments, the system and method provide adaptive clock monitoring for a wide range of use cases. In some embodiments, the system and method are more of a systemic solution than a particular one.

[0019] In some embodiments, the systems and methods do not rely on phase-locked loop (PLL) solutions and use integer dividers (e.g., integer dividers are predominantly used in the circuit). In some embodiments, the systems and methods meet frequency resolution, range, and low jitter requirements that are difficult to achieve using conventional PLL cores. In some embodiments, clock frequency calculators are provided in silicon products, application-specific integrated circuits (ASICs), digital signal processors, programmable logic circuits, SoCs, or standard products. In some embodiments, clock frequency calculators provide very fine ratio-based frequency resolution, use small silicon areas, and are scalable and portable to newer integrated circuit processes. In some embodiments, the clock frequency calculation systems and methods are used in modern high-speed and energy-efficient data communication and processing systems, including but not limited to any backplane, serializer / deserializer (SERDES), Ethernet physical layer (PHY), optical transceivers, coherent transceivers, digital signal processor (DSP) modules, input / output (I / O) interfaces, multi-core processors, memory, power management, and wireless transceivers.

[0020] Some embodiments relate to an apparatus. The apparatus includes: a first counter configured to receive a reference clock signal and provide a first signal in response to a first cycle number of the reference clock signal; and a second counter configured to receive a sample clock signal and provide a second signal in response to the first signal. The second signal indicates a second cycle number of the sample clock signal occurring during the first cycle number of the reference clock signal. The circuitry is configured to determine a ratio of a first frequency of the reference clock signal to a second frequency of the sample signal in response to the first signal and the second signal.

[0021] In some embodiments, the apparatus includes a calculator configured to subtract the second signal at a first time from the second signal at a second time to provide a difference. In some embodiments, the circuitry is configured to determine the ratio in response to the difference. In some embodiments, the circuitry is configured to determine the ratio in response to samples of the difference over time.

[0022] In some embodiments, the circuit includes an infinite impulse response filter. In some embodiments, the circuit determines the ratio according to the following equation: Y(n) / (K+1)=(Q((X(n)–Y(n-1))+Y(n-1))) / (K+1), where Y(n) / (K+1) is the ratio at sample n, X(n) is the difference at sample n, and Y(n-1) / (K+1) is the ratio at sample n-1. In some embodiments, the circuit determines the ratio according to the following equation: Y(n)=(Q(α((X(n)–Y(n-1)))+Y(n-1)) / (K+1), where Y(n) / (K+1) is the ratio at sample n, X(n) is the difference at sample n, Q is the quantization function, α is the programmable bandwidth, and Y(n-1) / (K+1) is the ratio at sample n-1.

[0023] In some embodiments, the second counter is configured as a free-running counter. In some embodiments, the first counter is configured as a periodic counter. In some embodiments, the difference is an integer value.

[0024] Some embodiments relate to a method. The method includes: providing a first signal in response to a first cycle number of a reference clock signal; providing a second signal in response to the first signal, wherein the second signal indicates a second cycle number of a sample clock signal occurring during the first cycle number of the reference clock signal; and determining a difference between a first sample of the second signal at a first time and a second sample of the second signal at a second time. The method further includes determining a ratio of a first frequency of the reference clock signal to a second frequency of the sample signal in response to the difference.

[0025] In some embodiments, a sample may refer to the value of a signal (e.g., data) acquired at a specific time. In some embodiments, the ratio is related to the following expression: Q(X(n)–Y(n-1))+Y(n-1))) / (K+1), where Y(n) / (K+1) is the ratio provided as a fraction at sample n, X(n) is the difference at sample n, and Y(n-1) / (K+1) is the ratio at sample n-1.

[0026] In some embodiments, the first signal is provided by a first counter configured as a periodic counter. In some embodiments, the difference is an integer value, and the second signal is provided by a second counter configured as a free-running counter. In some embodiments, an α parameter is used to determine the ratio, wherein the α parameter affects the settling time. In some embodiments, the α parameter is dynamically adjusted.

[0027] Some embodiments relate to an apparatus comprising: a first circuit configured to receive a reference clock signal and provide a first signal in response to a first number of cycles of the reference clock signal; and a second circuit configured to receive a sample clock signal and provide a second signal in response to the first signal. The second signal indicates a second number of cycles of the sample clock signal occurring during the first number of cycles of the reference clock signal. The apparatus further comprises a third circuit configured to use the second signal to determine a ratio of a first frequency of the reference clock signal to a second frequency of the sample signal.

[0028] In some embodiments, the first circuit, the second circuit, and the third circuit are disposed on the same integrated circuit die providing the sample clock signal. In some embodiments, the first circuit, the second circuit, and the third circuit are disposed on an integrated circuit die separate from another integrated circuit die providing the sample clock signal.

[0029] In some embodiments, the third circuit includes a calculator circuit configured to provide the difference between a first sample of the second signal at a first time and a second sample of the second signal at a second time.

[0030] Before discussing specific embodiments of this solution, the methods and systems described herein can be used with a variety of computing, storage, communication, or networking devices. Network devices may include or communicate with SANs, security adapters, or converged Ethernet network adapters (CANs). These devices may include access points, one or more wireless communication devices, network hardware components, including but not limited to laptops, tablets, personal computers, wearable devices, vehicles (e.g., automobiles, drones, intelligent vehicles, robotic units, etc.), sensors, media systems, gaming systems, communication systems, and / or cellular telephone devices. In some embodiments, the network may be an ad hoc network, an infrastructure wireless network, a wired network, a subnet environment, etc. Network components include, but are not limited to, routers, gateways, switches, bridges, modems, system controllers, appliances, etc.

[0031] The network connection may include any type and / or form of network, and may include any of the following: point-to-point network, broadcast network, telecommunications network, data communication network, computer network. The network topology may be a bus, star, or ring network topology. The network may have any such network topology known to those skilled in the art as capable of supporting the operations described herein. In some embodiments, different types of data may be transmitted via different protocols. In other embodiments, the same type of data may be transmitted via different protocols.

[0032] The aspects of the operating environment and components described above will become apparent in the context of the systems and methods disclosed herein.

[0033] refer to Figure 1 System 100 is any type of electronic device or group of devices. System 100 may be disposed on an integrated circuit (IC) die (e.g., on one or more IC dies). System 100 can be used in any electronic and / or optical application. System 100 can be used in and / or with the devices and networks discussed above.

[0034] In some embodiments, system 100 includes a clock frequency processor or clock frequency calculator 110 having a reference clock signal input 112, a target clock signal input 114, and a ratio output 122. System 100 may include multiple clock frequency calculators similar to clock frequency calculator 110 (e.g., one for each monitored clock signal). In some embodiments, clock frequency calculator 110 is configured to receive a target clock signal at target clock signal input 114, a reference clock signal at reference clock signal input 112, and provide a ratio of the frequencies of the reference clock signal to the target clock signal at ratio output 122. In some embodiments, the target clock signal may refer to a clock signal to be monitored or measured with respect to the reference clock signal. In some embodiments, the target clock signal may refer to a clock signal used to monitor or measure the target clock signal. In some embodiments, the reference clock signal and the target clock signal have frequencies different from each other. In some embodiments, the ratio is a fractional value, which is the ratio of the frequencies of the reference clock signal to the target clock signal (e.g., represented by an M-bit integer part and an N-bit fractional part, where M and N are any integers). The ratio can be used to adjust the target clock signal, perform other correction actions, or provide warnings.

[0035] In some embodiments, the clock frequency calculator 110 uses a bandwidth parameter or setting (e.g., BW). The bandwidth parameter can be input to or generated by the clock frequency calculator 110. The bandwidth parameter controls the measurement accuracy and convergence time of the ratio at the ratio output 122. In some embodiments, the bandwidth parameter is a digital value that allows fine-tuning of the measurement speed and accuracy. The bandwidth parameter can be adjusted while the clock frequency calculator 110 is operating.

[0036] In some embodiments, a reference clock signal input 112 is coupled to a signal source 124. The signal source 124 provides the reference clock signal, and in some embodiments, the signal source 124 is a crystal integrated circuit that provides a reference frequency signal at a given frequency. The signal source 124 can be any type of device for providing the reference clock signal (e.g., a square wave or sine wave oscillator, a phase-locked loop-based source, a ring oscillator, etc.). In some embodiments, the reference clock signal can be provided at a frequency from 5 MHz to 400 MHz (e.g., 100 MHz). In some embodiments, the reference clock signal and the target clock signal can be a square wave or other signals provided at a given frequency for driving gates, processors, or other logic. In some embodiments, the target clock signal can have a frequency between 1 MHz and 6 GHz. In some embodiments, the target clock signal has a frequency less than the target clock signal frequency. In some embodiments, the target clock signal has a frequency greater than the target clock signal frequency. The reference clock signal and the target clock signal can have any duty cycle (e.g., approximately 50%). In some embodiments, the signal source 124 provides a relatively stable and accurate frequency to the reference clock signal (e.g., a frequency suitable for measuring the target clock signal). In some embodiments, the reference clock signal is provided by a precise and accurate clock signal source at a known frequency.

[0037] In some embodiments, the clock frequency calculator 110 is a high-speed macro, processor, unit, circuit, logic, or other implementation that provides a ratio of the frequencies of a reference clock signal to a target clock signal in response to a reference clock signal and a target clock signal. In some embodiments, the clock frequency calculator 110 advantageously does not require an integer relationship between the reference clock signal and the target clock signal. In some embodiments, the clock frequency calculator 110 uses a slower reference clock signal (e.g., 5 MHz) to accurately measure a high-speed target clock signal (e.g., 210.33 MHz) with minimal hardware and computational cost. In some embodiments, the ratio determined by the clock frequency calculator 110 may be a fractional reading extended according to application requirements. In some embodiments, the fractional reading may be extended almost infinitely.

[0038] refer to Figure 2 The clock frequency calculator 110 includes counters 132 and 134, a delay circuit 136, an adder or calculator 138, and a mean tracking module 140. Counter 134 includes a clock input 113 coupled to a reference clock signal input 112, and counter 132 includes a clock input 115 coupled to a target clock signal input 114. Counters 132 and 134 are coupled to the mean tracking module 140, which provides a ratio of the frequencies of the reference clock signal to the target clock signal at a ratio output 122.

[0039] In some embodiments, counter 134 is a K-periodic counter that provides a strobe signal at output 142 every K cycles of a reference clock signal. Counter 134 can be any type of circuitry used to provide the strobe signal. In some embodiments, counter 134 is a sequential digital logic circuit. Counter 132 can utilize a cascaded array of flip-flops. Counter 134 can utilize a reset input, set input, load input, enable input, etc. A counter can refer to any type of circuitry used to provide a periodic signal in response to a number of cycles of one or more other signals (e.g., a clock signal). In some embodiments, a cycle can refer to the period of a signal, or a quantity thereof that is the amount of time between two pulses of the signal (e.g., between each leading edge or each falling edge of a square wave clock signal).

[0040] In some embodiments, counter 134 provides a strobe signal at each fixed time interval T (K cycles of the reference clock signal, where K is an integer). In some embodiments, the strobe signal may be a pulse or square wave signal. In some embodiments, the value K may be a fixed value or a programmed value. The value K may be a predetermined constant value. The strobe signal is a segmented version of the control signal used as counter 132 at input 143 and mean tracking module 140 at input 141.

[0041] In some embodiments, counter 132 is a free-running counter that provides a signal at output 156 in response to a target clock signal at clock input 115 and a strobe signal at input 143. In some embodiments, a free-running counter may refer to a counter that counts to a maximum number, overflows to zero, and starts counting up again. Counter 132 is configured to produce an output that cycles from 0 to N-1, where N is the maximum count at which counter 132 ends counting and cycles back to 0. Counter 132 may be any type of circuitry used to provide a signal at output 156. In some embodiments, counter 132 is a sequential digital logic circuit. Counter 132 may utilize a cascaded array of flip-flops. Counter 132 may utilize a reset input, a set input, a load input, an enable input, etc. In some embodiments, counters 132 and 134 may be macros, cells, circuits, logic, or other implementations that provide the counting operations described above.

[0042] Counter 132 can be configured to count pulses of a target clock signal until a pulse of a strobe signal is provided to input 143. In some embodiments, counter 132 counts the number of pulses during a time interval T or K clock cycles of a reference clock signal. The number of pulses of the target clock signal is related to the frequency of the target clock signal (e.g., pulses per second equal to a frequency in Hz). The number of pulses of the reference clock signal is related to the frequency of the reference clock signal (e.g., pulses per second equal to a frequency in Hz). In some embodiments, counter 132 provides a count value of the number of pulses counted at output 156 and is reset to zero by a pulse of the strobe signal provided to input 143. In some embodiments, the count value provided at output 156 of counter 132 is an unsigned integer value. The count value at output 156 can vary during operation. For example, the count value can vary due to clock domain crossover (CDC) associated with the reference clock signal and the target clock signal. CDC can occur at any time data is transferred from a flip-flop or latch driven by one clock signal to a flip-flop or latch driven by another clock signal.

[0043] In some embodiments, calculator 138 is configured as a subtractor. In some embodiments, calculator 138 uses modulo-N subtraction to subtract the digital value at output 156 from the digital value from delay circuit 136. Delay circuit 136 provides a K-delay such that the maximum value at output 56 (e.g., the value after K cycles) is subtracted from the previous maximum value at output 56 (the value after the previous K cycles). Delay circuit 136 may be any circuitry used to provide appropriate sample selection or for calculator 138. Calculator 138 subtracts the value at input 148 from output 156 from the value at input 154 from delay circuit 136 and provides the difference to input 149. In some embodiments, the difference is an unsigned integer value. In some embodiments, calculator 138 provides modulo-N subtraction that always produces a positive value. In some embodiments, delay circuit 136 is a latch-based storage element timed by a strobe signal, and stores a value at output 156 of counter 132 every K cycles.

[0044] In some embodiments, the mean tracking module 140 is coupled to the calculator 138 and receives the difference at input 149. The mean tracking module 140 provides a fractional value (e.g., Y(n)) indicating the frequency of the target signal to the frequency of the reference signal. In some embodiments, the mean tracking module 140 uses an averaging process with an iterative method. In some embodiments, multiplying the fractional value by the frequency of the reference signal can be used to determine the frequency of the target signal in real-time or near real-time. In some embodiments, the fractional value is the mean or average of integer values ​​(e.g., differences) provided by the calculator 138. In some embodiments, the mean tracking module 140 is configured to calculate the average target clock cycle count over a time interval T using an infinite impulse response (IIR) filter. In some embodiments, the mean tracking module 140 executes the following equation: Y(n) = Q(α(X(n) – Y(n-1))) + Y(n-1), where in some embodiments, Y(n) is the fractional real-valued average clock cycle count at sample n, Q is a quantization function, α is a programmable bandwidth (e.g., BW), X(n) is the difference provided at output 144 (e.g., a value provided as input to an IIR filter), and Y(n-1) is the fractional real-valued average clock cycle count at sample n-1. In some embodiments, Y(n) / (K+1) is the fractional value at output 122 at sample n. Y(n) can be calculated using X(n) and previous values ​​of Y(n).

[0045] In some embodiments, the quantization function provides an actual fractional limit (e.g., 10 to 30 bits, 20 bits) for the value Y(n). In some embodiments, quantization can refer to the operation of reducing a large set of input values ​​to a smaller set of output values, typically having a finite number of elements. Rounding and truncation are examples of quantization. The value α is optional or fixed and affects tracking speed (e.g., settling time) and stable measurement accuracy. In some embodiments, the higher the value, the faster the settling time. In some embodiments, the value α can be a number from 0 to 1. In some embodiments, the settling time can refer to the time period during which the value reaches convergence. In some embodiments, the settling time is the time required for the ratio to reach a stable state within a given tolerance band. In some embodiments, an infinite impulse response filter can refer to an electronic filter (e.g., a digital filter) with an infinite impulse response. In some embodiments, the α parameter can refer to a bandwidth value that affects measurement accuracy and convergence time.

[0046] In some embodiments, the ratio Y(n) / (K+1) provided by the mean tracking module 140 can be expressed by the following equation: Y(n) / (K+1) = frequency of the target clock signal / frequency of the reference clock, which is equal to (r int [7:0]+r fraction [19:10]*2 -20 ) / (K+1), where rint [7:0] represents the integer part of Y(n) (e.g., 8 bits), r fraction [19:0] represents the fractional portion of Y(n) (e.g., 20 bits), and K is equal to the number of cycles of the reference clock signal in the strobe signal (if Y(n) is a complement of 2). The number of bits discussed above is exemplary. In some embodiments, the precision of Y(n) and Y(n) / (K+1) can be increased by increasing the data width of the fixed-point representation of Y(n) (e.g., the α value), and the stabilization speed can be increased by decreasing the data width of the fixed-point representation of Y(n) (e.g., the α value). In some embodiments, the mean tracking module 140 may be a macro, cell, circuit, logic, processor, digital filter, or other implementation that provides the fractional value calculation operations as described above in some embodiments. In some embodiments, the mean tracking module may include a digital accumulator, adder, subtractor, multiplier, filter, divider, or other logic for calculating Y(n) / (K+1) at output 122. In some embodiments, the output of calculator 138 is used to calculate the real-valued average count of the cycles of the sample clock signal in the cycle of the strobe signal. In some embodiments, the real-valued average count may refer to at least a partial expression as the average of fractions.

[0047] refer to Figure 3 Waveform 210 represents the clock frequency calculator 110 ( Figure 1 Y(n) / (K+1) is calculated for a target clock signal with a frequency of 100 MHz and a K value of 11, and a reference clock signal with a frequency of 1.111 MHz. The frequency of the target clock signal is faster or greater than the frequency of the reference clock signal. X-axis 202 represents the number of K clock cycles of the time or reference clock signal, and Y-axis 204 represents the ratio (e.g., Y(n) / (K+1)). The expected ratio is 20.088888, and the actual value is 20.088867. In some embodiments, the use of frequency calculator 110 allows for a more accurate understanding of the frequency of the target clock signal (e.g., 0.000105% more accurate than the expected frequency). In some embodiments, waveform 210 converges 211 after approximately 300K cycles of a reference clock signal indicating a stable measurement.

[0048] refer to Figure 4Waveform 220 represents Y(n) / (K+1) of a target clock signal with a frequency of 1.111 MHz and a K value of 249, and a reference clock signal with a frequency of 100 MHz. The frequency of the target clock signal is slower than or less than the frequency of the reference clock signal. The X-axis 224 represents the number of K clock cycles of the reference clock signal, and the Y-axis 224 represents the ratio (e.g., Y(n) / (K+1)). The expected ratio is 0.01111, and the actual value is 0.01110. In some embodiments, the use of a frequency calculator allows for a more accurate understanding of the frequency of the target clock signal (e.g., 0.09% more accurate than the expected frequency). In some embodiments, waveform 220 converges 225 at approximately 300K cycles of the reference clock signal, indicating that the measurement is stable.

[0049] refer to Figure 5 Waveform 250 represents the dynamically changing Y(n) / (K+1) of the target clock signal. The target clock signal has a frequency that changes from the frequency associated with levels 257, 259, and 261. Waveform 250 is associated with a K value of 19 and an α value bandwidth setting of 6, the α value bandwidth setting representing a number from 0 to 1. Level 257 represents a ratio (e.g., Y(n) / (K+1)). X-axis 252 represents the number of K clock cycles of the reference clock signal, and Y-axis 254 represents a ratio (e.g., Y(n) / (K+1)). The K value is represented by waveform 258, the α value is represented by waveform 262, and the clock frequency calculator 110 ( Figure 1 The enable signal is represented by waveform 264. In some embodiments, the enable signal can turn the clock frequency calculator 110 on and off.

[0050] refer to Figure 6 System 300 includes any type of electronic device or group of devices. System 100 may be disposed on an integrated circuit (IC) die. System 300 can be used in any electronic and / or optical application. System 300 can be used in and / or with the devices discussed above.

[0051] In some embodiments, system 300 includes a clock frequency calculator 308 coupled to a module 304 that provides a reference clock signal at output 314 and a module 306 that provides a target clock signal at output 316. Clock frequency calculator 308 is similar to clock frequency calculator 110. Figure 1 Modules 304 and 306 can be disposed in the same IC package, IC die, or substrate as system 300, or as off-chip devices.

[0052] refer to Figure 7System 400 includes any type of electronic device or group of devices, and includes systems 402 and 401. System 401 includes a clock frequency calculator 408. System 402 may be disposed on a different integrated circuit (IC) die than system 401. System 400 can be used in any electronic and / or optical application. System 400 can be used in and / or with the devices discussed above. Systems 401 and 402 may be in different IC packages or in the same IC package. In some embodiments, an integrated circuit die may refer to a chip or substrate containing an active integrated circuit device. An integrated circuit package may refer to a device containing one or more IC dies housed in a package. In some embodiments, an IC package may be a multi-chip package or a signal chip package.

[0053] In some embodiments, clock frequency calculator 408 is coupled to module 304, which provides a reference clock signal at output 414, and module 306, which provides a target clock signal at output 416. Modules 404 and 406 are provided as part of system 402. Clock frequency calculator 408 is similar to clock frequency calculator 110. Figure 1 Modules 404 and 406 may be disposed in the same IC package or substrate as system 402, or may be off-chip devices. In some embodiments, module 404 is integrated with system 401, and module 404 is integrated with module 406, or vice versa.

[0054] In some embodiments, a flip-flop may refer to a circuit element having two stable states that can be used to store binary data. In some embodiments, a latch may refer to a circuit element having two inputs and one output. In some embodiments, a clock signal may refer to a signal used to drive or be applied to another circuit. In some embodiments, a clock signal may be an electronic logic signal (voltage or current) that oscillates between high and low states at a certain frequency and is used to synchronize the operation of digital circuits. In some embodiments, a clock signal may be applied to all memory devices, flip-flops, and latches, causing them all to change states simultaneously. The clock signal is generated by an electronic oscillator called a clock generator and may be in the form of a square wave with a 50% duty cycle. Circuits synchronized using a clock signal may become active on the rising edge, falling edge, or, in the case of double data rate, on both the rising and falling edges of the clock cycle. In some embodiments, the clock signal may have a variable frequency. In some embodiments, a reference clock signal may refer to a clock signal used as a reference for comparison with another clock signal. In some embodiments, a sample clock signal may refer to a clock signal being measured.

[0055] It should be noted that certain paragraphs of this disclosure may refer to terms (e.g., "first" and "second") related to device signals, data, inputs, channels, etc., for the purpose of identifying or distinguishing them from one another or from another. These terms are not intended to merely relate entities (e.g., first input and second input) temporally or sequentially, but in some cases, these entities may contain such a relationship. These terms also do not limit the number of possible entities (e.g., devices) that can operate in the system or environment.

[0056] It should be understood that the system described above may provide any or multiple of those components. Furthermore, the system and method described above may provide one or more computer-readable programs or executable instructions, programmable circuits, or digital logic embodied on or in one or more articles of manufacture. The articles of manufacture may be floppy disks, hard disks, CD-ROMs, flash memory cards, PROMs, RAM, ROMs, ASICs, or magnetic tape. Generally, computer-readable programs may be implemented using any programming language such as LISP, PERL, C, C++, C#, PROLOG, or any bytecode language such as JAVA. The software program or executable instructions may be stored as object code on or in one or more articles of manufacture.

[0057] While the foregoing written description of the methods and systems enables those skilled in the art to make and use various embodiments of the methods and systems, those skilled in the art will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiments, methods, and examples herein. Therefore, the methods and systems should not be limited to the embodiments, methods, and examples described above, but rather to all embodiments and methods within the scope and spirit of this disclosure.

Claims

1. An apparatus comprising: A first counter is configured to receive a reference clock signal and provide a first signal in response to a first number of cycles of the reference clock signal; A second counter is configured to receive a sample clock signal and provide a second signal in response to the first signal, wherein the second signal indicates a second number of cycles of the sample clock signal that occurs during the first number of cycles of the reference clock signal; and A circuit that responds to the first signal and the second signal to determine the ratio of a first frequency of the reference clock signal to a second frequency of the sample clock signal. The ratio is determined using an α parameter, which affects the settling time required for the ratio to reach a steady state within a given tolerance band.

2. The apparatus of claim 1, further comprising a calculator configured to subtract the second signal at a first time from the second signal at a second time to provide a difference.

3. The apparatus of claim 2, wherein the circuitry is configured to determine the ratio in response to the difference.

4. The apparatus of claim 2, wherein the circuitry is configured to determine the ratio in response to samples of the difference over time.

5. The apparatus of claim 1, wherein the circuitry comprises an infinite impulse response filter.

6. The apparatus of claim 2, wherein the circuit is configured to determine the ratio according to the following equation: Y(n) / (K+1) = (Q(X(n) – Y(n-1) + Y(n-1)) / (K+1), where Q is a quantization function, Y(n) / (K+1) is the ratio provided at sample n, X(n) is the difference at sample n, Y(n) is the real-valued average count of the cycles of the sample clock signal in the cycle of the first signal at sample n, K is the first cycle number of the reference clock signal, and Y(n-1) is the real-valued average count of the cycles of the sample clock signal in the cycle of the first signal at sample n-1.

7. The apparatus of claim 2, wherein the ratio is related to the following expression: Y(n) = (Q(α(X(n) –Y(n-1)) + Y(n-1)) / (K+1), where Y(n) / (K+1) is the ratio provided as a fractional value at sample n, X(n) is the difference at sample n, Q is the quantization function, α is the programmable bandwidth, Y(n) is the real-valued average count of the cycles of the sample clock signal in the cycle of the first signal at sample n, K is the first cycle number of the reference clock signal, and Y(n-1) is the real-valued average count of the cycles of the sample clock signal in the cycle of the first signal at sample n-1.

8. The apparatus of claim 2, wherein the circuitry is configured to determine a real-valued average count of cycles of the sample clock signal in a cycle of the first signal in response to a sample of the difference, and wherein the difference is an integer value.

9. The apparatus of claim 1, wherein the second counter is configured as a free-running counter.

10. The apparatus of claim 1, wherein the first counter is configured as a periodic counter.

11. A method comprising: The first signal is provided in response to the first cycle number of the reference clock signal; A second signal is provided in response to the first signal, wherein the second signal indicates a second cycle number of the sample clock signal that occurs during the first cycle number of the reference clock signal; Determine the difference between a first sample of the second signal at a first time point and a second sample of the second signal at a second time point; and The ratio of a first frequency of the reference clock signal to a second frequency of the sample clock signal is determined in response to the difference. The ratio is determined using an α parameter, which affects the settling time required for the ratio to reach a steady state within a given tolerance band.

12. The method of claim 11, wherein the ratio is related to the following expression (Q(X(n) – Y(n-1)) + Y(n-1)) / (K+1), where Q is a quantization function, Y(n) / (K+1) is the ratio provided as a fractional value at sample n, X(n) is the difference at sample n, K is the first cycle number of the reference clock signal, and Y(n-1) / (K+1) is the ratio at sample n-1.

13. The method of claim 11, wherein the first signal is provided by a first counter configured as a periodic counter.

14. The method of claim 11, wherein the second signal is provided by a second counter configured as a free-running counter.

15. The method of claim 11, wherein the α parameter is dynamically adjusted.

16. An apparatus comprising: A first circuit is configured to receive a reference clock signal and provide a first signal in response to a first number of cycles of the reference clock signal; A second circuit is configured to receive a sample clock signal and provide a second signal in response to the first signal, wherein the second signal indicates a second number of cycles of the sample clock signal that occurs during the first number of cycles of the reference clock signal; and A third circuit is configured to use the second signal to determine the ratio of a first frequency of the reference clock signal to a second frequency of the sample clock signal. The ratio is determined using an α parameter, which affects the settling time required for the ratio to reach a steady state within a given tolerance band.

17. The apparatus of claim 16, wherein the first circuit, the second circuit, and the third circuit are disposed on the same integrated circuit die providing the sample clock signal.

18. The apparatus of claim 16, wherein the first circuit, the second circuit, and the third circuit are disposed on an integrated circuit die separate from another integrated circuit die providing the sample clock signal.

19. The apparatus of claim 16, wherein the third circuitry includes a calculator circuitry configured to provide the difference between a first sample of the second signal at a first time and a second sample of the second signal at a second time.

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