Imaging system comprising an HV driver for rolling clamp

Abstract

The present disclosure relates to HV drivers for rolling clamp in image sensors. An imaging system includes a pixel array having pixel circuits, each pixel circuit including a photodiode, a floating diffusion, a source follower transistor, and a row select transistor. The imaging system further includes rolling clamp RC drivers, each driver coupled to a gate terminal of the row select transistor of one of the pixel circuits, and each driver including first and second PMOS transistors coupled between a clamp voltage and the gate terminal of the row select transistor of the one of the pixel circuits, and first, second, and third NMOS transistors coupled between the clamp voltage and the gate terminal of the row select transistor of the one of the pixel circuits. The PMOS transistors and the NMOS transistors are coupled in parallel. The PMOS transistors are configured to provide an upper clamp voltage range, and the NMOS transistors are configured to provide a lower clamp voltage range.

Description

Technical Field

[0001] This disclosure generally relates to image sensors, and specifically, but not exclusively, to high dynamic range (HDR) complementary metal-oxide-semiconductor (CMOS) image sensors. Background Technology

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, surveillance cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, there is a growing expectation to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range) through device architecture design and image acquisition and processing. The technologies used to manufacture image sensors have continued to evolve rapidly. For example, the demand for higher resolution and lower power consumption has driven further miniaturization and integration of these devices.

[0003] A typical image sensor operates in response to incident image light from an external scene. The image sensor comprises an array of pixels with photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge in the process. The image charge generated by the pixel light can be measured as an analog output image signal on the bit lines, which varies according to changes in the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out as an analog image signal from the bit lines and converted into a digital value to produce a digital image (e.g., image data) representing the external scene. The analog image signal on the bit lines is coupled to a readout circuit that includes an input stage with an analog-to-digital converter (ADC) circuitry to convert those analog image signals from the pixel array into digital image signals. Summary of the Invention

[0004] In one aspect, this disclosure provides an imaging system comprising: a pixel array including a plurality of pixel circuits, wherein each pixel circuit includes: a photodiode configured to generate an image charge in response to incident light; a floating diffuser coupled to receive the image charge from the photodiode; a source follower transistor having a gate terminal coupled to the floating diffuser; and a row select transistor coupled to a source terminal of the source follower transistor; and a plurality of rolling clamp (RC) drivers, wherein each RC driver is coupled to the gate terminal of the row select transistor of one of the pixel circuits, wherein each RC driver has an on state and an off state, and wherein each RC driver includes: a first PMOS transistor coupled between a clamping voltage and the gate terminal of the row select transistor of one of the pixel circuits; and a second PMOS transistor coupled between the first PMOS transistor and the gate of the row select transistor of the one of the pixel circuits. Between terminals; a first NMOS transistor coupled between the clamping voltage and the gate terminal of the row selection transistor of one of the pixel circuits; a second NMOS transistor coupled between the first NMOS transistor and the clamping voltage; and a third NMOS transistor coupled between the second NMOS transistor and the clamping voltage, wherein the first and second PMOS transistors and the first, second, and third NMOS transistors are coupled in parallel between the clamping voltage and the gate terminal of the row selection transistor of one of the pixel circuits, wherein the first and second PMOS transistors of each RC driver are configured to provide an upper clamping voltage range to the gate terminal of the row selection transistor of one of the pixel circuits, and wherein the first, second, and third NMOS transistors of each RC driver are configured to provide a lower clamping voltage range to the gate terminal of the row selection transistor of one of the pixel circuits. Attached Figure Description

[0005] The following figures illustrate non-limiting and non-exhaustive embodiments of this disclosure, wherein similar reference numerals throughout the various views refer to similar portions unless otherwise specified.

[0006] Figure 1 This describes an example of an imaging system based on the teachings of this disclosure.

[0007] Figure 2 A schematic diagram illustrating an example pixel circuit based on the teachings of this disclosure.

[0008] Figure 3 This diagram illustrates an example of a rolling clamp driver and an example of a driver selection based on the teachings of this disclosure.

[0009] Figure 4 This diagram illustrates an example of a rolling clamp driver and a row selection driver in clamping and reading rows according to the teachings of this disclosure.

[0010] Figure 5 A schematic diagram illustrating an example circuit for controlling the gate voltage value of a transistor in a rolling clamp driver, according to the teachings of this disclosure.

[0011] Figure 6 This is a table listing example gate voltage values ​​of transistors in a rolling clamp driver according to the teachings of this disclosure.

[0012] Throughout the various views in the accompanying drawings, corresponding reference numerals indicate corresponding components. Those skilled in the art will understand that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to aid in understanding the various embodiments of this disclosure. Furthermore, common but well-understood elements that are useful or necessary in commercially viable embodiments are generally not depicted in order to facilitate a more unhindered understanding of these various embodiments of this disclosure. Detailed Implementation

[0013] Examples of imaging systems with rolling clamping actuators are disclosed, which provide an increased clamping voltage range, reduced cost, and reduced risk of transistor breakdown. Numerous specific details are set forth in the following description to provide a thorough understanding of the examples. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of the specific details stated herein, or using other methods, components, materials, etc. In other examples, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects.

[0014] Throughout this specification, references to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one instance of this disclosure. Therefore, the phrases "in an example" or "in an embodiment" appearing in various places throughout this specification do not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, or characteristic may be combined in one or more examples in any suitable manner.

[0015] For ease of description, spatial relative terms such as “below,” “below,” “above,” “under,” “above,” “top,” “bottom,” “left,” “right,” “center,” “middle,” etc., may be used herein to describe the relationship of one element or feature to another element(s), as illustrated in the figures. It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figures is rotated or flipped, then an element described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” may cover both the above and below orientations. The device may be oriented in other ways (rotated ninety degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Furthermore, it should be understood that when an element is described as being “between” two other elements, it may be the only element between the two other elements, or there may be one or more intervening elements.

[0016] Throughout this specification, several terms in the art are used. These terms will have their ordinary meaning in the field from which they are derived, unless expressly defined herein or otherwise indicated by the context in which they are used. It should be noted that throughout this document, component names and symbols are used interchangeably (e.g., Si and silicon); however, they have the same meaning.

[0017] As will be discussed, various examples of imaging systems with rolling clamping drivers are disclosed, which offer increased clamping voltage range, reduced cost, and reduced risk of transistor breakdown. Pixel circuitry included in the imaging system receives voltage from a voltage supply grid at various nodes (i.e., voltage sources). Each voltage source has both horizontal and vertical current draw paths within the grid. In the same row, the voltage at a node sensing dim light can increase due to the low current draw from the node sensing bright light through the voltage supply grid, since bright light pixels only draw vertical current. This variation in voltage sources alters the voltage at the floating diffuser in the same trend and can lead to a harmful h-band in the sensed image, particularly when the sensed image has significant contrast between bright and dark areas. An h-band appears when dark and bright areas of the image appear darker in the same row. Rolling clamping helps reduce the h-band by mitigating current variations and thus voltage variations in the voltage supply grid.

[0018] However, conventional imaging systems with rolling clamp drivers are at high risk of transistor breakdown due to potential differences across different transistor terminals exceeding certain thresholds. The rolling clamp driver will also fail if the clamping voltage exceeds the acceptable voltage range it can handle. Furthermore, imaging systems can have thousands of rolling clamp drivers on a single image sensor logic chip, making the risk of transistor breakdown and failure extremely high. Additionally, using transistors specially manufactured to withstand high voltages can be very expensive.

[0019] It should be understood that the imaging system according to the teachings of this disclosure may include a high-voltage rolling clamp driver that provides a wide clamping voltage range without using expensive, specially manufactured high-voltage transistors. The rolling clamp driver may include transistors arranged in a transfer gate structure having a PMOS side and an NMOS side with different bias schemes. In various examples, the PMOS side is biased with a static cascode bias, and the NMOS side is biased with a dynamic triple cascode bias. In various examples, the rolling clamp driver limits the potential difference across the different transistor terminals to prevent transistor breakdown. In various examples, the rolling clamp driver includes normal transistors instead of expensive, specially manufactured high-voltage transistors requiring high-voltage wells or high-voltage gate oxides. In various examples, the imaging system includes 40 nm normal transistors using a 3.3 V process technology. In various examples, the PMOS transistor is located in an N-well, and the NMOS transistor is located in a P-well, which is not connected to the substrate, so both the NMOS and PMOS bodies can be connected to any potential.

[0020] Therefore, as will be shown and described in the various examples below, the example imaging system includes a pixel array having multiple pixel circuits. Each pixel circuit includes a photodiode configured to generate image charge in response to incident light, a floating diffuser coupled to receive image charge from the photodiode, a source follower transistor having a gate terminal coupled to the floating diffuser, and a row select transistor having a source terminal coupled to the source follower transistor. The example imaging system further includes multiple rolling clamp (RC) drivers, wherein each RC driver is coupled to the gate terminal of the row select transistor of one of the pixel circuits, and each RC driver has an on state and an off state. Each RC driver includes a first PMOS transistor coupled between the clamping voltage and the gate terminal of a row selection transistor in the pixel circuit, a second PMOS transistor coupled between the first PMOS transistor and the gate terminal of a row selection transistor in the pixel circuit, a first NMOS transistor coupled between the clamping voltage and the gate terminal of a row selection transistor in the pixel circuit, a second NMOS transistor coupled between the first NMOS transistor and the clamping voltage, and a third NMOS transistor coupled between the second NMOS transistor and the clamping voltage. The first and second PMOS transistors and the first, second, and third NMOS transistors are connected in parallel and coupled between the clamping voltage and the gate terminal of a row selection transistor in the pixel circuit. The first and second PMOS transistors of each RC driver are configured to provide an upper clamping voltage range to the gate terminal of a row selection transistor in the pixel circuit. The first, second, and third NMOS transistors of each RC driver are configured to provide a lower clamping voltage range to the gate terminal of a row selection transistor in the pixel circuit.

[0021] To illustrate, Figure 1 An example of an imaging system 100 with readout circuitry 106 according to the teachings of this disclosure is shown. Specifically, Figure 1 The illustration depicts an imaging system 100, which includes a pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array containing a plurality of pixel circuits 104 (e.g., P1, P2, ..., Pn), which are arranged in rows (e.g., R1 to Ry) and columns (e.g., C1 to Cx) to acquire image data of people, locations, objects, etc., which can then be used to render images of people, locations, objects, etc.

[0022] In various instances, the readout circuit 106 may be configured to read out the image signal via the column bit line 112. As will be discussed, in various instances, the readout circuit 106 may include an analog-to-digital converter (ADC) 107 according to the teachings of this disclosure. In said instances, the digital image data values ​​generated by the ADC in the readout circuit 106 may then be received by functional logic 108. The functional logic 108 may simply store the digital image data or even manipulate the digital image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or others).

[0023] In one example, control circuitry 110 is coupled to pixel array 102 to control the operation of multiple photodiodes in pixel array 102. For example, control circuitry 110 may generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with lighting effects (e.g., flash).

[0024] In one example, the imaging system 100 may be included in an imaging device such as a digital camera, mobile phone, laptop computer, endoscope, security camera, or automobile. Additionally, the imaging system 100 may be coupled to other hardware such as a processor (general-purpose or other processor), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), illumination / flash, electrical inputs (keyboard, touch screen, trackpad, mouse, microphone, etc.), and / or a display. This other hardware can deliver instructions to the imaging system 100, retrieve image data from the imaging system 100, or manipulate image data supplied by the imaging system 100.

[0025] Figure 2 A schematic diagram illustrating an example pixel circuit 204 according to the teachings of this disclosure is provided. It should be understood that... Figure 2 The pixel circuit 204 can be Figure 1 Examples of one of the pixel circuits 104 included in the imaging system 100 shown herein, and similarly named and numbered elements described above are similarly coupled and function below.

[0026] In the illustrated example, pixel circuit 204 includes a photodiode 214 configured to generate image charge in response to incident light, a floating diffuser 218 coupled to receive image charge from photodiode 214, a transfer transistor 216 coupled between photodiode 214 and floating diffuser 218 to transfer image charge from photodiode 214 to floating diffuser 218, a reset transistor 234 coupled between photodiode 214 and voltage source PIXVDD 260, and a dual floating diffuser transistor 224 coupled between reset transistor 234 and floating diffuser 218. Pixel circuit 204 also includes a source follower transistor 220 having a gate terminal coupled to floating diffuser 218 and a drain terminal coupled to voltage source PIXVDD 260; and a row select transistor 222 coupled between the source terminal of source follower transistor 220 and bit line 212.

[0027] In an imaging system that provides rolling clamping, each row of pixel circuitry (e.g., Figure 1 The rows R1 to Ry described can be read out one by one when adjacent rows are clamped. Depending on whether the row containing the pixel circuit is read out, clamped, or neither read out nor clamped, various control signals can be sent to the gate terminal of the row selection transistor 222.

[0028] Figure 3 The illustration shows an example of a rolling clamp (RC) driver 340 and an example of a row select (RS) driver 350 according to the teachings of this disclosure. It should be understood that the RC driver 340 and the RS driver 350 are coupled to output control signals to the pixel circuit 304, and Figure 3 The pixel circuit 304 can be Figure 1 Examples of one of the pixel circuits 104 included in the imaging system 100 shown herein, and similarly named and numbered elements described above are similarly coupled and function below.

[0029] In the illustrated example, the RC driver 340 includes a first PMOS transistor P0 341 and a second PMOS transistor P1 342 coupled between the clamping voltage Vclamp 336 and the gate terminal of the row selection transistor 322 of the pixel circuit 304. The RC driver 340 also includes a first NMOS transistor N1 343, a second NMOS transistor N2 344, and a third NMOS transistor N3 345 coupled between the clamping voltage Vclamp 336 and the gate terminal of the row selection transistor 322. In the illustrated example, the first and second PMOS transistors P0 341 and P1 342, and the first, second, and third NMOS transistors N1 343, N2 344, and N3 345 are connected in parallel between the clamping voltage Vclamp 336 and the gate terminal of the row selection transistor 322. In other embodiments, the RC driver 340 may include fewer or more transistors arranged in different configurations.

[0030] The first PMOS transistor P0 341 may have a gate terminal coupled to a variable signal pcon1 346 and a body terminal coupled to a high voltage VH. The second PMOS transistor P1 342 may have a gate terminal coupled to ground and a body terminal coupled to a high voltage VH. The first NMOS transistor N1 343 may have a gate terminal coupled to a variable signal ncon1 347 and a body terminal coupled to a negative voltage VN. The second NMOS transistor N2 344 may have a gate terminal coupled to a variable signal ncon2 348 and a body terminal coupled to a negative voltage VN. The third NMOS transistor N3 345 may have a gate terminal coupled to a variable signal ncon3 349 and a body terminal coupled to ground. The signals coupled to the various gate terminals can be controlled to configure the RC driver 340 to output a clamping voltage Vclamp 336 or to turn it off.

[0031] In the illustrated example, the RS driver 350 includes a third PMOS transistor P2 351 and a fourth PMOS transistor P3 352 coupled between a high voltage VH and the gate of the row select transistor 322. The RS driver 350 also includes a fourth NMOS transistor N4 353 and a fifth NMOS transistor N5 354 coupled between a negative voltage VN and the gate of the row select transistor 322. In other embodiments, the RS driver 350 may include fewer or more transistors arranged in a different configuration.

[0032] The third PMOS transistor P2 351 may have a gate terminal coupled to 0 V or a high voltage VH and a body terminal coupled to a high voltage VH. The fourth PMOS transistor P3 352 may have a gate terminal coupled to ground and a body terminal coupled to a high voltage VH. The fourth NMOS transistor N4 353 may have a gate terminal coupled to a fixed voltage DVDD and a body terminal coupled to a negative voltage VN. The fifth NMOS transistor N5 354 may have a gate terminal coupled to a negative voltage VN or a fixed voltage DVDD and a body terminal coupled to a negative voltage VN. The signals coupled to the various gate terminals can be controlled to configure the RS driver 350 to output a high voltage VH or a negative voltage VN, or to turn it off. The fixed voltage DVDD may be a voltage source for digital circuitry and is typically 1.2V, which is less than the voltage source PIXVDD 260.

[0033] Returning to the reference RC driver 340, the second PMOS transistor P1 342 can be biased with a static cascode bias, such that its gate terminal is coupled to ground regardless of whether the RC driver 340 is in the on or off state. On the other hand, the first, second, and third NMOS transistors N1 343, N2 344, and N3 345 can be biased with a dynamic triple cascode bias, such that signals ncon1 347, ncon2 348, and ncon3 349 can vary depending on whether the RC driver 340 is in the on or off state. By applying a static cascode bias to the PMOS side of the RC driver 340 and a dynamic triple cascode bias to the NMOS side, the potential difference across the transistor terminals can be maintained below the breakdown voltage difference (e.g., 3.6 V when using a 40 nm transistor with a 3.3 V process technology). More specifically, the RC driver 340 maintains the potential difference across the gate-source, gate-drain, gate-body, and drain-source terminals below the breakdown threshold. Due to the PN junction of the transistor, the potential difference across the drain-body and source-body terminals inherently suffers from a lower risk of breakdown. Furthermore, the RC driver 340 significantly reduces the risk of breakdown or failure without incorporating specially manufactured high-voltage transistors, which can be expensive.

[0034] Furthermore, thanks to its pass-gate structure, the RC driver 340 can handle a wide range of clamping voltage values ​​and transmit signals without significant voltage drop (i.e., with very low resistance). The first and second PMOS transistors P0 341 and P1 342 can transmit relatively high clamping voltages Vclamp 336, while the first, second, and third NMOS transistors N1 343, N2 344, and N3 345 can transmit relatively low clamping voltages Vclamp 336. In various examples, the clamping voltage Vclamp 336 can range from 0.6 V to 3 V.

[0035] Figure 4 The diagram illustrates example RC driver 440 and RS driver 450 in clamping row 404a and reading row 404b according to the teachings of this disclosure. It should be understood that... Figure 4 The RC driver 440 and RS driver 450 can be Figure 3 Examples of RC driver 340 and RS driver 350 shown in the text, and similarly named and numbered components described above are similarly coupled and function in the following text.

[0036] In an imaging system providing rolling clamping, a high-voltage signal (i.e., an on signal) is sent to the gate terminal of the row selection transistor in the readout row (e.g., 404b), a clamping voltage signal is sent to the gate terminal of the row selection transistor in the adjacent row used as the clamping row (e.g., 404a), and a low-voltage signal (i.e., an off signal) is sent to the gate terminals of the row selection transistors in the remaining rows. In the illustrated example, the pixel circuit in the readout row 404b includes an RC driver 440b configured to be off and an RS driver 450b configured to be on, and sends a high-voltage signal VH to the gate terminal of the corresponding row selection transistor. The gate of the source follower transistor SF is coupled to a floating diffuser FD, where a signal from a photodiode can be stored. On the other hand, the pixel circuit in the clamping row 404a includes an RC driver 440a configured to be on and sends a clamping voltage signal to the gate terminal of the corresponding row selection transistor. The gate of the source follower transistor SF is coupled to the voltage source PIXVDD 460, and the RST and DFD transistors (e.g., Figure 2 The RST transistor 234 and DFD transistor 224 described herein are both configured to be turned on. The row select transistors in clamp row 404a and read row 404b are configured to be coupled to the same bit line 412, such that clamp row 404a can clamp read row 404b.

[0037] Figure 5 This illustration shows an example circuit 570 for controlling or providing the gate voltage value of a transistor in a rolling clamp driver, according to the teachings of this disclosure. It should be understood that... Figure 5 The circuit 570 can be coupled to control Figure 3 The gate voltage values ​​of the transistors included in the RC driver 340 shown in the figure, and the similarly named and numbered elements described above are similarly coupled and function in the following text.

[0038] In the illustrated example, circuit 570 includes a first inverter 562, which includes an input coupled to the gate terminal of a first PMOS transistor pcon1 546 (e.g., the gate terminal pcon1 346 of the first PMOS transistor 341), a power supply input coupled to a high voltage VH and ground, and an inverted output coupled to the gate terminal of a third NMOS transistor ncon3 549 (e.g., the gate terminal ncon3 349 of the third NMOS transistor 345). A second inverter 564 includes an input coupled to ncon3 549, a power supply input coupled to a reference voltage Vref and ground, and an inverted output. A level shifter 568 includes an input coupled to the inverted output of the second inverter 564, a power supply input coupled to the reference voltage Vref and a negative voltage VN, and an inverted output coupled to the gate terminal of a second NMOS transistor ncon2 548 (e.g., the gate terminal ncon2 348 of the second NMOS transistor 344). The third inverter 566 includes an input coupled to the inverted output of the second inverter 564, a power supply input coupled to a reference voltage Vref and ground, and an inverted output coupled to the gate terminal of the first NMOS transistor ncon1 547 (e.g., the gate terminal ncon1 347 of the first NMOS transistor 343). In various examples, VH is a high voltage value (e.g., 3.6 V) and VN is a negative voltage value (e.g., -1.4 V). In various examples, Vref is a reference voltage value (e.g., 1.8 V) between 0 V and the high voltage VH.

[0039] The first PMOS transistor that can be coupled to the RC driver (e.g., Figure 3 The signal pcon1 546 at the gate terminal of the first PMOS transistor (P0341) can be switched between a high value (e.g., VH) and a low value (e.g., 0 V) ​​to control the values ​​of other signals ncon1 547, ncon2 548, and ncon3 549 at the gate terminals of NMOS transistors (e.g., the first, second, and third NMOS transistors N1 343, N2 344, and N3 345, respectively) that can be coupled to an RC driver. Changing the values ​​of signals ncon1 547, ncon2 548, and ncon3 549 provides a dynamic triple cascode bias to the NMOS transistors in the RC driver. In various instances, the dynamic triple cascode bias is provided by multiple on-chip level shifters.

[0040] Figure 6 This is a table listing example gate voltage values ​​for transistors in a rolling clamp driver according to the teachings of this disclosure. It should be understood that... Figure 6 The values ​​shown in the text can be Figure 3The example gate voltage values ​​of the transistors included in the RC driver 340 shown in the figure, and the similarly named and numbered elements described above are similarly coupled and function below.

[0041] When the RC driver is turned on, the signal pcon1 646 applied to the first PMOS transistor (e.g., the first PMOS transistor P0 341) can be 0 V, and the signals ncon1 647, ncon2 648, and ncon3 649 coupled to the gate terminals of the NMOS transistors (e.g., the first, second, and third NMOS transistors N1343, N2 344, and N3 345) can be Vref, Vref, and VH, respectively. When the RC driver is turned off, the signal pcon1 646 can be VH, and the signals ncon1 647, ncon2 648, and ncon3 649 can be 0 V, VN, and 0 V, respectively. In various examples, VH is a high voltage value (e.g., 3.6 V), and VN is a negative voltage value (e.g., -1.4 V). In various examples, Vref is a reference voltage value between 0 V and the high voltage VH (e.g., 1.8 V). Vref is tunable to accommodate various technologies. For example, when Vref is applied to the gate terminal of the first NMOS transistor N1, the gate-to-source, gate-to-drain, and gate-to-body voltages of N1 are controlled within specific breakdown voltages determined by specific process technologies.

[0042] By applying a static cascode bias to the PMOS side of the RC driver and a dynamic triple cascode bias to the NMOS side, the potential difference across the transistor terminals can be maintained below the breakdown voltage difference (e.g., 3.6 V). More specifically, the RC driver can maintain the potential difference across the gate-source, gate-drain, gate-body, and drain-source terminals below the breakdown threshold. Due to the PN junction of the transistor, the potential difference across the drain-body and source-body terminals inherently suffers from a lower risk of breakdown. Furthermore, the RC driver significantly reduces the risk of breakdown or failure without incorporating specially manufactured high-voltage transistors, which can be expensive.

[0043] The foregoing description of the illustrative examples in this disclosure, including those described in the abstract, is not intended to be exhaustive or to limit this disclosure to its precise form. While specific examples of this disclosure have been described herein for illustrative purposes, those skilled in the art will recognize that various modifications are possible within the scope of this disclosure.

[0044] In view of the detailed description above, these modifications may be made to the examples of this disclosure. The terminology used in the appended claims should not be construed as limiting this disclosure to the specific examples disclosed in the specification. Rather, the scope of this disclosure will be determined entirely by the following claims, which will be interpreted according to the established principles of claim interpretation.

Claims

1. An imaging system comprising: A pixel array comprising multiple pixel circuits, wherein each pixel circuit comprises: A photodiode configured to generate an image charge in response to incident light; A floating diffuser, coupled to receive the image charge from the photodiode; A source follower transistor having a gate terminal coupled to the floating diffuser; and A row selection transistor coupled to the source terminal of the source follower transistor; and A plurality of rolling clamping RC drivers, wherein each RC driver is coupled to the gate terminal of a row selection transistor in one of the pixel circuits, wherein each RC driver has an on state and an off state, and wherein each RC driver includes: A first PMOS transistor is coupled between a clamping voltage and the gate terminal of the row selection transistor of one of the pixel circuits; A second PMOS transistor is coupled between the first PMOS transistor and the gate terminal of the row selection transistor of one of the pixel circuits; A first NMOS transistor is coupled between the clamping voltage and the gate terminal of the row selection transistor of one of the pixel circuits; A second NMOS transistor is coupled between the first NMOS transistor and the clamping voltage; and A third NMOS transistor is coupled between the second NMOS transistor and the clamping voltage, wherein the first and second PMOS transistors and the first, second, and third NMOS transistors are coupled in parallel between the clamping voltage and the gate terminal of the row selection transistor of one of the pixel circuits. The first and second PMOS transistors of each RC driver are configured to provide an upper clamping voltage range to the gate terminal of the row selection transistor of one of the pixel circuits, and The first, second, and third NMOS transistors of each RC driver are configured to provide a lower clamping voltage range to the gate terminal of the row selection transistor of one of the pixel circuits.

2. The imaging system of claim 1, wherein the second PMOS transistor of each RC driver is configured to be biased with a static cascode bias.

3. The imaging system of claim 2, wherein for each RC driver, when the RC driver is in the on state: The gate terminal of the first PMOS transistor is configured to be coupled to a zero voltage value, and The gate terminal of the second PMOS transistor is configured to be coupled to ground.

4. The imaging system of claim 2, wherein for each RC driver, when the RC driver is in the off state: The gate terminal of the first PMOS transistor is configured to be coupled to a high voltage value, and The gate terminal of the second PMOS transistor is configured to be coupled to ground.

5. The imaging system of claim 1, wherein the first, second, and third NMOS transistors are configured to be biased with a dynamic triple common-source bias.

6. The imaging system of claim 5, wherein for each RC driver, when the RC driver is in the on state: The gate terminal of the first NMOS transistor is configured to be coupled to a reference voltage value. The gate terminal of the second NMOS transistor is configured to be coupled to the reference voltage value, and The gate terminal of the third NMOS transistor is configured to be coupled to a high voltage value. The high voltage value is higher than the reference voltage value.

7. The imaging system of claim 5, wherein for each RC driver, when the RC driver is in the off state: The gate terminal of the first NMOS transistor is configured to be coupled to a zero voltage value. The gate terminal of the second NMOS transistor is configured to be coupled to a negative voltage value, and The gate terminal of the third NMOS transistor is configured to be coupled to the zero voltage value. The negative voltage value is lower than the zero voltage value.

8. The imaging system of claim 5, wherein the dynamic three-source common gate bias is provided by a plurality of on-chip level shifters.

9. The imaging system of claim 1, wherein each of the first and second PMOS transistors and the first, second and third NMOS transistors is a non-high-voltage dedicated transistor.

10. The imaging system of claim 1, further comprising a plurality of row selection RS drivers, wherein each RS driver is coupled to the gate terminal of a row selection transistor of another in the pixel circuit, wherein each RS driver has an on state and an off state, wherein one of the RS drivers is configured to be in the off state when a corresponding RC driver is in the on state, and wherein one of the RS drivers is configured to be in the on state when the corresponding RC driver is in the off state.

11. The imaging system of claim 1, wherein for each of the first and second PMOS transistors and the first, second and third NMOS transistors, the gate-body voltage difference, gate-drain voltage difference, gate-source voltage difference and drain-source voltage difference are configured to be less than the breakdown voltage value.

12. The imaging system according to claim 1, further comprising: The first inverter includes an input coupled to the gate terminal of the first PMOS transistor, a power supply input coupled to a high voltage value, and an inverted output coupled to the gate terminal of the third NMOS transistor. The second inverter includes an input coupled to the inverted output of the first inverter, a power input coupled to a reference voltage value, and an inverted output; A level shifter comprising an input coupled to the inverted output of the second inverter, a power input coupled to the reference voltage value and the negative voltage value, and an inverted output coupled to the gate terminal of the second NMOS transistor; and The third inverter includes an input coupled to the inverted output of the second inverter, a power input coupled to the reference voltage value, and an inverted output coupled to the gate terminal of the first NMOS transistor.

13. The imaging system of claim 1, wherein the upper clamping voltage range comprises 3 V, and wherein the lower clamping voltage range comprises 0.6 V.

14. The imaging system of claim 6, wherein the reference voltage is configured to maintain each of the gate-to-source voltage, gate-to-drain voltage, and gate-to-body voltage of at least one of the first and second NMOS transistors within a breakdown voltage, and wherein the breakdown voltage is determined by a process technology for manufacturing the at least one of the first and second NMOS transistors.

Images