A power MOSFET chip with improved avalanche breakdown energy

Abstract

The present invention relates to a power MOSFET chip for improving avalanche breakdown energy. The power MOSFET chip comprises a strip cell structure. The power MOSFET chip comprises a transition region, an N+ injection region, and a source lead hole, and comprises: the source lead hole extends out of the N+ injection region, wherein the transition region is a transition region at a straight edge of an active region, thereby avoiding premature conduction of a parasitic NPN of a cell at an edge of the active region at the moment of MOSFET shutoff, thereby improving the EAS energy and consistency of a product. The extension of the lead hole at the edge of the active region and the N+ injection region is used to collect a lateral current IR1 of a P region, thereby avoiding the problem of premature breakdown of an NPN at an edge of the active region due to lithography bias, thereby obtaining a higher and more stable product EAS characteristic, and simultaneously improving the short-circuit resistance of a parallel application, thereby improving system reliability, and eliminating the EAS grading action due to the improvement of product consistency, thereby saving testing and management costs.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductors, in particular to a power MOSFET chip capable of improving avalanche breakdown energy. Background Art

[0002] MOSFET products in power semiconductor devices have the characteristics of fast switching speed, low loss, and recoverable drain-source breakdown. They are widely used in BMS power supplies, motor drives and other applications. MOSFET parameters include two categories: static parameters and dynamic parameters. Static parameters include: breakdown voltage, on-resistance, turn-on voltage, etc. Dynamic parameters include switching time, capacitance, EAS (Energy of Avalanche of Single pulse) single pulse avalanche breakdown energy, etc. EAS is usually used to measure the avalanche breakdown energy tolerance of the product;

[0003] Existing MOSFETs can include planar MOSFETs, trench MOSFETs, and split-gate MOSFETs. The equivalent diagrams of the MOSFET cell structures of the three structures are as follows: Figure 1 As shown in the figure, the three MOSFETs are in normal working state, where: Figure 1 a in the figure represents the equivalent diagram of the cell structure of the planar MOSFET. Figure 1 b in the figure represents the equivalent diagram of the cell structure of the trench MOSFET. Figure 1 The c in the figure represents the cell structure equivalent diagram of the split-gate MOSFET. The gate (G) voltage controls the on / off of the channel to achieve the function of a switch, and the drain-source reverse withstand voltage (BVdss) is achieved by the reverse PN junction composed of NP-. However, the power MOSFET has parasitic effects. Figure 1 a: Take the planar MOSFET as an example, each cell has a parasitic NPN transistor, where the substrate layer N+ and epitaxial layer N- of the drain (D) are equivalent to the collector (c) of the transistor, the N+ of the source (S) is equivalent to the emitter (e) of the transistor, and the P- / P+ region is equivalent to the base (b) and base resistor (Rb) of the transistor. A power MOSFET chip is equivalent to millions of cells; Source represents the source, abbreviated as S, Gate represents the gate, abbreviated as G, and Drain represents the drain, abbreviated as D.

[0004] At the moment of turning off, the MOSFET drain-source will enter a breakdown state in order to continue the current of the parasitic or load inductor. Excessive follow-up current will trigger the NPN to turn on, causing local overcurrent and burning the chip. Figure 2 The MOSFET application diagram is shown in Figure 1, where L is the parasitic or load inductance. Figure 3 In Figure 3During the Vgs on period, Vdd charges the inductor L, and the drain current Id gradually rises to the peak value Ias. When Vgs is turned off, in order to continue the current for the inductor L, the MOSFET quickly enters the reverse breakdown state. At this time, V d =BVdss, inductor current discharge. Id gradually decreases from Ias to zero. During the inductor current discharge, MOSFET is in high voltage and high current mode, and the energy is relatively high. The total energy during this period is 1 / 2*L*Ias^2. When the Vgs on-time is extended, Ias will increase, and the energy that MOSFET can withstand will also increase. When Ias reaches Iasmax, the MOSFET will burn out at the moment of shutdown. At this time, the inductor energy is 1 / 2*L*Iasmax^2, which is EAS.

[0005] like Figure 1 As shown, at the moment when Vgs is turned off, the drain-source enters breakdown, that is, the NPN transistor also enters the reverse breakdown state. At this time, the discharge current is the drain-source breakdown current, that is, the reverse breakdown current I of the NPN R Due to the existence of P-body resistance Rb, I R A voltage drop V will be generated on Rb Rb =Rb*I R .Depend on Figure 1 The equivalent diagram shows that the transistor emitter voltage drop Vbe=V Rb。 When Ias increases to Iasmax, that is, I R Increase to meet V Rb =0.7V, the emitter is turned on, and due to the current amplification of the transistor, the current from c to e will increase sharply, causing local overheating of the chip and burning of the product. For any product, when Rb*I R When the voltage is >0.7V, the NPN will conduct and burn the chip. To improve the EAS capability, it is essentially to delay the conduction of the NPN. There are two ways: one is to reduce the Rb resistance, and the other is to optimize the current distribution to avoid IR concentration in the local part of the chip.

[0006] Power MOSFET chips generally include three major parts: active area, transition area, and terminal area. The active area is usually designed in the middle of the chip. It is the part responsible for current flow and power bearing, which can be equivalent to thousands of cells in parallel. The terminal area is designed in the peripheral area of ​​the chip to weaken the surface electric field and increase the breakdown voltage of the product. The transition area is designed in the middle area between the active area and the terminal area, mainly to realize the metal routing function. Compared with the active area and the terminal area, the graphics of the chip transition area are irregular and the three-dimensional space is relatively complex.

[0007] Drain-source breakdown current I R Evenly distributed in each cell of the active area, the reverse current I RO, all flow from the bottom N-drain, through the N- / P- / P+ junction, and vertically flow out of the source from the source lead hole. In the transition region, because there is also an N- / P-junction at the bottom, the reverse current I R1 , it needs to flow from the N-drain at the bottom of the transition region, through the N- / P-junction, flow laterally through the P-region, and then gather at the source lead hole at the edge of the active region and flow to the source. The transition region design of the prior art, such as Figure 4 and Figure 5 As shown in Figure 1, the source lead hole is completely aligned with the N+ implantation region pattern boundary. Ideally, I R1 Does not flow through Rb below the cell and does not cause V Rb The rise of has no effect on EAS energy. However, in the actual process, there is a lithography pattern offset. For example, when the lead hole is lithographic, the offset range with the N+ area pattern is about -0.1~0.1µm. When the offset is positive, the lead hole is indented relative to the N+ position. At this time, I R1 It must first flow through Rb1 below N+ before flowing to the P+ source. At this time, the reverse current on Rb1 is I R0 +I R1 , causing the local VRb1 to rise, satisfying the 0.7V NPN trigger turn-on condition in advance. This causes the product EAS energy to decrease. There is a certain process fluctuation in the lithography set offset, because the EAS energy value of the prior art product is also prone to fluctuations. Using the prior art products, it is also necessary to perform 100% testing on the product EAS and perform parameter grading, which increases the testing cost. For occasions such as BMS that require multiple power MOSFETs to be used in parallel, due to the consistency problem of EAS parameters, the end customer can only increase the number of MOSFETs in parallel to meet the high power requirements of the product, reducing the power density of the system board and restricting the market development of high-power (for example, above 1000W) applications; that is, the technical problem of the present invention is: the problem of damage to the device caused by the energy impact of parasitic or load inductance at the moment of shutdown due to the EAS (avalanche breakdown energy) consistency defect of the MOSFET product. Summary of the invention

[0008] The purpose of the present invention is to provide a power MOSFET chip with improved avalanche breakdown energy, aiming to solve the problem that the MOSFET is damaged by the energy impact of parasitic or load inductance at the moment of shutdown due to the EAS (avalanche breakdown energy) consistency defect of MOSFET products.

[0009] To achieve the above-mentioned purpose, the present invention proposes a power MOSFET chip with improved avalanche breakdown energy. The power MOSFET chip includes a strip cell structure, and the power MOSFET chip includes a transition zone, an N+ injection zone, and a source lead hole, including: the source lead hole extends out of the N+ injection zone, wherein the transition zone is a transition zone at the straight edge of the active zone.

[0010] More preferably, the length of the source lead hole extending out of the N+ implantation region is 2 microns or more.

[0011] More preferably, the transition region is a transition region at a corner of the active region.

[0012] More preferably, the source lead hole and the N+ implantation region extend in a step-like manner, and the source lead hole extends out of the N+ implantation region.

[0013] More preferably, the number of the steps is 3 to 9.

[0014] More preferably, the power MOSFET chip is a trench MOSFET, a split-gate MOSFET, or a planar MOSFET; or, the power MOSFET chip is a SiC-based MOSFET or a silicon-based MOSFET.

[0015] To achieve the above-mentioned purpose, the present invention proposes a power MOSFET chip with improved avalanche breakdown energy, wherein the power MOSFET chip includes a cellular structure with a square structure or a hexagonal structure, and the power MOSFET chip includes a transition zone, an N+ injection zone, and a dummy cell, including: an active zone is provided with a dummy cell in which N+ injection is not performed, wherein the transition zone is a transition zone at the straight edge of the active zone.

[0016] More preferably, the number of the pseudo cells is two or more per column, and double drainage holes are provided.

[0017] More preferably, the transition region is a transition region at a corner of the active region.

[0018] More preferably, the pseudo-cells are in a stepped shape.

[0019] More preferably, the power MOSFET chip is a trench MOSFET, a split-gate MOSFET, or a planar MOSFET; or, the power MOSFET chip is a SiC-based MOSFET or a silicon-based MOSFET.

[0020] The power MOSFET chip with improved avalanche breakdown energy of the present invention has at least the following beneficial effects: the design of the source lead hole and the N+ injection area in the transition zone is optimized, the photolithography offset process margin of the product is improved, the photolithography offset can be accommodated, the reverse current IR1 in the transition zone is avoided, the current of the cells at the edge of the active area is converged, the consistency of the EAS energy of the product is improved, the parasitic NPN of the cells at the edge of the active area is avoided to be turned on in advance at the moment of MOSFET shutdown, the EAS energy and consistency of the product are improved, and it is beneficial to the application of high-power MOSFET MOSFET parallel connection reduces the number of MOSFETs in parallel at the high-power parallel application end, improves the system power density, and develops the product in the direction of miniaturization, low power consumption, and ultra-high power. The lead holes at the edge of the active area and the extension of the N+ injection area are used to collect the lateral current IR1 in the P- area, avoiding the problem of premature breakdown of the NPN at the edge of the active area due to lithography bias, so as to obtain higher and more stable product EAS characteristics. At the same time, it can improve the short-circuit resistance of parallel applications and improve system reliability. Because of the improvement of product consistency, the EAS grading action is omitted, saving testing and management costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0022] Figure 1 are equivalent diagrams of three MOSFET cell structures in the prior art;

[0023] Figure 2 A circuit diagram of a MOSFET of the prior art;

[0024] Figure 3 It is the working waveform diagram of MOSFET in the prior art;

[0025] Figure 4 A schematic diagram of the straight edge of the active area of ​​a strip cell in the prior art;

[0026] Figure 5 A schematic diagram of the straight edge of the active area of ​​a square cell in the prior art;

[0027] Figure 6 A schematic diagram of the straight edge of the active area of ​​the strip cell of the present invention;

[0028] Figure 7 is a schematic diagram of a corner of an active area of ​​a strip cell of the present invention;

[0029] Figure 8A schematic diagram of a corner of an active area of ​​a strip cell in the prior art;

[0030] Fig. 9 is a schematic diagram of the straight edge of the active area of ​​the square cell of the present invention;

[0031] Fig.10 is a schematic diagram of the corner of the active area of ​​the square cell of the present invention;

[0032] Fig.11 Schematic diagram of the corner of the active area of ​​a square cell in the prior art.

[0033] In the attached drawings: 1-active area, 2-transition area, 3-extended source lead hole, 4-step-extended source lead hole, 5-pseudo cell, 6-step-arranged pseudo cell, 7-groove or polycrystalline strip, 8-double drain flow hole. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0035] The specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0036] For strip cell structures: please refer to Figure 6 , shows a power MOSFET chip for improving avalanche breakdown energy according to an embodiment of the present invention, the cell structure includes a strip cell structure, the power MOSFET chip includes a transition region, an N+ injection region, and a source lead hole, including: the source lead hole extends out of the N+ injection region, wherein the transition region is a transition region at the straight edge of the active region. Further applied to the embodiment of the present invention, the length of the source lead hole extending out of the N+ injection region is 2 microns or more, and in the embodiment of the present invention, the strip cell is provided with an extended source lead hole.

[0037] When the cell structure in the embodiment of the present invention is a strip cell, the source lead hole extends out of the N+ injection region. The source lead hole of the present invention, such as Figure 6 As shown in the figure, there is an extension greater than or equal to 2 microns (µm) compared to the boundary of the N+ implantation region. At this time, even if there is a photolithography offset, the IR1 flowing laterally from the transition region can still flow out of the source through the extended lead hole, and no additional VRb will be generated in the Rb below the N+.

[0038] For further information, please refer to Figure 7, shows a power MOSFET chip with improved avalanche breakdown energy according to an embodiment of the present invention, wherein the transition region is a transition region at a corner of an active region, and 4 represents a source lead hole with stepped extension. Figure 8 The source lead hole and the N+ injection area of ​​the prior art are flush, while the source lead hole and the N+ injection area of ​​the present invention extend in a step-like manner, and the source lead hole extends out of the N+ injection area; further applied to the embodiment of the present invention, the number of steps is 3 to 9; the present invention improves the design of the N+ and source lead holes at the edge of the active area. On the basis of the traditional method, the extension of the lead hole at the edge of the active area and the N+ area is used to collect the lateral current IR1 of the P- area. The problem of premature breakdown of the NPN at the edge of the active area due to the lithography bias is avoided, so as to obtain higher and more stable product EAS characteristics.

[0039] In actual application to the embodiments of the present invention, in the transition zone at the corner of the active area, the source lead hole and the N+ injection area are distributed in a stepped manner. The stepped source lead hole setting can collect the reverse currents IR1 (X) and IR1 (Y) from the transition zone in the X and Y directions, thereby improving the consistency of EAS. Compared with the design method of aligning the source lead with N+ in the prior art, the present invention adopts the source lead hole extension technology to optimize the design of the transition zone for the strip cell product.

[0040] For square or hexagonal cell structures: please refer to Fig. 9 , showing a power MOSFET chip for improving avalanche breakdown energy according to an embodiment of the present invention, the cell structure may include a square structure or a hexagonal structure cell structure, the power MOSFET chip includes a transition zone, an N+ injection zone, and a dummy cell, including: a dummy cell 5 without N+ injection is set in the active area, wherein the transition zone is a transition zone at the straight edge of the active area. In a preferred embodiment, the number of the dummy cells 5 is two or more per column, and the embodiment of the present invention does not impose too many restrictions on this; in the embodiment of the present invention, the transition zone design of the strip cell and the square structure or hexagonal structure cell structure is optimized, including the technology of extending the source lead hole to the N+ zone and adding dummy cells, so as to avoid the influence of the lateral current IR0 of the transition zone on the edge cell VRb of the active area, and increase the consistency of the EAS parameters.

[0041] In another application scenario of the embodiment of the present invention, in the transition zone of the straight edge of the active area, a pseudo cell 5 without N+ injection is additionally provided. The N+ of the pseudo cell 5 is not injected, and there is no NPN parasitic effect, which can be used as the discharge of the IR1 current. Furthermore, the number of the pseudo cells 5 can be two or more per column, and a double-row continuous flow hole technology is adopted. On the basis of the pseudo cell 5, a double drainage hole 8 is provided to increase the drainage area of ​​IR1. P+ injection is performed in the drainage hole area. Therefore, the double drainage hole has a larger total P+ area than the single drainage hole, and the drainage capacity is more than doubled, thereby increasing the ability to collect the transition zone IR1.

[0042] like Figure 5 The prior art uses a single row of continuous flow holes to collect the transition zone IR1. In the technical solution of the present invention, Fig. 9 As shown, the double-row continuous flow hole technology is adopted to increase the ability to collect the transition area IR1. At the same time, the present invention also adds 2 rows of dummy cells in the transition area. The N+ of the dummy cells is not injected, and there is no NPN parasitic effect, which can be used as a discharge of the IR1 current. In the corner area of ​​the square cell active area.

[0043] For square cell products, the present invention adopts double-row follow-up holes and pseudo-cell technology to achieve design optimization of the transition zone.

[0044] Please refer to Fig.10 , showing a power MOSFET chip with improved avalanche breakdown energy according to an embodiment of the present invention, wherein the transition zone is a transition zone at a corner of an active area, and the pseudo-cells of the transition zone at the corner of the active area are in a stepped shape, and 6 represents pseudo-cells with a stepped arrangement.

[0045] like Fig.11 In the prior art, the N+ implantation region and the edge cells are designed to be aligned, while the configuration of the present invention adopts a stepped pseudo-cell design, so that the corners of the active area can simultaneously collect the reverse currents IR1(X) and IR1(Y) from the cross-region in the X and Y directions, thereby improving the consistency of EAS.

[0046] Specifically applied to the embodiments of the present invention, the power MOSFET chip is a trench MOSFET, a separated gate MOSFET, a planar MOSFET, etc., and the embodiments of the present invention do not impose too many restrictions on this; in terms of materials, the power MOSFET chip can be a SiC-based MOSFET, a silicon-based MOSFET, etc., and the embodiments of the present invention also do not impose too many restrictions on this.

[0047] The technical effect achieved by the present invention is: the design of the source lead hole and the N+ injection area of ​​the transition zone is optimized. By improving the design of the straight edge and the corner of the active area, the product can accommodate the photolithography process deviation, avoid the reverse current IR1 in the transition zone, and the current convergence in the cells at the edge of the active area, so that the consistency of the EAS energy of the product is improved, and the early conduction of the parasitic NPN of the cells at the edge of the active area at the moment of MOSFET shutdown is avoided, the EAS energy of the product is improved, the EAS consistency of the MOSFET product is improved, and the probability of the MOSFET being damaged by the energy impact caused by parasitic or load inductance at the moment of shutdown is reduced, the power density of the system and the robustness of the product are improved, and it is beneficial to the parallel connection of MOSFET in high-power MOSFET applications. The number of MOSFETs in parallel at the high-power parallel application end is reduced, the system power density is improved, and the product is developed in the direction of miniaturization, low power consumption, and ultra-high power. The lead holes at the edge of the active area and the extension of the N+ injection area are used to collect the lateral current IR1 in the P- area, avoiding the problem of premature breakdown of the NPN at the edge of the active area due to lithography bias, so as to obtain higher and more stable product EAS characteristics, and at the same time, it can improve the short-circuit resistance of parallel applications and improve system reliability. Because of the improvement of product consistency, the EAS grading action is omitted, saving testing and management costs.

[0048] In the above description of this specification, unless otherwise clearly specified and limited, the terms "fixed", "installed", "connected" or "connected" should be understood in a broad sense. For example, with regard to the term "connection", it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements. Therefore, unless otherwise clearly defined in this specification, those skilled in the art can understand the specific meanings of the above terms in the present invention according to the specific circumstances.

[0049] According to the above description of this specification, those skilled in the art may also understand that the terms used below, such as "up", "down", "front", "back", "left", "right", "length", "width", "thickness", "vertical", "horizontal", "top", "bottom", "inside", "outside", "axial", "radial", "circumferential", "center", "longitudinal", "lateral", "clockwise" or "counterclockwise", etc., which indicate the orientation or position relationship, are based on the orientation or position relationship shown in the drawings of this specification, and are only for the purpose of facilitating the explanation of the scheme of the present invention and simplifying the description, rather than explicitly or implicitly indicating that the device or element involved must have the specific orientation, be constructed and operate in a specific orientation. Therefore, the above-mentioned orientation or position relationship terms cannot be understood or interpreted as limitations on the scheme of the present invention.

Claims

1. A power MOSFET chip with improved avalanche breakdown energy, characterized in that: The power MOSFET chip includes a strip cell structure, and the power MOSFET chip includes a transition area, an N+ injection area, and a source lead hole, including: the source lead hole extends out of the N+ injection area, wherein the transition area is a transition area at the straight edge of the active area and the corner of the active area; the source lead hole and the N+ injection area extend in a stepped shape, and the source lead hole extends out of the N+ injection area; The length of the source lead hole extending out of the N+ injection region is 2 microns or more, the number of the steps is 3 to 9, the source lead hole and the N+ injection region are distributed in a stepped manner, and the stepped source lead hole setting method can collect the reverse currents IR1 (X) and IR1 (Y) from the transition region in the X and Y directions, thereby improving the consistency of the avalanche breakdown energy EAS.

2. The power MOSFET chip with improved avalanche breakdown energy according to claim 1, characterized in that: The power MOSFET chip is a trench MOSFET, a separated gate MOSFET, or a planar MOSFET; or the power MOSFET chip is a SiC-based MOSFET or a silicon-based MOSFET.

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