A storage circuit, a test method and a memory thereof
By introducing a compression circuit and a masking selection signal into the storage circuit, the problem of the inability to accurately locate the failed bit in the chip test in the prior art is solved, the chip test yield is improved and the cost is reduced.
CN118887988BActive Publication Date: 2025-10-03CHANGXIN MEMORY TECH INC
Patent Information
- Application Number
- CN202310453493.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-04-24
- Publication Date
- 2025-10-03
- Estimated Expiration
- 2043-04-24
AI Technical Summary
Technical Problem
The existing technology uses a compressed readout method in chip testing, which makes it impossible to accurately locate the failed bit, resulting in chip waste and increased testing costs.
Method used
A storage circuit is designed, including a storage array and a compression circuit. The read data group is compressed by masking the selection signal, and part of the data is masked to continue testing and locate the fault point.
Benefits of technology
It improves the chip test yield, reduces test costs, screens out more usable chips, and locates fault points.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN118887988B_ABST
Abstract
The present disclosure provides a storage circuit, a test method, and a memory thereof. The storage circuit includes a storage array and a compression circuit. During a test process, after receiving a read instruction, the storage array generates multiple read data groups. The compression circuit compresses the multiple read data groups based on a mask selection signal to generate test result data. The mask selection signal instructs the compression circuit to mask part of the data in the multiple read data groups.
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Citation Information
Patent Citations
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