Dual-gate semiconductor device, preparation method, power module, conversion circuit and vehicle

Abstract

The present invention discloses a dual-gate semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle. The dual-gate semiconductor device includes: a substrate; a semiconductor epitaxial layer, located on one side of the substrate; a first gate trench and a first gate structure; the first gate trench is located on the surface of the semiconductor epitaxial layer away from the substrate, and the first gate structure is located in the first gate trench; a second gate trench and a second gate structure; the second gate trench is located on the side of the first gate trench close to the substrate, and the second gate structure is located in the second gate trench; a first electrode is located on the side of the substrate away from the semiconductor epitaxial layer; a second electrode is located on the surface of the semiconductor epitaxial layer away from the substrate; wherein the first gate structure and the second gate structure synchronously input gate voltage. The technical solution provided by the embodiment of the present invention reduces the on-resistance while increasing the breakdown voltage of the device.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular to a dual-gate semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle. Background Art

[0002] As a representative of the third generation of semiconductor materials, silicon carbide (SiC) has excellent physical and electrical properties. Compared with silicon materials, SiC materials have a large bandgap, high breakdown electric field, high thermal conductivity, high electron saturation rate, and strong radiation resistance. Therefore, semiconductor devices made of SiC materials can not only operate stably at higher temperatures, but are also suitable for high voltage and high frequency scenarios.

[0003] SiC MOSFET has gone through a process from planar type to trench type. By improving the gate structure, the current flow direction on the gate has changed from planar to vertical. Trench-type semiconductor devices have the advantages of small cell size and high current density; however, in trench-type semiconductor devices, the high electric field at the bottom and corner of the trench will increase the electric field on the gate insulation layer, which will make the gate insulation layer easy to be broken down.

[0004] In the related technology, Figure 1 It is a structural schematic diagram of a semiconductor device provided in the prior art. Referring to the figure, the semiconductor device shown in the figure is a trench-type semiconductor device including a shielded gate structure 1. By setting a trench gate structure G and a shielded gate structure 1 located below the trench gate structure G in the same trench, the shielded gate structure 1 is usually connected to the source electrode S, which can improve the problem that the gate insulating layer is easily broken down and improve the breakdown voltage of the device; however, when setting the trench gate structure and the shielded gate structure 1 in the same trench, a deeper trench needs to be set, and the deeper the trench is, the more difficult it is to prepare the device; in addition, for a deeper trench, the thickness of the oxide layer on the trench wall is uneven: the bottom of the trench is seriously "oxygen-deficient", the oxide layer is thin, and the withstand voltage of the oxide layer is determined by this part; the side wall of the top of the trench is "oxygen-rich", the oxide layer is thick, but the stress at this part is large, resulting in serious leakage of the oxide layer; Figure 2 is a schematic diagram of the structure of another semiconductor device provided in the prior art, referring to Figure 2 , a P+ region 2 can also be formed at the bottom of the gate trench as an electric field shielding structure by ion implantation, but the P+ region 2 at the bottom of the gate will easily cause the shielding effect to decrease and fail due to the accumulated charge. Therefore, how to reduce the on-resistance of the semiconductor device while increasing the breakdown voltage of the device is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] Embodiments of the present invention provide a dual-gate semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle, so as to reduce the on-resistance and improve the breakdown voltage of the device at the same time.

[0006] According to one aspect of the present invention, there is provided a dual-gate semiconductor device, comprising:

[0007] substrate;

[0008] A semiconductor epitaxial layer, located on one side of the substrate;

[0009] A first gate trench and a first gate structure; the first gate trench is located on a surface of the semiconductor epitaxial layer away from the substrate, and the first gate structure is located in the first gate trench;

[0010] a second gate trench and a second gate structure; the second gate trench is located on a side of the first gate trench close to the substrate, and the second gate structure is located in the second gate trench;

[0011] A first electrode is located on a side of the substrate away from the semiconductor epitaxial layer;

[0012] A second electrode is located on a surface of the semiconductor epitaxial layer away from the substrate;

[0013] The first gate structure and the second gate structure input gate voltage synchronously.

[0014] Optionally, the semiconductor epitaxial layer includes a drift region, a body region, and a contact region contacting the second electrode, which are sequentially away from the substrate;

[0015] Wherein, the contact region comprises a first doping type contact region and a second doping type contact region; the first doping type contact region is located between the first gate trench and the second doping type contact region;

[0016] The second gate structure extends from the body region into the drift region along a direction perpendicular to the substrate;

[0017] The first gate structure extends from a surface of the contact region away from the substrate along a direction perpendicular to the substrate into the body region or the drift region.

[0018] Optionally, the surface of the semiconductor epitaxial layer away from the substrate includes at least two first gate trenches spaced apart from each other, a first gate structure is correspondingly arranged in each first gate trench; and the second gate structure is arranged in the area between two adjacent first gate structures.

[0019] Optionally, two second gate structures are arranged side by side between two adjacent first gate structures.

[0020] Optionally, a vertical projection of the second gate structure on the substrate does not overlap with a vertical projection of the first gate structure on the substrate, or partially overlaps with the vertical projection of the first gate structure on the substrate.

[0021] Optionally, when a vertical projection of the second gate structure on the substrate does not overlap with a vertical projection of the first gate structure on the substrate, the vertical projection of the second gate structure on the substrate is arranged around the vertical projection of the first gate structure on the substrate.

[0022] Optionally, a distance from a surface of the second gate structure away from the substrate to the substrate is greater than or equal to a distance from a surface of the first gate structure close to the substrate to the substrate.

[0023] Optionally, the dual-gate semiconductor device further comprises:

[0024] an auxiliary doped region, located between the top of the second gate structure and the bottom of the first gate structure; or,

[0025] a current distribution layer, located in the body region between two adjacent first gate structures, covering the top of the second gate structure, and extending from the top of the second gate structure along a direction parallel to the substrate to the first gate structures on both sides of the second trench gate;

[0026] Wherein, the auxiliary doping region and the current distribution layer are both doped with doping ions of the first doping type.

[0027] Optionally, the first gate structure includes a first polysilicon gate and a first gate insulating layer wrapping the first polysilicon gate;

[0028] The second gate structure includes a second polysilicon gate and a second gate insulating layer wrapping the second polysilicon gate;

[0029] Wherein, the thickness of the second gate insulating layer is greater than the thickness of the first gate insulating layer.

[0030] According to another aspect of the present invention, a method for preparing a dual-gate semiconductor device is provided, which is used to prepare the dual-gate semiconductor device according to any embodiment of the present invention, comprising:

[0031] providing a substrate;

[0032] forming a first semiconductor epitaxial sublayer on one side of the substrate;

[0033] forming a second gate trench on a side of the first semiconductor epitaxial sublayer away from the substrate, and forming a second gate structure in the second gate trench;

[0034] forming a second semiconductor epitaxial sublayer on a side of the first semiconductor epitaxial sublayer away from the substrate; the semiconductor epitaxial layer includes the first semiconductor epitaxial sublayer and the second semiconductor epitaxial sublayer;

[0035] forming a first gate trench on a side of the second semiconductor epitaxial sublayer away from the substrate, and forming a first gate structure in the first gate trench;

[0036] A first electrode is formed on a side of the semiconductor epitaxial layer away from the substrate, and a second electrode is formed on a side of the substrate away from the semiconductor epitaxial layer; wherein, when the dual-gate semiconductor device is in operation, the first gate structure and the second gate structure synchronously input gate voltages.

[0037] Optionally, after forming a second semiconductor epitaxial sublayer on a side of the first semiconductor epitaxial sublayer away from the substrate, the method further comprises:

[0038] Based on the patterned mask, ion implantation is performed in the first semiconductor epitaxial sublayer and the second semiconductor epitaxial sublayer to form a drift region, a body region, and a contact region contacting the second electrode in the semiconductor epitaxial layer, which are sequentially away from the substrate;

[0039] Wherein, the contact region includes a first doping type contact region and a second doping type contact region; the first doping type contact region is located between the first gate trench and the second doping type contact region; the second gate structure extends from the body region along a direction perpendicular to the substrate to the drift region; the first gate structure extends from the surface of the contact region away from the substrate side, along a direction perpendicular to the substrate to the body region or the drift region.

[0040] Optionally, the second gate structure includes a second polysilicon gate and a second gate insulating layer wrapping the second polysilicon gate; forming the second gate structure in the second gate trench includes:

[0041] forming a first insulating sublayer on the wall of the second gate trench and on the surface of the first semiconductor epitaxial sublayer away from the substrate;

[0042] Filling the second gate trench with polysilicon material, and etching back the polysilicon material until the surface of the polysilicon material away from the substrate is lower than the surface of the first semiconductor epitaxial sublayer away from the substrate, so as to form the second polysilicon gate;

[0043] forming a second insulating sublayer on a side of the second polysilicon gate away from the substrate;

[0044] The second insulating sublayer and the first insulating sublayer are sequentially ground until the surface of the first semiconductor epitaxial sublayer away from the substrate is exposed; wherein the ground second insulating sublayer does not expose the surface of the second polysilicon gate away from the substrate; the first insulating sublayer located on the wall of the second gate trench and the second insulating sublayer located on the top of the second polysilicon gate are used to constitute the second gate insulating layer.

[0045] Optionally, after forming a second gate trench on a side of the first semiconductor epitaxial sublayer away from the substrate, the method further includes:

[0046] forming a first sacrificial oxide layer on the wall of the second gate trench, and removing the first sacrificial oxide layer;

[0047] And / or, after forming a first gate trench on a side of the second semiconductor epitaxial sublayer away from the substrate, the method further comprises:

[0048] forming a carbon film on the groove wall of the first gate groove, passivating the groove wall with argon gas and performing high-temperature annealing treatment, and then removing the carbon film;

[0049] A second sacrificial oxide layer is formed on the wall of the first gate trench, and the second sacrificial oxide layer is removed.

[0050] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one dual-gate semiconductor device according to any one of the embodiments of the present invention, wherein the substrate is used for carrying the dual-gate semiconductor device.

[0051] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0052] The power conversion circuit comprises a circuit board and at least one dual-gate semiconductor device according to any one of the embodiments of the present invention, wherein the dual-gate semiconductor device is electrically connected to the circuit board.

[0053] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in any embodiment of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0054] The technical solution provided by the embodiment of the present invention is to set a first gate trench on the surface of the semiconductor epitaxial layer away from the substrate side and set a first gate structure in the first gate trench, and set a second gate trench on the side of the first gate trench close to the substrate and set a second gate structure in the second gate trench, wherein the first gate structure and the second gate structure synchronously input gate voltage, the first gate structure serves as the main gate, and the second gate structure serves as the bottom gate, and the two gates (bottom gate and main gate) can be used to control the device at the same time, so that the device has a lower on-resistance when turned on and a higher breakdown voltage when turned off; in addition, the second gate trench where the second gate structure is located and the first gate trench where the first gate structure is located are separately arranged, that is, the second gate structure and the first gate structure are not located in the same trench, which can reduce the difficulty of preparing the gate trench and also avoid the problem of uneven oxide layer thickness.

[0055] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0057] Figure 1 It is a structural schematic diagram of a semiconductor device provided in the prior art;

[0058] Figure 2 It is a schematic structural diagram of another semiconductor device provided in the prior art;

[0059] Figure 3 is a schematic structural diagram of a dual-gate semiconductor device provided by an embodiment of the present invention;

[0060] Figure 4 is a schematic structural diagram of another dual-gate semiconductor device provided by an embodiment of the present invention;

[0061] Figure 5 is a schematic structural diagram of another dual-gate semiconductor device provided by an embodiment of the present invention;

[0062] Figure 6 is a schematic structural diagram of another dual-gate semiconductor device provided by an embodiment of the present invention;

[0063] Figure 7is a schematic structural diagram of another dual-gate semiconductor device provided by an embodiment of the present invention;

[0064] Figure 8 is a schematic structural diagram of another dual-gate semiconductor device provided by an embodiment of the present invention;

[0065] Fig. 9 is a schematic structural diagram of another dual-gate semiconductor device provided by an embodiment of the present invention;

[0066] Fig.10 is a schematic structural diagram of another dual-gate semiconductor device provided by an embodiment of the present invention;

[0067] Fig.11 is a schematic structural diagram of another dual-gate semiconductor device provided by an embodiment of the present invention;

[0068] Fig.12 is a top view of a first polysilicon gate and a second polysilicon gate provided by an embodiment of the present invention;

[0069] Fig.13 is a flow chart of a method for preparing a dual-gate semiconductor device provided by an embodiment of the present invention;

[0070] Fig.14 It is a structural schematic diagram corresponding to step S120 in a method for preparing a semiconductor device with multiple channels provided in an embodiment of the present invention;

[0071] Figure 15 to Figure 19 It is a structural schematic diagram corresponding to step S130 in a method for preparing a semiconductor device with multiple channels provided in an embodiment of the present invention;

[0072] Fig. 20 It is a structural schematic diagram corresponding to step S140 in a method for preparing a semiconductor device with multiple channels provided in an embodiment of the present invention;

[0073] Fig.21 It is a structural schematic diagram corresponding to step S1401 in a method for preparing a semiconductor device with multiple channels provided in an embodiment of the present invention;

[0074] Figure 22-23 It is a structural schematic diagram corresponding to step S150 in a method for preparing a semiconductor device with multiple channels provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0075] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0076] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0077] An embodiment of the present invention provides a dual-gate semiconductor device. Figure 3 is a schematic structural diagram of a dual-gate semiconductor device provided by an embodiment of the present invention, Figure 4 is a schematic diagram of the structure of another dual-gate semiconductor device provided by an embodiment of the present invention, referring to Figure 3 and Figure 4 , the dual-gate semiconductor device comprises:

[0078] Substrate 10;

[0079] A semiconductor epitaxial layer 20 is located on one side of the substrate 10;

[0080] A first gate trench and a first gate structure 30; the first gate trench is located on a surface of the semiconductor epitaxial layer 20 away from the substrate 10, and the first gate structure 30 is located in the first gate trench;

[0081] A second gate trench and a second gate structure 40; the second gate trench is located on a side of the first gate trench close to the substrate 10, and the second gate structure 40 is located in the second gate trench;

[0082] A first electrode 50 is located on a side of the substrate 10 away from the semiconductor epitaxial layer 20;

[0083] The second electrode 60 is located on the surface of the semiconductor epitaxial layer 20 away from the substrate 10;

[0084] The first gate structure 30 and the second gate structure 40 are synchronously input with a gate voltage.

[0085] Specifically, the material of the substrate 10 and the material of the semiconductor epitaxial layer 20 may be the same or different. In the embodiment of the present invention, the material of the substrate 10 and the material of the semiconductor epitaxial layer 20 are the same, and both may be SiC. That is, the trench power device in the embodiment of the present invention may be a trench SiC power device. SiC has excellent physical and electrical properties.

[0086] The semiconductor epitaxial layer 20 includes a first semiconductor epitaxial sublayer located on one side of the substrate 10 and a second semiconductor epitaxial sublayer located on the side of the first semiconductor epitaxial sublayer away from the substrate 10. The second gate trench is formed on the surface of the first semiconductor epitaxial sublayer away from the substrate 10; the first gate trench is formed on the surface of the second semiconductor epitaxial sublayer away from the substrate 10. The surface of the second semiconductor epitaxial sublayer away from the substrate 10 is the surface of the semiconductor epitaxial layer 20 away from the substrate 10. The first gate structure 30 includes a first polysilicon gate 31 and a first gate insulating layer 32 wrapping the first polysilicon gate 31. The second gate structure 40 includes a second polysilicon gate 41 and a second gate insulating layer 42 wrapping the second polysilicon gate 41. When preparing the first gate structure 30 and the second gate structure 40, a gate insulating layer is first formed on the sidewall and bottom of the gate trench where each is located, and then a polysilicon material is filled to form a polysilicon gate. The materials of the first gate insulating layer 32 and the second gate insulating layer 42 may include at least one of aluminum oxide and silicon oxide.

[0087] By separately arranging the second gate trench where the second gate structure 40 is located and the first gate trench where the first gate structure 30 is located, so that the second gate structure 40 and the first gate structure 30 are not located in the same trench, the depth of the trench can be reduced, thereby reducing the difficulty of preparing the first gate trench and the second gate trench. At the same time, it can prevent the first gate insulation layer 32 on the upper part of the side wall of the first gate trench from being too thick and the first gate insulation layer 32 on the bottom of the side wall of the first gate trench from being too thin, and prevent the second gate insulation layer 42 on the upper part of the side wall of the second gate trench from being too thick and the second gate insulation layer 42 on the bottom of the side wall of the second gate trench from being too thin, thereby improving the uniformity of the thickness of the first gate insulation layer 32 in the first gate trench and the uniformity of the thickness of the second gate insulation layer 42 in the second gate trench, thereby avoiding the problem of uneven thickness of the oxide layer (the first gate insulation layer 32 and the second gate insulation layer 42) caused by the deep depth of the trench.

[0088] The materials of the first electrode 50 and the second electrode 60 may both include metal materials. The first electrode 50 may be a drain electrode D, and the second electrode 60 may be a source electrode S; or the first electrode 50 may be a source electrode S, and the second electrode 60 may be a drain electrode D. In the embodiment of the present invention, the first electrode 50 is a drain electrode D, and the second electrode 60 is a source electrode S. When controlling the dual-gate semiconductor device to be turned on, the first gate structure 30 and the second gate structure 40 are synchronously input with a gate voltage, and an inversion layer is formed on both sides of the second gate structure 40, which helps to reduce the on-resistance in the on state; at the same time, by setting the second gate structure 40 (bottom gate), the electric field strength from the drain end to the first gate structure 30 (main gate) can be reduced, and the risk of breakdown of the first gate insulation layer 32 at the bottom of the first gate structure 30 is reduced, thereby increasing the breakdown voltage of the semiconductor device.

[0089] The technical solution provided by the embodiment of the present invention is to set a first gate trench on the surface of the semiconductor epitaxial layer away from the substrate side and a first gate structure in the first gate trench, and set a second gate trench on the side of the first gate trench close to the substrate and a second gate structure in the first gate trench, wherein the first gate structure and the second gate structure synchronously input gate voltage, the first gate structure serves as a main gate, and the second gate structure serves as a bottom gate, and two gates (bottom gate and main gate) can be used for control at the same time, so that the device has a lower on-resistance when turned on and a higher breakdown voltage when turned off; in addition, the second gate trench where the second gate structure is located and the first gate trench where the first gate structure is located are separately arranged, that is, the second gate structure and the first gate structure are not located in the same trench, which can reduce the difficulty of preparing the gate trench and also avoid the problem of uneven oxide layer thickness.

[0090] The above is the core inventive concept of the present invention. The semiconductor device with multiple channels is described in detail below with reference to the accompanying drawings.

[0091] Based on the above embodiments, optionally, refer to Figure 3 and Figure 4 The surface of the semiconductor epitaxial layer 20 away from the substrate 10 includes at least two first gate trenches arranged at intervals, and a first gate structure 30 is correspondingly arranged in each first gate trench; wherein a second gate structure 40 is arranged in the area between two adjacent first gate structures 30.

[0092] Different from related technologies Figure 1In the structure shown, a shielding gate structure 1 is arranged directly below the main gate. The bottom gate (second gate structure 40) in the embodiment of the present invention is located below the two main gates (first gate structures 30). According to the actual design requirements of the device, the bottom gate can be freely placed at any position between the two main gates, and the number of second gate structures 40 between two adjacent first gate structures 30 can also be set according to actual requirements. In the semiconductor device, the number of second gate structures 40 is an integer multiple of half the number of first gate structures 30. Figure 4 In the embodiment, a second gate structure 40 is disposed in the region between two adjacent first gate structures 30; Figure 3 In the embodiment, two second gate structures 40 are arranged side by side between two adjacent first gate structures 30 .

[0093] Based on the above embodiments, please continue to refer to Figure 3 and Figure 4 The semiconductor epitaxial layer 20 includes a drift region 21, a body region 22 and a contact region in contact with the second electrode 60, which are sequentially away from the substrate 10; wherein the contact region includes a first doping type contact region 231 and a second doping type contact region 232; the first doping type contact region 231 is located between the first gate trench and the second doping type contact region 232.

[0094] Specifically, the doping type of the first doping type contact region 231 may be N-type, and the doping type of the second doping type contact region 232 may be P-type. Alternatively, the doping type of the first doping type contact region 231 may be P-type, and the doping type of the second doping type contact region 232 may be N-type. The doping type of the drift region 21 is the same as the doping type of the first doping type contact region 231, and the ion doping concentration of the drift region 21 is less than the ion doping concentration of the first doping type contact region 231. The doping type of the body region 22 is the same as the doping type of the second doping type contact region 232, and the ion doping concentration of the body region 22 is less than the ion doping concentration of the second doping type contact region 232.

[0095] Figure 3 and Figure 4 In the figure, it is exemplarily shown that the first doping type contact region 231 and the drift region 21 are doped with N-type doping ions; the second doping type contact region 232 and the body region 22 are doped with P-type doping ions. P+ and N+ shown in the figure indicate that the ion doping concentration in the region is high, and P- and N- indicate that the ion doping concentration in the region is low. Among them, the N-type doping ions can be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions can be Al (aluminum) ions or B (boron) ions.

[0096] The second gate structure 40 extends from the body region 22 to the drift region 21 along a direction perpendicular to the substrate 10 ; the first gate structure 30 extends from the surface of the contact region away from the substrate 10 side to the body region 22 or the drift region 21 along a direction perpendicular to the substrate 10 . Figure 3 and Figure 4 In the example, the second gate structure 40 is shown to extend from the body region 22 to the drift region 21 along a direction perpendicular to the substrate 10; the first gate structure 30 extends from the surface of the contact region away from the substrate 10 to the body region 22 along a direction perpendicular to the substrate 10. Figure 5 and Figure 6 , exemplarily showing that the second gate structure 40 extends from the body region 22 to the drift region 21 along a direction perpendicular to the substrate 10 ; the first gate structure 30 extends from the surface of the contact region away from the substrate 10 side to the drift region 21 along a direction perpendicular to the substrate 10 .

[0097] Preferably, the first gate structure 30 extends from the surface of the contact region away from the substrate 10 side to the body region 22 along a direction perpendicular to the substrate 10. The main gate is embedded in the body region 22, which can reduce the depth of the main gate trench and further avoid the problem of uneven thickness of the oxide layer on the main gate trench wall. In addition, since the electric field is mainly concentrated between the body region 22 and the drift region 21, the main gate is embedded in the body region 22, which can also avoid the problem of easy breakdown of the gate insulation layer (32) at the two sides of the bottom edge of the main gate.

[0098] Based on the above embodiments, optionally, refer to Figure 3 to Figure 6 , the thickness of the second gate insulating layer 42 is greater than the thickness of the first gate insulating layer 32 .

[0099] Specifically, since the second gate structure 40 extends from the body region 22 to the drift region 21 along a direction perpendicular to the substrate 10, and since the electric field is mainly concentrated between the body region 22 and the drift region 21, the thickness of the second gate insulating layer 42 is greater than the thickness of the first gate insulating layer 32, which can reduce the risk of breakdown of the second gate insulating layer 42 in the second gate structure 40. However, it should be noted that by increasing the thickness of the second gate insulating layer 42, the speed of generating the inversion layer in the body region 22 outside the second gate insulating layer 42 will be slowed down (when the bottom gate voltage changes), and the current mobility will also be lowered. In the embodiment of the present invention, the thickness of the second gate insulating layer 42 ranges from 100A to 200A, which can prevent the second gate insulating layer 42 from being broken down due to the thickness of the second gate insulating layer 42 being too thin; and prevent the second gate insulating layer 42 from being too thick, which can slow down the speed of generating the inversion layer in the body region 22 outside the second gate insulating layer 42 and reduce the current mobility.

[0100] Based on the above embodiments, Figure 7and Figure 8 In one embodiment of the present invention, the dual-gate semiconductor device further includes: an auxiliary doping region 71 located between the top of the second gate structure 40 and the bottom of the first gate structure 30; the auxiliary doping region 71 is doped with doping ions of the first doping type.

[0101] Based on the above embodiments, Fig. 9 and Fig.10 In another embodiment of the present invention, the dual-gate semiconductor device further includes: a current distribution layer 72, which is located in the body region 22 between two adjacent first gate structures 30, covers the top of the second gate structure 40, and extends from the top of the second gate structure 40 along a direction parallel to the substrate 10 to the first gate structures 30 on both sides of the second trench gate; wherein the current distribution layer 72 is doped with dopant ions of the second doping type.

[0102] Specifically, the current distribution layer 72 is a film layer structure doped with doping ions of the second doping type formed in the semiconductor epitaxial layer 20. The auxiliary doping region 71 is formed by implanting doping ions of the second doping type in the semiconductor epitaxial layer 20. Both can play a role in reducing the on-resistance (highly doped semiconductors have the characteristic of low resistance).

[0103] Based on the above embodiments, Fig.11 is a schematic diagram of the structure of another dual-gate semiconductor device provided by an embodiment of the present invention, referring to Figure 3 to Figure 11 Optionally, a distance from a surface of the second gate structure 40 away from the substrate 10 to the substrate 10 is greater than or equal to a distance from a surface of the first gate structure 30 close to the substrate 10 to the substrate 10 .

[0104] in, Figures 3 to 10 The example in FIG. 4 shows that the distance between the surface of the second gate structure 40 away from the substrate 10 and the substrate 10 is greater than the distance between the surface of the first gate structure 30 close to the substrate 10 and the substrate 10 . Fig.11 The example shows that the distance from the surface of the second gate structure 40 away from the substrate 10 to the substrate 10 is equal to the distance from the surface of the first gate structure 30 close to the substrate 10 to the substrate 10. Setting the distance from the surface of the second gate structure 40 away from the substrate 10 to the substrate 10 to be greater than or equal to the distance from the surface of the first gate structure 30 close to the substrate 10 to the substrate 10 can facilitate the current on the side wall of the second gate structure 40 to flow to the side wall of the first gate structure 30, and then flow to the second electrode 60 along the side wall of the first gate structure 30.

[0105] Based on the above embodiments, Figure 3 to Figure 11Optionally, the vertical projection of the second gate structure 40 on the substrate 10 does not overlap with the vertical projection of the first gate structure 30 on the substrate 10, or partially overlaps. Figures 3 to 10 The example in FIG. 4 shows that the vertical projection of the second gate structure 40 on the substrate 10 does not overlap with the vertical projection of the first gate structure 30 on the substrate 10 . Fig.11 The example in FIG. 4 shows that the vertical projection of the second gate structure 40 on the substrate 10 partially overlaps with the vertical projection of the first gate structure 30 on the substrate 10 .

[0106] In the case where the vertical projection of the second gate structure 40 on the substrate 10 does not overlap with the vertical projection of the first gate structure 30 on the substrate 10, Fig.12 is a top view of a first polysilicon gate 31 and a second polysilicon gate 41 provided in an embodiment of the present invention, with reference to Fig.12 The vertical projection of the second gate structure 40 on the substrate 10 can be arranged around the vertical projection of the first gate structure 30 on the substrate 10. Thus, the risk of the first gate insulating layer 32 at the bottom of the first polysilicon gate 31 being broken down can be reduced from all directions.

[0107] The embodiment of the present invention further provides a method for preparing a dual-gate semiconductor device, which is used to prepare the dual-gate semiconductor device described in any of the above embodiments. Fig.13 is a flow chart of a method for preparing a dual-gate semiconductor device provided by an embodiment of the present invention, with reference to Fig.13 , a method for preparing a dual-gate semiconductor device comprises:

[0108] S110 , providing a substrate.

[0109] S120 , forming a first semiconductor epitaxial sublayer on one side of the substrate.

[0110] Specifically, refer to Fig.14 , the material of the substrate 10 and the material of the first semiconductor epitaxial sublayer 201 may be the same or different. In an embodiment of the present invention, the material of the substrate 10 and the material of the first semiconductor epitaxial sublayer 201 are the same, and both may be SiC. In some embodiments of the present invention, the substrate 10 and the first semiconductor epitaxial sublayer 201 may be integrally provided. The substrate 10 and the first semiconductor epitaxial sublayer 201 being integrally provided may be understood as the substrate 10 and the first semiconductor epitaxial sublayer 201 being a whole SiC film layer structure formed in the same preparation process.

[0111] S130, forming a second gate trench on a side of the first semiconductor epitaxial sublayer away from the substrate, and forming a second gate structure in the second gate trench.

[0112] Specifically, forming a second gate trench on a side of the first semiconductor epitaxial sublayer away from the substrate in step S130 may include:

[0113] S131, forming a second gate trench 01 on the side of the first semiconductor epitaxial sublayer 201 away from the substrate 10 by photolithography. (For details, please refer to Fig.15 )

[0114] The specific steps may include: depositing SiO2 as a mask layer on the surface of the first semiconductor epitaxial sublayer 201 away from the substrate 10 by a deposition process such as CVD, spin-coating a photoresist PR on the surface of the mask layer, forming a photoresist PR of a desired pattern by exposure and development, and then etching the mask layer based on the patterned photoresist PR to pattern the mask layer. The patterned mask layer exposes the preset position of the second gate trench 01. Based on the patterned mask layer, the first semiconductor epitaxial sublayer 201 is etched to form the second gate trench 01. Among them, the etching process can adopt a plasma dry etching process, such as RIE or ICP etching process.

[0115] Further, after forming the second gate trench 01 on the side of the first semiconductor epitaxial sublayer 201 away from the substrate 10, the method further includes: forming a first sacrificial oxide layer on the groove wall of the second gate trench 01 to repair the lattice on the groove surface of the first semiconductor epitaxial sublayer 201, and removing the first sacrificial oxide layer. The sacrificial oxide layer on the surface can be removed by BOE cleaning.

[0116] The step S130 of forming a second gate structure in the second gate trench may include:

[0117] S132, forming a first insulating sublayer on the wall of the second gate trench and the surface of the first semiconductor epitaxial sublayer away from the substrate. Fig.16 The material of the first insulating sublayer 421 may include at least one of SiO 2 and Al 2 O 3 , and the preparation method of the first insulating sublayer 421 may be at least one of ALD, thermal oxidation, and wet method.

[0118] S133, filling the second gate trench with polysilicon material, and etching back the polysilicon material until the surface of the polysilicon material away from the substrate is lower than the surface of the first semiconductor epitaxial sublayer away from the substrate, so as to form a second polysilicon gate. Fig.17 , deposit polysilicon material, and then use a dry etching process to etch the polysilicon material to 0.1um-0.5um below the surface of the first semiconductor epitaxial sublayer 201 away from the substrate 10, and the polysilicon material retained in the second gate trench 01 forms a second polysilicon gate 41.

[0119] S134, forming a second insulating sublayer on a side of the second polysilicon gate away from the substrate. Fig.18 The material of the second insulating sublayer 422 may include at least one of SiO 2 and Al 2 O 3 , and the preparation method of the second insulating sublayer 422 may be at least one of ALD, thermal oxidation, and wet method.

[0120] S135, grinding the second insulating sublayer and the first insulating sublayer in sequence until the surface of the first semiconductor epitaxial sublayer away from the substrate is exposed; wherein the ground second insulating sublayer does not expose the surface of the second polysilicon gate away from the substrate.

[0121] Specifically, refer to Fig.19 , the second insulating sublayer 422 and the first insulating sublayer 421 are sequentially ground by CMP until the surface of the first semiconductor epitaxial sublayer 201 away from the substrate 10 is exposed. A portion of the first semiconductor epitaxial sublayer 201 can be ground to ensure that the insulating sublayer on the surface of the first semiconductor epitaxial sublayer 201 is completely removed. It should be noted that the second insulating sublayer 422 after grinding exposes the surface of the second polysilicon gate 41 away from the substrate 10 to isolate the second polysilicon gate 41 from the body region 22. The first insulating sublayer located on the groove wall of the first gate trench 02 and the second insulating sublayer located on the top of the second polysilicon gate 41 are used to form the second gate insulating layer 42. The above-mentioned etching of the polysilicon material to 0.1um-0.5um below the surface of the first semiconductor epitaxial sublayer 201 away from the substrate 10 includes ensuring that after the second insulating sublayer 422 and the first insulating sublayer 421 are sequentially ground, the second insulating sublayer 422 does not expose the surface of the second polysilicon gate 41 away from the substrate 10.

[0122] S140, forming a second semiconductor epitaxial sublayer on a side of the first semiconductor epitaxial sublayer away from the substrate; the semiconductor epitaxial layer includes the first semiconductor epitaxial sublayer and the second semiconductor epitaxial sublayer. Fig. 20 A second semiconductor epitaxial sublayer 202 is formed on the side of the first semiconductor epitaxial sublayer 201 away from the substrate 10 . The material of the second semiconductor epitaxial sublayer 202 is the same as that of the first semiconductor epitaxial sublayer 201 , which may be SiC. The semiconductor epitaxial layer 20 includes the first semiconductor epitaxial sublayer 201 and the second semiconductor epitaxial sublayer 202 .

[0123] refer to Fig.21After forming the second semiconductor epitaxial sublayer 202 on the side of the first semiconductor epitaxial sublayer 201 away from the substrate 10, the method further includes: S141, based on the patterned mask, ion implantation is performed in the first semiconductor epitaxial sublayer 201 and the second semiconductor epitaxial sublayer 202 to form a drift region 21, a body region 22 and a contact region 23 in contact with the second electrode 60 in the semiconductor epitaxial layer 20, which are sequentially away from the substrate 10. The contact region 23 includes a first doping type contact region 231 and a second doping type contact region 232 which are sequentially arranged.

[0124] Specifically, the pattern of the mask can be transferred to the SiO2 mask layer by using PECVD and photolithography technology, and then the semiconductor epitaxial layer 20 is frontally ion-implanted based on the patterned mask layer to form a drift region 21, a body region 22, and a contact region in contact with the second electrode 60 in the semiconductor epitaxial layer 20, which are sequentially away from the substrate 10, and then the mask layer is removed. Different patterned mask layers can be used when ion implanting different regions. After ion implantation, it is necessary to ensure that the second gate structure 40 extends from the body region 22 to the drift region 21 in a direction perpendicular to the substrate 10.

[0125] S150, forming a first gate trench on a side of the second semiconductor epitaxial sublayer away from the substrate, and forming a first gate structure in the first gate trench.

[0126] Specifically, forming a first gate trench on a side of the second semiconductor epitaxial sublayer away from the substrate in step S150 may include:

[0127] S151, forming a first gate trench 02 on a side of the second semiconductor epitaxial sublayer 202 away from the substrate 10 by photolithography. (See Fig. 22 The step of forming the first gate trench 02 by photolithography process can refer to step S131, which will not be described in detail here.

[0128] It should be noted that when etching to form the first gate trench 02, the contact region (first doping type contact region 231) and part of the body region 22 may be sequentially etched from the surface of the contact region away from the substrate 10 to form the first gate trench 02 with the bottom located in the body region 22 (refer to Fig. 22 Alternatively, the contact region 23 (first doping type contact region 231 ), the body region 22 and part of the drift region 21 are sequentially etched from the surface of the contact region away from the substrate 10 to form a first gate trench 02 (not shown) with the bottom located in the drift region 21 .

[0129] Preferably, the contact area (first doping type contact area 231231) and part of the body area 22 are etched in sequence from the surface of the contact area away from the substrate 10 to form a first gate trench 02 with the bottom located in the body area 22, so as to reduce the difficulty of preparing the first gate trench 02, improve the problem of uneven thickness of the oxide layer formed on the groove wall of the first gate trench 02, and reduce the risk of breakdown of the oxide layer at the bottom of the first gate trench 02.

[0130] Furthermore, after forming the first gate trench 02 on the side of the second semiconductor epitaxial sublayer 202 away from the substrate 10, the method further includes:

[0131] A second carbon film is formed on the groove wall of the first gate groove 02, and the groove wall is passivated by argon gas and subjected to high-temperature annealing treatment, and then the second carbon film is removed;

[0132] A second sacrificial oxide layer is formed on the wall of the first gate trench 02, and then the second sacrificial oxide layer is removed.

[0133] Specifically, in order to activate the implanted doping ions and eliminate the lattice damage defects caused by the implantation of doping ions, the semiconductor epitaxial layer 20 needs to be activated annealed at a high temperature, and the temperature is generally as high as 1600°C to 1800°C. However, at such a high activation annealing temperature, since the material of the semiconductor epitaxial layer 20 is silicon carbide, the Si on the surface of silicon carbide is easily sublimated from the surface of SiC, and re-deposited on the surface of the wafer in the form of Si, Si2C, SiC2, etc., forming a step cluster, resulting in an increase in the surface roughness of the SiC sheet and an increase in the interface state density, which seriously affects the performance of the device. The commonly used method for high-temperature annealing is a carbon film protection method, and its preparation method is generally sputtering a carbon film protective layer or forming a carbon film protective layer by baking and curing a photoresist. After the high-temperature annealing is completed, the carbon film used to protect the surface of silicon carbide needs to be removed. If the carbon film is not removed cleanly, it will affect the ohmic contact, seriously affecting the switching characteristics, conductive characteristics, withstand voltage characteristics and other performances of the device. The carbon film can be removed by immersion in a chemical solution, and the chemical solution is mostly a certain concentration of hydrochloric acid plus a certain amount of nitric acid as a catalyst. After removing the carbon film on the surface of the semiconductor epitaxial layer 20, a sacrificial oxide layer is formed on the surface of the semiconductor epitaxial layer 20 by a thermal oxidation process to repair the lattice on the surface of the semiconductor epitaxial layer 20, and then the sacrificial oxide layer is removed. The sacrificial oxide layer on the surface can be removed by BOE cleaning.

[0134] The step S150 of forming a second gate structure in the first gate trench may include:

[0135] S152 , forming a first gate insulating layer 32 on the wall of the first gate trench 02 and the surface of the first semiconductor epitaxial sublayer 201 away from the substrate 10 .

[0136] S153 , filling the first gate trench 02 with polysilicon material to form a first polysilicon gate 31 .

[0137] Specifically, refer to Fig.23 The material of the first gate insulating layer 32 may include at least one of SiO2 and Al2O3, and the preparation method of the first insulating sublayer may be at least one of ALD, thermal oxidation, and wet method. The thickness of the first gate insulating layer 32 may range from 40A to 50A. Polysilicon material is filled in the first gate trench 02 to form a first polysilicon gate 31. The second gate structure 40 includes a first polysilicon gate 31 and a first gate insulating layer 32 that wraps the first polysilicon gate 31.

[0138] Figure 14 to Figure 23 The method for preparing a dual-gate semiconductor device is exemplarily shown in which the surface of the semiconductor epitaxial layer 20 away from the substrate 10 includes at least two first gate trenches 02 arranged at intervals, and the region between the two adjacent first gate structures 30 is provided with two side-by-side second gate structures 40. In other embodiments of the present invention, a second gate structure 40 may be provided in the region between the two adjacent first gate structures 30. According to the actual design requirements of the device, the second gate structure 40 may be freely placed at any position between the two main gates, and the number of the second gate structures 40 between the two adjacent first gate structures 30 may also be set according to actual requirements. Therefore, when forming the second gate trench 01 and the first gate trench 02, the relative positions and respective numbers of the second gate trench 01 and the first gate trench 02 should be set according to the relative positions and respective numbers of the first gate structure 30 and the second gate structure 40. In addition, the depth of the second trench gate and the depth of the first trench gate can be set according to actual needs, so that the formed semiconductor device meets the requirement that the distance from the surface of the second gate structure 40 away from the substrate 10 to the substrate 10 is greater than or equal to the distance from the surface of the first gate structure 30 away from the substrate 10 to the substrate 10.

[0139] S160, forming a first electrode on a side of the semiconductor epitaxial layer away from the substrate, and forming a second electrode on a side of the substrate away from the semiconductor epitaxial layer; wherein, when the dual-gate semiconductor device is in operation, the first gate structure and the second gate structure synchronously input gate voltages. (For details, please refer to Figure 3 )

[0140] After forming the second electrode 60 on the side of the substrate 10 away from the semiconductor epitaxial layer 20, the first electrode 50 may be formed on the side of the semiconductor epitaxial layer 20 away from the substrate 10. It should be noted that before forming the first electrode 50 on the surface of the substrate 10 away from the semiconductor epitaxial layer 20, the substrate 10 may be thinned from the side of the substrate 10 away from the semiconductor epitaxial layer 20, and the substrate 10 may be heavily doped with the first doping ions, so that the doping concentration of the first doping ions in the substrate 10 is greater than the doping concentration of the first doping ions in the drift region 21.

[0141] The embodiment of the present invention further provides a power module, comprising a substrate and at least one dual-gate semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the dual-gate semiconductor device. The two devices have the same technical effects and are not described in detail here.

[0142] The embodiment of the present invention further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one dual-gate semiconductor device as described in any embodiment of the present invention, and the dual-gate semiconductor device is electrically connected to the circuit board. The same technical effects are achieved, which will not be described in detail here.

[0143] The embodiment of the present invention further provides a vehicle, comprising a load and a power conversion circuit as described in any embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load. The same technical effects are achieved, which will not be described in detail here.

[0144] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A dual-gate semiconductor device, characterized in that: include: substrate; A semiconductor epitaxial layer, located on one side of the substrate; a first gate trench and a first gate structure; The first gate trench is located on a surface of the semiconductor epitaxial layer away from the substrate, and the first gate structure is located in the first gate trench; a second gate trench and a second gate structure; the second gate trench is located on a side of the first gate trench close to the substrate, and the second gate structure is located in the second gate trench; A first electrode is located on a side of the substrate away from the semiconductor epitaxial layer; A second electrode is located on a surface of the semiconductor epitaxial layer away from the substrate; The first gate structure and the second gate structure are synchronously input with a gate voltage; the semiconductor epitaxial layer comprises a drift region, a body region and a contact region contacting the second electrode in sequence away from the substrate; the second gate structure extends from the body region to the drift region along a direction perpendicular to the substrate; The first gate structure extends from a surface of the contact region away from the substrate to the body region along a direction perpendicular to the substrate.

2. The dual-gate semiconductor device according to claim 1, characterized in that: The contact region includes a first doping type contact region and a second doping type contact region; the first doping type contact region is located between the first gate trench and the second doping type contact region.

3. The dual-gate semiconductor device according to claim 1, characterized in that: The surface of the semiconductor epitaxial layer away from the substrate includes at least two first gate trenches arranged at intervals, and a first gate structure is correspondingly arranged in each first gate trench; the second gate structure is arranged in the area between two adjacent first gate structures.

4. The dual-gate semiconductor device according to claim 3, characterized in that: Two second gate structures are arranged side by side between two adjacent first gate structures.

5. The dual-gate semiconductor device according to claim 1, characterized in that: A vertical projection of the second gate structure on the substrate does not overlap with, or partially overlaps with, a vertical projection of the first gate structure on the substrate.

6. The dual-gate semiconductor device according to claim 5, characterized in that: When the vertical projection of the second gate structure on the substrate does not overlap with the vertical projection of the first gate structure on the substrate, the vertical projection of the second gate structure on the substrate is arranged around the vertical projection of the first gate structure on the substrate.

7. The dual-gate semiconductor device according to claim 1, characterized in that: The distance between the surface of the second gate structure away from the substrate and the substrate is greater than or equal to the distance between the surface of the first gate structure close to the substrate and the substrate.

8. The dual-gate semiconductor device according to claim 2, characterized in that: Also includes: an auxiliary doped region, located between a top of the second gate structure and a bottom of the first gate structure; or, a current distribution layer, located in the body region between two adjacent first gate structures, covering the top of the second gate structure, and extending from the top of the second gate structure to the first gate structures on both sides along a direction parallel to the substrate; Wherein, the auxiliary doping region and the current distribution layer are both doped with doping ions of the first doping type.

9. The dual-gate semiconductor device according to any one of claims 1 to 8, characterized in that: The first gate structure includes a first polysilicon gate and a first gate insulating layer wrapping the first polysilicon gate; The second gate structure includes a second polysilicon gate and a second gate insulating layer wrapping the second polysilicon gate; Wherein, the thickness of the second gate insulating layer is greater than the thickness of the first gate insulating layer.

10. A method for preparing a dual-gate semiconductor device, characterized in that: Used to prepare the dual-gate semiconductor device according to any one of claims 1 to 9, comprising: providing a substrate; forming a first semiconductor epitaxial sublayer on one side of the substrate; forming a second gate trench on a side of the first semiconductor epitaxial sublayer away from the substrate, and forming a second gate structure in the second gate trench; forming a second semiconductor epitaxial sublayer on a side of the first semiconductor epitaxial sublayer away from the substrate; the semiconductor epitaxial layer includes the first semiconductor epitaxial sublayer and the second semiconductor epitaxial sublayer; forming a first gate trench on a side of the second semiconductor epitaxial sublayer away from the substrate, and forming a first gate structure in the first gate trench; A first electrode is formed on a side of the semiconductor epitaxial layer away from the substrate, and a second electrode is formed on a side of the substrate away from the semiconductor epitaxial layer; wherein, when the dual-gate semiconductor device is in operation, the first gate structure and the second gate structure synchronously input gate voltages.

11. The method for preparing a dual-gate semiconductor device according to claim 10, characterized in that: After forming a second semiconductor epitaxial sublayer on a side of the first semiconductor epitaxial sublayer away from the substrate, the method further includes: Based on the patterned mask, ion implantation is performed in the first semiconductor epitaxial sublayer and the second semiconductor epitaxial sublayer to form a drift region, a body region, and a contact region contacting the second electrode in the semiconductor epitaxial layer, which are sequentially away from the substrate; Wherein, the contact region includes a first doping type contact region and a second doping type contact region; the first doping type contact region is located between the first gate trench and the second doping type contact region; the second gate structure extends from the body region along a direction perpendicular to the substrate to the drift region; the first gate structure extends from the surface of the contact region away from the substrate side, along a direction perpendicular to the substrate to the body region or the drift region.

12. The method for preparing a dual-gate semiconductor device according to claim 10, characterized in that: The second gate structure includes a second polysilicon gate and a second gate insulating layer wrapping the second polysilicon gate; the second gate structure is formed in the second gate trench, including: forming a first insulating sublayer on the wall of the second gate trench and on the surface of the first semiconductor epitaxial sublayer away from the substrate; Filling the second gate trench with polysilicon material, and etching back the polysilicon material until the surface of the polysilicon material away from the substrate is lower than the surface of the first semiconductor epitaxial sublayer away from the substrate, so as to form the second polysilicon gate; forming a second insulating sublayer on a side of the second polysilicon gate away from the substrate; The second insulating sublayer and the first insulating sublayer are sequentially ground until the surface of the first semiconductor epitaxial sublayer away from the substrate is exposed; wherein the ground second insulating sublayer does not expose the surface of the second polysilicon gate away from the substrate; the first insulating sublayer located on the wall of the second gate trench and the second insulating sublayer located on the top of the second polysilicon gate are used to constitute the second gate insulating layer.

13. The method for preparing a dual-gate semiconductor device according to claim 10, characterized in that: After forming a second gate trench on a side of the first semiconductor epitaxial sublayer away from the substrate, the method further includes: forming a first sacrificial oxide layer on the wall of the second gate trench, and removing the first sacrificial oxide layer; And / or, after forming a first gate trench on a side of the second semiconductor epitaxial sublayer away from the substrate, the method further includes: forming a carbon film on the groove wall of the first gate groove, passivating the groove wall with argon gas and performing high-temperature annealing treatment, and then removing the carbon film; A second sacrificial oxide layer is formed on the wall of the first gate trench, and the second sacrificial oxide layer is removed.

14. A power module, characterized in that: It comprises a substrate and at least one dual-gate semiconductor device according to any one of claims 1 to 9, wherein the substrate is used for supporting the dual-gate semiconductor device.

15. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one dual-gate semiconductor device according to any one of claims 1 to 9, wherein the dual-gate semiconductor device is electrically connected to the circuit board.

16. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 15, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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