N-of-m arbitration method and circuit

Abstract

The application discloses an N-to-M arbitration method, which belongs to chip design, network on chip, system on chip and computer bus structure. The method can be used for arbitrating a plurality of result arbitrators in a plurality of request ports in one arbitration cycle. Through the statistical effective request code arbitration mode, the arbitration cycle is shorter, the arbitration frequency and the arbitration efficiency are improved, and thus the bus bandwidth and the utilization rate of bus resources are improved. The high-speed circuit is easy to realize, and is widely used in bus arbitration in the chip. The effective arbitration rate can reach 100%, and the advantage of the method is very obvious when the number of request ports N and selected results M is large.

Description

Technical Field

[0001] This invention relates to the fields of chip design, on-chip networks, on-chip systems, and computer architecture, particularly for use in shared-resource parallel computing or multi-processor systems. This method can maximize arbitration efficiency and shared resource utilization. Background Technology

[0002] Bus resources for data transmission have always been a bottleneck in the bus systems of network chips and large-scale chips (such as GPUs, TPUs, and APUs). These chips handle massive amounts of data transmission, involve numerous data routing between modules, and represent the most frequent data exchange paths. Data bandwidth is typically increased by adding physical lines and raising circuit frequencies, which necessitates efficient arbitration and fast arbitration circuits to ensure fair and efficient resource sharing among all requesting ports. Therefore, the arbitration algorithm and arbitration circuit design can become a system bottleneck, significantly impacting system performance.

[0003] Common arbitration algorithms include the RR (Round-Robin) algorithm and the FP (Fixed Priority) algorithm.

[0004] In chip design, the required number of bus resources is often determined based on the bus bandwidth of multiple requesting endpoints. The model can be abstracted as follows: there are N request ports and M response resources, and each arbitration cycle needs to arbitrate at most M results across the N request ports, where N > M. The N requesting endpoints and the M response endpoints are also independent and indistinguishable.

[0005] Current implementation methods include two approaches. One is based on the RR or FP algorithm, which selects the result through M rounds of iterative arbitration. This sequential iterative arbitration method makes the arbitration circuit very slow, especially as M increases, the iteration calculation time also increases, which severely affects the bus frequency and limits bandwidth. Another approach is hierarchical bus arbitration technology, which groups the requesting ports N into smaller groups, and so on, dividing the entire arbitration into a multi-level tree-like arbitration structure. This method allows each lower-level group to arbitrate in parallel and independently, reduces the number of core units, and the time taken for a complete arbitration is much shorter than that of sequential iterative arbitration, which can effectively improve the frequency. However, the drawback is that the distribution of requests from the N requesting ports is random and uneven, affecting arbitration efficiency and limiting bandwidth. Summary of the Invention

[0006] In view of the above problems, this application designs a request index encoding arbitration algorithm, which solves the problem of uneven distribution of general segmented requests and meets the maximum arbitration efficiency. Because it only requires a counter, comparator and shift register, it greatly shortens the arbitration cycle and increases the circuit frequency.

[0007] Technical solution:

[0008] This invention first discloses an N-to-M arbitration method, which arbitrates M results from N request ports, where N is a positive integer and M is a positive integer less than N. It includes the following steps:

[0009] S1. Number the N request ports, and assign a priority [R] to each request port R;

[0010] S2. Each request to port R is independent and random, denoted by request_valid[R].

[0011] S3. Calculate the valid request code SI[r] for each request port R;

[0012] S4. Select the winning request port: Determine the valid request code SI[r] of each request port R. The index code port with a value less than or equal to M and non-zero is the selected winning request port.

[0013] S5. Update the priority of each request port for the next arbitration cycle;

[0014] S6. Repeat steps S2-S5 to proceed with the arbitration for the next arbitration cycle.

[0015] Preferably, in S1, the initial port_id_0 has the highest priority of N-1, and the priority of subsequent request ports decreases sequentially.

[0016] Preferably, in S1, the priority of each request port is determined by polling the priority according to the RoundRobin method.

[0017] Preferably, in S1, a priority orchestration method is used to calculate the priority of each request port.

[0018] Preferably, in S3, the effective request code for each request port is calculated starting from the highest priority request port.

[0019] Preferably, in S3, the calculation method for the valid request code of any port R is as follows:

[0020] For all ports whose weight priority is greater than or equal to the weight priority of this port, calculate the sum of the number of valid requests for each of the above ports, and use it as the valid request index code SI[r] for port R.

[0021] If port R itself does not have request_valid[R], then the valid request index code SI[r] for port R is 0.

[0022] Preferably, in S5, the next request port of the lowest priority request port in the current arbitration selection result is the highest priority for the next arbitration cycle, and the priorities of other request ports decrease sequentially.

[0023] Preferably, in S4, after the winning request port is selected, the M winning request ports are allocated to the M index numbers according to the mapping function F(m).

[0024] This invention also discloses an N-to-M arbitration circuit, which arbitrates M results from N request ports, where N is a positive integer and M is a positive integer less than N. Each request port is assigned a unique weight priority. Each request port is equipped with a statistical adder. The weight priority of each port is updated once in each arbitration cycle. Each request port sends a valid request to the statistical adder below its own port, and so on. Each statistical adder outputs a valid index code SI[r] of the statistical result and sends it to the corresponding Compare module to compare with the selected target value M. The one less than SI[r] <= M is the winner.

[0025] Preferably, a circular shift register is configured to update the weight priority of each port once per arbitration cycle.

[0026] This invention also discloses another N-to-M arbitration circuit, which arbitrates M results from N request ports, where N is a positive integer and M is a positive integer less than N. Each request port is assigned a unique weight priority. Each request port is equipped with a statistical adder. The weight priority of each port is updated once in each arbitration cycle. The valid index code SI[r-1] of the request port with the higher weight priority is sent to the statistical adder corresponding to the next weight priority request port SI[r], and is statistically summed with the valid request number of the request port corresponding to the statistical adder to obtain the valid index SI[r] of the request port. Each statistical adder outputs the valid index code SI[r] of the statistical result and sends it to the corresponding comparator Compare module to compare with the selected target value M. The one less than SI[r] <= M is the winner.

[0027] Preferably, a circular shift register is configured to update the weight priority of each port once per arbitration cycle.

[0028] This invention discloses a third type of N-to-M arbitration circuit, which arbitrates M results from N request ports, where N is a positive integer and M is a positive integer less than N. Each request port has a priority weight update module priorit_nxt, which is used to update the priority weight value Priority[r] of each port. In the Compare module, by comparing the priority weight value Priority[r] of this port with the priority weight value Priority[N] of each other port, each port outputs a set of Mark_r_[N], and sends the grouped vector values ​​to the weight counter Counter module of the corresponding S_* of each port. The weight counter of each port counts its own Mark_*[r] to obtain the effective request statistical code S_* of this port, and sends it to the corresponding Compare module, and compares it with the selected target value M. The one less than SI[r]<=M is ​​the winner.

[0029] Beneficial effects of the present invention

[0030] This application proposes an N-to-M arbitration method, an arbitrator capable of arbitrating multiple results from multiple request ports within a single arbitration cycle. By statistically encoding valid requests, the arbitration cycle is shortened, increasing arbitration frequency and efficiency, thereby improving bus bandwidth and bus resource utilization. It is easy to implement in high-speed circuits and has been widely used for bus arbitration on our chips, achieving an effective arbitration rate of 100%. The advantages of this method are particularly evident when the number of request ports N and the number of selected results M are large. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of an N-choose-M arbitrator.

[0032] Figure 2 A diagram illustrating the calculation of valid identifiers for 8 request ports.

[0033] Figure 3 The diagram for the 8-port funnel shift arbitration circuit at time T.

[0034] Figure 4 The arbitration circuit diagram for the 8 request ports' funnel shift is shown at time T+1.

[0035] Figure 5 A recursive statistical method circuit for arbitration of 8 request ports via the funnel shift.

[0036] Figure 6 A circuit diagram for indiscriminate arbitration of 8 request ports. Detailed Implementation

[0037] The present invention will be further described below with reference to embodiments, but the scope of protection of the present invention is not limited thereto:

[0038] This application discloses an N-to-M arbitration method and its circuit implementation, such as Figure 1 As shown, M results are arbitrated from N request ports, where N is a positive integer and M is a positive integer less than N. For ease of description, let's assume N = 8 and M = 4 as an example. Any one of the N request ports is called R (0 ≤ R). <N)。

[0039] The specific algorithm is described below:

[0040] S1. Number the N request ports sequentially: port_id_0 == 0, port_id_1 == 1, ..., port_id_N_1 == N-1; and each request port R has a priority [R]. Initially, port_id_0 has the highest priority (N-1), and the priority of each port decreases sequentially thereafter. Figure 2 The top part is shown. In other embodiments, the priority of each request port can be numbered according to the position of the request port, or the priority can be calculated by polling the priority using the RoundRobin method, or other priority arrangement methods, as long as fairness can be guaranteed. This patent uses the RoundRobin priority algorithm as an example for illustration.

[0041] S2. Each request to port R is independent and random, denoted by request_valid[R].

[0042] S3. Starting with the highest priority request port, calculate the valid request code for each request port. The calculation method is as follows: for each request port R, count the number of all valid requests with a priority greater than or equal to that request port, and use this as the valid request index code SI[r]. If there are no valid requests for a request port, the valid request index code for that request port is invalid and the code is 0. Figure 2 As shown, the effective index codes of the ports are SI[0]==1, SI[1]==2, SI[2]==0, SI[3]==3, SI[4]==4, SI[5]==0, SI[6]==5, SI[7]==0.

[0043] S4. Determine the valid request code SI[r] for each request port. The index code port that is less than or equal to M and is not 0 is the selected winning request port. Among them, the four ports SI[0]=1, SI[1]=2, SI[3]=3, and SI[4]=4 are selected winning request ports. It should be noted that if there is a mapping relationship between the winning request port and the index number M, it is only necessary to determine that S[r]==F(M[m]). Figure 3-5The selection mapping is completed based on the output of the statistical adder and the corresponding M numbered relationships. The mapping relationship F is not constrained in this patent. That is, the M winners are to be assigned to M seats (or ports, or other allocation objects, numbered A, B, C, D…). In a preferred embodiment, the allocation is performed using the mapping function F(m). In other embodiments, the first winner can be assigned to A, the second winner to B, and so on, in a sequential or other allocation manner.

[0044] S5. Update the priority of each request port in the next arbitration cycle. The next request port after the lowest priority request port in the current arbitration round will be the highest priority in the next arbitration cycle. Since the lowest priority port in this arbitration round was 4, port 5 will be the highest priority in the next round, and the priorities of other request ports will decrease sequentially. For example... Figure 2 As shown, in the next arbitration interim, the updated weight priority is denoted as Priority_nxt.

[0045] S6. Repeat steps S2-S5 to proceed with the arbitration for the next arbitration cycle.

[0046] Arbitrator circuit implementation:

[0047] This patent implements the above arbitration algorithm in two ways: one is a fixed priority implementation using funnel shift, and the other is a non-discriminatory port implementation. These are described below.

[0048] The first method for implementing fixed priority in funnel shift is as follows: Figure 3 As shown, each weighted port corresponds to a valid request statistics adder. The highest priority is Count_1_1, which only counts whether there are requests for the highest priority port; Count_2_1 is next, which counts the valid requests for the highest and second-highest priority ports; and so on for each port until Count_N_1, which counts the valid requests for all ports. Each weighted port sends its own valid request Mark[r] to the weighted ports with lower priority than itself for statistical aggregation, and adds them to obtain the valid index code SI[r] for each weighted port.

[0049] This implementation method, because each statistical unit is distinguished according to priority, can be followed... Figure 3 The funnelshift circuit in the diagram shifts the request port, moving the highest priority port to the rightmost position in the diagram. The number of bits shifted is based on the position number of the last winning request port in the previous arbitration cycle, such as... Figure 3 The last winning position is Count_5_1, so it shifts 5 positions in the next arbitration cycle. In the T+1 arbitration cycle, the request port with port_id == 5 is moved to the highest priority position. Figure 4As shown.

[0050] Because valid requests to high-priority ports are counted on low-priority ports, there are two possible implementation methods:

[0051] One is Figure 3-4 Parallel statistics at each port in the circuit have the advantages of short circuit paths, high frequency, and suitability for high-speed circuits, but the disadvantage of large circuit area. Using methods such as... Figure 3-4 The circular shift register implementation shown ensures that the highest priority port always corresponds to the rightmost Count_1_1, the next highest priority port corresponds to Count_2_1, and so on until the lowest priority port. Each requesting port sends a valid request to a statistical adder of lower priority than its own port, such as... Figure 3-4 The rightmost, highest-priority (Priority=3'b111) is sent to all statistical adders to its left with lower priorities, and so on. Each statistical adder outputs the valid index code SI[r] of the statistical result and sends it to the corresponding Compare module. This code is compared with the selected target value M; the value less than SI[r] <= M is the winning selection. Figure 3-4 The output `winner_valid[r]` can be used as the grant signal for each corresponding port. The priority of each port is updated in each arbitration cycle and shifted to the corresponding statistical adder via a shift register, such as... Figure 3 The diagram shown is the arbitration port mapping at time T. Figure 4 This is the arbitration port mapping diagram at time T+1.

[0052] Another one is like Figure 5 The recursive addition statistics shown, where the statistical result SI[r+1] of the low-priority port is based on SI[r], has the advantage of small circuit area, but the circuit path is relatively long and not suitable for high-speed circuit implementation. Using... Figure 5 The circular shift register implementation ensures that the highest priority port always corresponds to the rightmost Count_1_1, the next highest priority port corresponds to Count_2_1, and so on until the lowest priority port. The valid index code SI[r-1] of the request port with the highest priority is fed into the statistical adder corresponding to the next highest priority request port SI[r], and summed with the valid request count of the request port corresponding to that statistical adder to obtain the valid index SI[r] of that request port. Figure 5The rightmost priority unit, Priority=3'b111, sends the calculated SI_0 to the leftmost unit SI_1=SI_0+V[1], which is lower in priority. SI_1 sends to SI_2, SI_2=SI_1+V[2], and so on. Each statistical adder outputs the valid index code SI[r] of the statistical result and sends it to the corresponding comparator Compare module. It compares the result with the selected target value M. The value less than SI[r]<=M is ​​the winner. Figure 5 The output `winner_valid[r]` can be used as the grant signal for each corresponding port.

[0053] In specific embodiments, these two statistical implementation methods can be selected according to the actual power design requirements.

[0054] The second method for implementing indiscriminate ports is illustrated in the circuit diagram below. Figure 6 As shown, each request port has a priority weight update module priorit_nxt, which updates the priority weight value Priority[r] of each port based on the last winning port max_priority_request_id of the previous arbitration cycle. In the Compare module, by comparing the priority weight value Priority[r] of this port with the priority weight value Priority[N] of each other port, each port outputs a set of Mark_r_[N], and sends the grouped vector values ​​to the weight counter Counter module of S_* corresponding to each port, such as... Figure 6 As shown, each port sends the Mark_*[0] component to S_0:Counter, and similarly, the Mark_*[1] component to S_1:Counter. Each port's weight counter calculates its own Mark_*[r] to obtain the valid request statistics code S_* for that port, and sends it to the corresponding Compare module. It compares this code with the selected target value M; the value less than SI[r] <= M is the winning candidate. Figure 6 The output grant_valid[r] can be used as the grant signal for each corresponding port.

[0055] Each request port R has N valid request flag bits Mark_R[N], which indicate whether the request port is valid for each request port encoding statistics and are used to calculate the valid request code of the request port.

[0056] Mark_R[n]=((priority[n]≤priority[R])&&request_valid[R]).

[0057] Each request port R has a valid request counter SI, which calculates the valid request statistics code for this request port.

[0058]

[0059] The first implementation method uses different circuits depending on the priority number, resulting in a simple circuit. The second implementation method uses identical circuits for each port, requiring only replication based on the number of ports. The choice can be made based on time constraints. This patent focuses on the arbitration method, but other implementation methods using this arbitration algorithm are also within the scope of this patent protection.

[0060] Using the arbitration method or circuit provided in this application, the arbitration efficiency of each round can reach 100%; the priority of the polling ensures the fairness of the arbitration; different methods can be selected to calculate the effective index code SI[r] according to the circuit area and timing requirements; it is simple and efficient compared with the traditional iterative arbitration method.

[0061] The specific embodiments described herein are merely illustrative of the spirit of the invention. Those skilled in the art to which this invention pertains may make various modifications or additions to the described specific embodiments or use similar methods to substitute them, without departing from the spirit of the invention or exceeding the scope defined by the appended claims.

Claims

1. An N-to-M arbitration method, arbitrating M results from N request ports, where N is a positive integer and M is a positive integer less than N, characterized in that... It includes the following steps: S1. Number the N request ports, and assign a priority [R] to each request port R; S2. Requests for each request port R are independent and random. Count the valid requests for each request port R. S3. Starting with the highest priority request port, calculate the effective request code SI[r] for each request port R; In S3, the calculation method for the valid request code of any port R is as follows: For all ports whose weight priority is greater than or equal to the weight priority of this port, calculate the sum of the number of valid requests for each of the above ports, and use it as the valid request index code SI[r] for port R. If port R itself has no valid requests, then the valid request index code SI[r] for port R is 0; S4. Select the winning request port: Determine the valid request code SI[r] of each request port R. The index code port with a value less than or equal to M and non-zero is the selected winning request port. In S4, after the winning request port is selected, the M winning request ports are assigned to the M index numbers according to the mapping function F(m); S5. Update the priority of each request port for the next arbitration cycle; S6. Repeat steps S2-S5 to proceed with the arbitration for the next arbitration cycle.

2. The method according to claim 1, characterized in that... In S1, the initial port_id_0 has the highest priority of N-1, and the priority of subsequent request ports decreases sequentially.

3. The method according to claim 1, characterized in that... In S1, the priority of each request port is determined by polling the priority according to the RoundRobin method.

4. The method according to claim 1, characterized in that... In S1, a priority orchestration method is used to calculate the priority of each request port.

5. The method according to claim 1, characterized in that... In S5, the next request port after the lowest priority request port in the current arbitration selection result is the highest priority for the next arbitration cycle, and the priorities of other request ports decrease sequentially.

6. An N-to-M arbitration circuit, arbitrating M results from N request ports, where N is a positive integer and M is a positive integer less than N, characterized in that: Each request port is assigned a unique weight priority. Each request port is assigned a statistical adder; the weight priority of each port is updated once per arbitration cycle; starting with the highest priority request port, each request port sends valid requests to statistical adders with lower priority than itself, and so on; each statistical adder outputs the valid index code SI[r] of the statistical result and sends it to the corresponding Compare module to compare with the selected target value M. The one less than SI[r] <= M is the winner. After the winning request port is selected, the M winning request ports are assigned to index numbers M according to the mapping function F(m); The calculation method for the valid request code of any port R is as follows: For all ports whose weight priority is greater than or equal to the weight priority of this port, calculate the sum of the number of valid requests for each of the above ports, and use it as the valid request index code SI[r] for port R. If port R itself has no valid requests, then the valid request index code SI[r] for port R is 0.

7. The circuit according to claim 6, characterized in that... Configure a circular shift register to update the weight priority of each port once per arbitration cycle.

8. An N-to-M arbitration circuit, arbitrating M results from N request ports, where N is a positive integer and M is a positive integer less than N, characterized in that: Each request port is assigned a unique weight priority. Each request port is assigned a statistical adder; the weight priority of each port is updated once per arbitration cycle; starting with the highest priority request port, the valid index code SI[r-1] of the request port with the highest weight priority is sent to the statistical adder corresponding to the next weight priority request port SI[r], and is summed with the valid request count of the request port corresponding to that statistical adder to obtain the valid index SI[r] of that request port. If port R itself has no valid requests, then the valid request index code SI[r] of port R is 0; each statistical adder outputs the statistical result valid index code SI[r] and sends it to the corresponding Compare module to be compared with the selected target value M. The one less than SI[r] <= M is the winner. After the winning request port is selected, the M winning request ports are assigned to the M index numbers according to the mapping function F(m).

9. The circuit according to claim 8, characterized in that... Configure a circular shift register to update the weight priority of each port once per arbitration cycle.

10. An N-to-M arbitration circuit, arbitrating M results from N request ports, where N is a positive integer and M is a positive integer less than N, characterized in that: Each request port has a priority weight update module, priorit_nxt, used to update the priority weight value of each port, Priority[r]. In the Compare module, by comparing the current port's Priority[r] with the priority weight values ​​of every other port, Priority[N] is used. Each port outputs a set of Mark_r_[N], and these grouped vector values ​​are sent to the corresponding S_ of each port. The weight counter module; each port's weight counter counts its own Mark_ [r] This retrieves the valid request statistics code S_ for this port. The value is sent to the corresponding Compare module and compared with the selected target value M. The value less than SI[r] <= M is the winner. After the winning request port is selected, the M winning request ports are assigned to the M index numbers according to the mapping function F(m). The calculation method for the valid request code of any port R is as follows: For all ports whose weight priority is greater than or equal to the weight priority of this port, calculate the sum of the number of valid requests for each of the above ports, and use it as the valid request index code SI[r] for port R. If port R itself has no valid requests, then the valid request index code SI[r] for port R is 0.

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