Display device

Abstract

Embodiments of the present application provide a display device, comprising a display panel, a plurality of gate lines, a plurality of data lines and a plurality of sub-pixel circuits disposed on the display panel, each of the sub-pixel circuits comprising a pixel driving circuit and a light emitting element, in the pixel driving circuit, a light emitting threshold compensation circuit stores a first threshold voltage of a driving transistor in a compensation stage of each display period, after the compensation stage, driving data is obtained, the driving data is compensated by using the first threshold voltage, so that the light emitting element is not affected by drift of the first threshold voltage in a light emitting process, a driving signal generated according to the driving data compensated by the first threshold voltage controls the light emitting element to emit light, and the light emitting intensity of the light emitting element is only affected by the driving data in the case that the light emitting duration is consistent, thereby ensuring uniformity of the light emitting element in a display process.

Description

Technical Field

[0001] Embodiments of this application relate to the field of display technology, and more particularly to a display device. Background Technology

[0002] In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer lifespan, the application of micro-LEDs in displays has developed rapidly and has become a research hotspot in display devices.

[0003] The pixel driving circuit of a micro LED can drive the micro LED to emit light through pulse width modulation (PWM) + pulse amplitude modulation (PAM). That is, the pixel driving circuit obtains the PWM signal, determines the time when the pixel driving circuit generates the driving signal based on the PWM signal, and determines the light emission time of the micro transistor in each frame display cycle. Then, it determines the current value in the driving signal based on the PAM signal, and determines the light intensity of the micro transistor during the light emission process, thereby determining the brightness of the micro LED in each frame display cycle.

[0004] However, the driving transistors that generate driving signals in the pixel driving circuit are affected by the uniformity of the manufacturing process. During use, the threshold voltage of the transistors will drift, which will cause the current value of the driving signal generated by the pixel driving circuit to change under the same PAM signal. This will eventually cause uneven brightness of the micro LED display panel, resulting in poor display and affecting image quality. Summary of the Invention

[0005] This application provides a display device to solve the technical problem of poor light emission uniformity of micro LEDs driven by PWM and PAM.

[0006] In a first aspect, embodiments of this application provide a display device, including:

[0007] The display panel is provided with multiple gate lines, multiple data lines and multiple sub-pixel circuits;

[0008] Each of the sub-pixel circuits includes a pixel driving circuit and a light-emitting element;

[0009] The pixel driving circuit includes a light emission threshold compensation circuit, and the light emission threshold compensation circuit includes a driving transistor.

[0010] The light emission threshold compensation circuit is electrically connected to the data line and is configured to store the first threshold voltage of the driving transistor during the compensation phase of each display cycle, acquire driving data after the compensation phase, compensate the driving data using the first threshold voltage, and generate a driving signal.

[0011] The light-emitting element and the light-emitting threshold compensation circuit are electrically connected and configured to emit light according to the driving signal.

[0012] In the above technical solution, a pixel driving circuit is provided, including a light emission threshold compensation circuit. During the compensation phase of each display cycle, the light emission threshold compensation circuit stores the first threshold voltage of the driving transistor. After the compensation phase, it acquires driving data and uses the first threshold voltage to compensate the driving data so that the light emission element is not affected by the drift of the first threshold voltage during the light emission process. The driving signal generated according to the driving data compensated by the first threshold voltage controls the light emission element to emit light. The light emission intensity of the light emission element is only affected by the driving data when the light emission duration is consistent, thereby ensuring the uniformity of the light emission element during the display process.

[0013] In one feasible implementation, a power line is also provided on the display panel, and the light emission threshold compensation circuit includes a storage circuit and a data writing circuit.

[0014] The first end of the data writing circuit is electrically connected to the power line, and its second end is electrically connected to the second end of the storage circuit. It is configured such that during the compensation phase, its first end obtains a first power signal from the power line and outputs a first power signal after first threshold voltage compensation from its second end.

[0015] The first end of the storage circuit is electrically connected to the power line and is configured such that, during the compensation phase, the first end obtains the first power signal from the power line, and determines and stores the first threshold voltage based on the first power signal and the first power signal after compensation for the first threshold voltage.

[0016] In one feasible implementation, the third terminal of the storage circuit and the third terminal of the data writing circuit are electrically connected and configured to acquire driving data from the third terminal after the compensation phase and output the driving data after the first threshold voltage compensation from the second terminal.

[0017] The data writing circuit is configured to generate a drive signal based on the drive data after the first threshold voltage compensation when its second terminal only acquires the drive data after the first threshold voltage compensation, and to stop generating the drive signal based on the shutdown control signal when its second terminal acquires the shutdown control signal.

[0018] In the above technical solution, within the light emission threshold compensation circuit, the data writing circuit generates a first power signal after first threshold voltage compensation during the compensation phase of each display cycle. The storage circuit obtains the first power signal after first threshold voltage compensation from the data writing circuit and also obtains the first power signal from the power line. It calculates and stores the first threshold voltage by the difference. When the storage circuit obtains driving data, it uses the first threshold voltage to compensate the driving data and generates driving data after first threshold voltage compensation. This allows the data writing circuit to cancel the first threshold voltage when generating a driving signal based on the driving data after first threshold voltage compensation, so that the current value of the driving signal is no longer affected by the threshold voltage, thereby ensuring the uniformity of the light emission element during the display process.

[0019] In one feasible implementation, a display cycle sequentially includes a reset phase, a compensation phase, a data writing phase, and a display phase.

[0020] During the reset phase, the first scan signal and the second power signal are at a first level, the second scan signal, the third scan signal, and the light emission control signal are at a second level, and the light emission threshold compensation circuit does not acquire the shutdown control signal;

[0021] The reset transistor is turned on according to the first scan signal, and transmits the second power supply signal obtained by its first terminal to the second terminal of the second capacitor and the control terminal of the driving transistor.

[0022] The second capacitor stores the second power signal;

[0023] The driving transistor is turned on according to the second power supply signal.

[0024] In one feasible implementation, during the reset phase, the third power supply signal is adjusted from the first level to the second level;

[0025] The second transistor is turned on according to the first scan signal, and transmits the second power supply signal obtained at its first terminal to the first terminal of the third capacitor;

[0026] The third capacitor adjusts the potential value of its first terminal according to the second power signal, and adjusts the potential value of its second terminal according to the third power signal.

[0027] The sixth transistor is turned off according to the light emission control signal and does not output the turn-off control signal.

[0028] In the above technical solution, during the reset phase, the third capacitor obtains the second power supply signal from its first terminal and the third power supply signal that jumps from the first level to the second level from its second terminal. Due to the coupling effect of the third capacitor, the potential value of its first terminal is not affected by the third power supply signal obtained from its second terminal. This helps to ensure that the potential value of its first terminal is only related to the obtained electrical signal and is not related to the third power supply signal during the subsequent compensation phase and data writing phase, thus preventing the jump of the third power supply signal from affecting the operation of each device in the pixel driving circuit.

[0029] The display device provided in this application embodiment includes a display panel with multiple gate lines, multiple data lines, and multiple sub-pixel circuits. Each sub-pixel circuit includes a pixel driving circuit and a light-emitting element. In the pixel driving circuit, the light-emitting threshold compensation circuit stores the first threshold voltage of the driving transistor during the compensation phase of each display cycle. After the compensation phase, it acquires driving data and uses the first threshold voltage to compensate the driving data so that the light-emitting element is not affected by the drift of the first threshold voltage during the light-emitting process. The driving signal generated according to the driving data compensated by the first threshold voltage controls the light-emitting element to emit light. The light-emitting intensity of the light-emitting element is only affected by the driving data when the light-emitting duration is consistent, thereby ensuring the uniformity of the light-emitting element during the display process. Attached Figure Description

[0030] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0031] Figure 1 This is a schematic diagram of the structure of a display device provided in accordance with an exemplary embodiment of this application;

[0032] Figure 2 This is a schematic diagram of the structure of a display device provided in this application according to another exemplary embodiment;

[0033] Figure 3 This is a circuit structure diagram of a conventional pixel driving circuit provided in accordance with an exemplary embodiment of this application;

[0034] Figure 4 This is a schematic diagram of the structure of an N-type pixel driving circuit provided in an exemplary embodiment of this application;

[0035] Figure 5 This is a timing diagram of the driving signals for an N-type pixel driving circuit provided in an exemplary embodiment of this application;

[0036] Figure 6 This is a schematic diagram of the structure of a P-type pixel driving circuit provided in an exemplary embodiment of this application;

[0037] Figure 7 This is a timing diagram of the driving signals for a P-type pixel driving circuit provided in an exemplary embodiment of this application.

[0038] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0039] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0040] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment. It should be further understood that the terms "comprising" or "including" indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups.

[0041] In the description of this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise expressly specified. The terms "or" and "and / or" are interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C." Exceptions to this definition occur only when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some manner.

[0042] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0043] In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer lifespan, the application of micro-LEDs in displays has developed rapidly and has become a research hotspot in display devices.

[0044] A schematic diagram of the display device is shown below. Figure 1 and Figure 2 As shown, the system includes a control circuit 10, a data drive circuit 20, a gate drive circuit 30, a display panel 40, and a power supply circuit 70. The control circuit 10 is electrically connected to the data drive circuit 20 and the gate drive circuit 30, respectively, and the display panel 40 is electrically connected to the data drive circuit 20, the gate drive circuit 30, and the power supply circuit 70.

[0045] The display panel 40 includes a display area AA with multiple pixel circuits 403 and a non-display area NA located outside the display area.

[0046] Within the display area AA, there are power lines 80, multiple gate lines 60, multiple data lines 50, and multiple pixel circuits 403 arranged in an array. Each pixel circuit 403 is located in the area where the gate lines 60 and data lines 50 intersect.

[0047] Each pixel circuit 403 includes a pixel driving circuit 4032 and a light-emitting element 4033. The pixel driving circuit 4032 is electrically connected to the light-emitting element 4033 and is configured to drive the light-emitting element 4033 to emit light.

[0048] The gate drive circuit 30 is electrically connected to the gate line 60 and is configured to obtain clock signals and trigger signals from the control circuit 10, generate a gate drive signal, and transmit the gate drive signal to the corresponding pixel circuit 403 through the gate line 60 to control the conduction of the transistors therein.

[0049] The gate driving circuit 30 can be connected to the display panel 40 via a gate driver integrated circuit (GDIC), or it can be implemented using the gate-in-panel (GIP) method and directly disposed on the display panel 40. In some cases, each GDIC can be integrated and disposed on the display panel 40 using the chip-on-glass (COG) method; in other cases, each GDIC can be implemented using the chip-on-film (COF) method, in which the components are connected to the film of the display panel 40 via a flexible printed circuit (FPC).

[0050] More specifically, depending on the signal type required by the pixel driving circuit 4032, the signals provided by the gate driving circuit 30 include driving signals, scanning signals, and light emission control signals.

[0051] The driving signal is generated by the control circuit 10 or obtained from an external source. This signal is transmitted by the control circuit 10 to the gate driving circuit 30, and then forwarded by the gate driving circuit 30 to the pixel circuit 403 via the first gate line 601. This includes, but is not limited to, start pulse signals, clock signals, and enable signals.

[0052] The scan signal is a successive displacement signal generated by the gate drive circuit 30.

[0053] More specifically, the gate driving circuit 30 includes a scan signal generation circuit 301, which comprises multiple scan signal generation sub-circuits connected in series. Each scan signal generation sub-circuit is configured to obtain a clock signal from the control circuit 10, obtain a scan signal from the output of its preceding scan signal generation sub-circuit, or obtain a trigger signal from the control circuit 10, generate a scan signal corresponding to the current scan signal generation sub-circuit, and transmit the scan signal to the corresponding pixel driving circuit through the corresponding second gate line 602 to control the pixel driving circuit to acquire display data at regular intervals. The phase of the output signal of each scan signal generation sub-circuit lags behind the phase of the input signal.

[0054] The pixel circuit 403, which is electrically connected to the scan signal generation circuit 301, can be electrically connected to the scan signal generation circuit 301 through at least one second gate line 602 to obtain a scan signal of at least one phase.

[0055] The light emission control signal can be a global signal provided by the control circuit 10 or a signal generated by the gate drive circuit 30; no specific limitation is made here.

[0056] When the light emission control signal is a global signal generated by the control circuit 10, the gate driving circuit 30 obtains the global signal from the control circuit 10 and transmits the global signal to the corresponding pixel driving circuit through the first gate line 601.

[0057] When the light emission control signal is generated by the gate driving circuit 30, the light emission control signal generation circuit 302 in the gate driving circuit 30 can generate a successive displacement signal, and transmit the light emission control signal to the corresponding pixel driving circuit through the third gate line 603. The process of generating the light emission control signal by the light emission control signal generation circuit 302 is the same as the process of generating the scan signal by the scan signal generation circuit 301, and will not be described again here.

[0058] The data driving circuit 20 is configured to acquire display data from the control circuit 10 and convert it into an analog data voltage. This analog data voltage is transmitted to the corresponding pixel circuit 403 via the data line 50, so that the light-emitting element in the pixel circuit 403 emits light according to the analog data voltage.

[0059] The data driver circuit 20 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit (SDIC) may include a shift register, latch circuit, digital-to-analog converter, output buffer, etc.

[0060] The power supply circuit 70 is a circuit that provides stable electrical signals and is configured to provide the corresponding power signals to the display panel 40, control circuit 10, data drive circuit 20, and gate drive circuit 30.

[0061] Each pixel circuit 403 includes multiple sub-pixel circuits 4031, integrated within the corresponding pixel area. Each sub-pixel circuit 4031 includes a pixel driving circuit 4032 and a light-emitting element 4033. The pixel driving circuit 4032 generates a corresponding current signal based on the driving data it obtains, so that the light-emitting element 4033 provides the corresponding brightness.

[0062] In one configuration, each pixel circuit 403 includes three sub-pixel circuits 4031, used to display red, blue, and green light respectively; in another configuration, each pixel circuit 403 includes four sub-pixel circuits 4031, used to display red, blue, green, and white light respectively. No specific limitation is made here.

[0063] The color of light emitted by each pixel circuit 403 is determined by the properties of its light-emitting element 4033. The light-emitting element 4033 can be any light-emitting device, including but not limited to OLED and micro LED.

[0064] A micro LED is a miniature light-emitting device manufactured using inorganic semiconductor layers. A micro LED typically includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The structure of such micro LEDs can be diverse, including vertical, horizontal, and flip-chip types, and is not particularly limited to a specific structure.

[0065] When driving the light-emitting element to emit light, the pixel driving circuit 4032 can obtain the gate driving signal through the gate line 60, obtain the driving data through the data line, and obtain the power signal through the power line 80. Based on the level state of the driving signal, it generates a current signal corresponding to the driving data to drive the light-emitting element to emit light.

[0066] Figure 3 This is a circuit structure diagram of a conventional pixel driving circuit provided in an exemplary embodiment of this application, including a thirteenth transistor T13, a fourteenth transistor T14, a fourth capacitor C4, a fifth capacitor C5, a fifteenth transistor T15, and a sixteenth transistor T16.

[0067] The following explanation focuses on the circuit structure and principle of a traditional pixel driving circuit, assuming that all transistors in the traditional pixel driving circuit are N-type transistors.

[0068] The first terminal of the fourteenth transistor T14 is electrically connected to the power supply line 80, and the control terminal is electrically connected to the gate line 60. It is configured to obtain a first power supply signal REF from the power supply line 80 at its first terminal and obtain a light emission control signal EM from the gate line 60 at its control terminal. When the light emission control signal EM is high, it is turned on and outputs the first power supply signal REF from its second terminal.

[0069] The first terminal of the thirteenth transistor T13 and the second terminal of the fourteenth transistor T14 are electrically connected. In one case, its control terminal is electrically connected to the output terminal of the PWM control signal generation circuit, and in another case, it is electrically connected to the gate line 60.

[0070] The thirteenth transistor T13 is configured to obtain the PWM control signal S from its control terminal. PWM And according to the PWM control signal S PWMControl its conduction state, that is, in the PWM control signal S PWM It is turned on when the voltage level is high and turned off when the voltage level is low. The PWM control signal S... PWM During the non-reset phase of each display cycle, a square wave signal is used.

[0071] The first terminal of the fourth capacitor C4 is electrically connected to the control terminal of the thirteenth transistor T13, and is configured such that the voltage level of its first terminal changes with the charging / discharging of the fourth capacitor C4. The waveform corresponding to the voltage level change of the first terminal I of the fourth capacitor C4 in each display cycle is a square wave.

[0072] Therefore, the control terminal voltage of the thirteenth transistor T13 has a relatively gentle edge steepness, which will affect the accuracy of the drive when directly applied to the transistor drive process.

[0073] When the thirteenth transistor T13 is turned on, when its first terminal receives the first power supply signal REF transmitted by the fourteenth transistor T14, it transmits the first power supply signal REF to point C. The steepness of the level transition edge at point C is greater than that at point I.

[0074] The second terminal of the fifteenth transistor T15 is electrically connected to point C, its first terminal is electrically connected to data line 50, and its control terminal is electrically connected to gate line 60. It is configured to obtain a scan signal from gate line 60 and a PAMD signal from data line 50. It is turned on when the scan signal is high, and when it is turned on, it transmits the PAMD signal obtained from its first terminal to point C.

[0075] The first end of the fifth capacitor C5 is electrically connected to point C, and the second end is electrically connected to the power line 80. It is configured to store the electrical signal at point C. That is, after the fifteenth transistor T15 transmits the PAMD signal to point C, the PAMD signal is stored, and the PAMD signal can still be provided to point C after the fifteenth transistor T15 is turned off.

[0076] The control terminal of the sixteenth transistor T16 is electrically connected to point C. Its first terminal is electrically connected to the second terminal of the fifth capacitor C5 and the first terminal of the fourteenth transistor T14. Its second terminal is electrically connected to the first terminal of the light-emitting element LED. It is configured to conduct when the difference between the voltage value of the electrical signal stored in the fifth capacitor C5 and the voltage value of its first terminal is greater than the threshold voltage of the sixteenth transistor T16, thereby generating a drive signal and transmitting the drive signal to the light-emitting element LED to control the LED to emit light.

[0077] When the sixteenth transistor T16 generates a drive signal, the current value of the drive signal is I. T10 =k(V GS -V th ), where V GS =V PAMD-V REF k is the current amplification factor of the transistor, which is determined by the characteristics of the transistor itself.

[0078] However, due to the uniformity of the manufacturing process, the threshold voltage of the sixteenth transistor in the pixel driving circuit that generates the driving signal will drift during use. This will cause the current value of the driving signal generated by the pixel driving circuit to change under the same PAMD signal, ultimately resulting in uneven brightness of the micro LED display panel, poor display, and problems affecting image quality.

[0079] To address the aforementioned problems, this application provides a display device to solve the technical issue of poor light emission uniformity in micro LEDs driven by PWM and PAM. The technical concept of this application is as follows: a display device is provided, including a display panel with multiple gate lines, multiple data lines, and multiple sub-pixel circuits. Each sub-pixel circuit includes a pixel driving circuit and a light-emitting element. In the pixel driving circuit, a light emission threshold compensation circuit stores a first threshold voltage of the driving transistor during the compensation phase of each display cycle. After the compensation phase, driving data is acquired, and the first threshold voltage is used to compensate the driving data, so that the light-emitting element is not affected by the drift of the first threshold voltage during the light emission process. A driving signal generated based on the driving data compensated by the first threshold voltage controls the light-emitting element to emit light. The light emission intensity of the light-emitting element, under the condition of consistent light emission duration, is only affected by the driving data, thereby ensuring the uniformity of the light-emitting element during the display process.

[0080] The pixel driving circuit proposed in this application will be explained in detail below. Figure 4 This is a schematic diagram of a pixel driving circuit provided according to an exemplary embodiment of this application. All transistors in this pixel driving circuit are N-type transistors.

[0081] like Figure 4 As shown, the pixel driving circuit 4032 provided in this application includes an emission threshold compensation circuit 4034.

[0082] The light emission threshold compensation circuit 4034 is electrically connected to the data line 50 and is configured to store the first threshold voltage Vth9 of the driving transistor T9 during the compensation phase of each display cycle, acquire the driving data PAMD after the compensation phase, and use the first threshold voltage Vth9 to compensate the driving data PAMD to generate a driving signal.

[0083] The light-emitting element LED and the light-emitting threshold compensation circuit 4034 are electrically connected and configured to emit light according to a drive signal.

[0084] The light emission threshold compensation circuit 4034 includes a storage circuit 4036, a data writing circuit 4037, a light emission control transistor T11, and a reset transistor T10.

[0085] The first end of the storage circuit 4036 is electrically connected to the power line 80 through point A, the second end is electrically connected to the second end of the data writing circuit 4037 through point B, the third end is electrically connected to the third end of the data writing circuit 4037 through point C, and the fourth end is electrically connected to the power line 80 through point D.

[0086] The storage circuit 4036 is configured to obtain a first power signal REF from the power line 80 at its fourth terminal. During the compensation phase, its first terminal obtains the first power signal REF from the power line 80, and its second terminal obtains the first power signal REF after compensation of the first threshold voltage Vth9 from the data writing circuit 4037. Based on the first power signal REF obtained by its first terminal and the first power signal REF after compensation of the first threshold voltage Vth9 obtained by its second terminal, the first threshold voltage Vth9 is determined and stored.

[0087] The storage circuit 4036 is also configured to, after the compensation phase, acquire drive data PAMD from its third terminal and output the compensated drive data PAMD to the data writing circuit 4037 from its second terminal, using the first threshold voltage Vth9.

[0088] The first terminal of the reset transistor T10 is electrically connected to the power supply line 80, its second terminal is electrically connected to point B, and its control terminal is electrically connected to the gate line 60. It is configured to obtain a second power supply signal VDD from its first terminal and a first scan signal SN-1 from its control terminal, and its conduction state is controlled by the first scan signal SN-1.

[0089] The reset transistor T10 is turned on when the first scan signal SN-1 is high, transmitting the second power supply signal VDD to point B; it is turned off when the first scan signal SN-1 is low, stopping the transmission of the second power supply signal VDD.

[0090] The first terminal of the data writing circuit 4037 is electrically connected to the power line 80 through point D, its input terminal is electrically connected to the data line 50 through point E, and its output terminal is electrically connected to the first terminal of the light-emitting control transistor T11 through point F.

[0091] The data writing circuit 4037 is configured such that, during the compensation phase, its first terminal obtains a first power signal REF from the power line 80, and its second terminal outputs the first power signal REF after compensation to the storage circuit 4036 at the first threshold voltage Vth9.

[0092] The data writing circuit 4037 is also configured to acquire the PAMD signal from its input terminal after the compensation phase and transmit the signal to the storage circuit 4036 through its third terminal. After the storage circuit 4036 compensates the PAMD signal using the first threshold voltage Vth9, it acquires the compensated drive data from its second terminal.

[0093] When its second terminal only acquires the drive data after compensation for the first threshold voltage Vth9, PAMD generates a drive signal based on the drive data after compensation for the first threshold voltage Vth9. When its second terminal acquires the turn-off control signal S... BD At that time, according to the shutdown control signal S BD Stop generating drive signals.

[0094] The control terminal of the light-emitting control transistor T11 is electrically connected to the gate line 60, and its second terminal is electrically connected to the light-emitting element LED. Since the light-emitting control transistor T11 is an N-type transistor, its second terminal is electrically connected to the output terminal of the light-emitting element LED.

[0095] The light-emitting control transistor T11 is configured to receive a light-emitting control signal EM from its control terminal, and its conduction state is controlled by the light-emitting control signal. It conducts when the light-emitting control signal EM is high, and transmits the drive signal to the light-emitting element LED when its first terminal receives a drive signal; it turns off when the light-emitting control signal EM is low, stopping the transmission of electrical signals.

[0096] In the above technical solution, within the light emission threshold compensation circuit, the data writing circuit generates a first power signal after first threshold voltage compensation during the compensation phase of each display cycle. The storage circuit obtains the first power signal after first threshold voltage compensation from the data writing circuit and also obtains the first power signal from the power line. It calculates and stores the first threshold voltage by the difference. When the storage circuit obtains driving data, it uses the first threshold voltage to compensate the driving data and generates driving data after first threshold voltage compensation. This allows the data writing circuit to cancel the first threshold voltage when generating a driving signal based on the driving data after first threshold voltage compensation, so that the current value of the driving signal is no longer affected by the threshold voltage, thereby ensuring the uniformity of the light emission element during the display process.

[0097] The shutdown control signal S obtained at point B BD This is the signal obtained from the outside by the light emission threshold compensation circuit 4034 during the display phase of each display cycle. Within each display cycle, the display phase follows the compensation phase.

[0098] In one embodiment, the shut-off control signal S BD This is the first power supply signal REF.

[0099] In one embodiment, the shut-off control signal S BD The signal is obtained from the gate line 60. This signal is generated by the control circuit 10 and transmitted to the pixel driving circuit 4032 through the gate driving circuit 30.

[0100] In another embodiment, the shut-off control signal S is used. BD It is the signal generated by the shutdown control signal generation circuit 4035 in the pixel driving circuit 4032.

[0101] The input terminal of the shutdown control signal generation circuit 4035 is electrically connected to the power supply line 80, its output terminal is electrically connected to point B via point F, and its control terminal is electrically connected to the gate line 60. It is configured to obtain a third power supply signal SWEEP from the power supply line 80, a scan signal and an illumination control signal EM from the gate line 60, and output a shutdown control signal S during the display phase based on the third power supply signal SWEEP, the scan signal, and the illumination control signal EM. BD This is to control the LED light-emitting element to stop emitting light.

[0102] The circuit structures of the light emission threshold compensation circuit 4034 and the shutdown control signal generation circuit 4035 are explained in detail below.

[0103] In the light emission threshold compensation circuit 4034, the storage circuit 4036 includes a first input transistor T12, a first capacitor C3, and a second capacitor C2.

[0104] The first terminal of the first input transistor T12 serves as the first terminal of the storage circuit 4036. Its second terminal is electrically connected to the second terminal of the first capacitor C1, and its control terminal is electrically connected to the gate line 60. It is configured to obtain a first power signal REF from the power line 80 at its first terminal and a second scan signal SN from its control terminal, and its conduction state is controlled by the second scan signal SN.

[0105] The first input transistor T12 is turned on when the second scan signal SN is high, transmitting the first power supply signal REF acquired at its first terminal to the second terminal of the first capacitor C1; it is turned off when the second scan signal SN is low, stopping the transmission of the first power supply signal REF.

[0106] The first end of the first capacitor C1 serves as the second end of the storage circuit 4036, and its second end serves as the third end of the storage circuit 4036. It is configured to acquire the first power signal REF transmitted by the data writing circuit 4037 after compensation of the first threshold voltage Vth9 when the first power signal REF is acquired at its second end, and to determine and store the first threshold voltage Vth9 based on the voltage difference between its two ends.

[0107] The first capacitor C1 is also configured to, when it obtains drive data PAMD from the third terminal of the data writing circuit 4037 at its second terminal, output drive data PAMD compensated for the first threshold voltage Vth9 from its first terminal based on the drive data PAMD and the first threshold voltage Vth9.

[0108] The second terminal of the second capacitor C2 is electrically connected to the first terminal of the first capacitor C1. Its first terminal serves as the fourth terminal of the storage circuit 4036 and is configured to obtain a stable electrical signal from the power line 80. This electrical signal is the first power signal REF, and the drive data PAMD after compensation of the first threshold voltage Vth9 is determined from its first terminal.

[0109] The second capacitor C2 is also configured to store the electrical signal acquired by the second terminal of the storage circuit 4036.

[0110] Based on the circuit structure composed of the first capacitor C1 and the second capacitor C2, when the electrical signal obtained at the second terminal of the first capacitor C1 is the first power supply signal REF, the potential value at its first terminal is V. REF +Vth9.

[0111] When the electrical signal obtained at the second terminal of the first capacitor C1 is adjusted from the first power supply signal REF to PAMD, the potential of the second terminal of the first capacitor C1 remains consistent with the potential value of the electrical signal obtained according to the charging and discharging operation of its capacitor.

[0112] When the electrical signal is adjusted from the second power supply signal REF to the PAMD signal, the voltage change at its second terminal is ΔV = V. PAMD -V REF Based on the bootstrap effect of the first capacitor C1, the voltage at the first terminal of the first capacitor C1 is adjusted to V. B =V REF +Vth9+ΔV*c1 / (c1+c2)=V REF +Vth9+(V PAMD -V REF )*c1 / (c1+c2), where c1 is the capacitance of the first capacitor C1 and c2 is the capacitance of the second capacitor C2.

[0113] The second capacitor C2 stores the voltage value mentioned above, which is the same as the voltage value at point B.

[0114] The data writing circuit 4037 generates a drive signal based on the voltage value at point B and determines the current value of the drive signal.

[0115] The data writing circuit 4037 includes a compensation transistor T7, a drive transistor T9, and a data writing transistor T8.

[0116] The first terminal of the compensation transistor T7 is electrically connected to the second terminal of the driving transistor T9. Its first terminal is electrically connected to the control terminal of the driving transistor T9, and its control terminal is electrically connected to the gate line 60. It is configured to obtain the second scan signal SN from the gate line 60 and control its conduction state by the second scan signal SN.

[0117] The compensation transistor T7 is turned on when the second scan signal SN is high, shorting the second terminal of the driving transistor T9 to the control terminal; it is turned off when the second scan signal SN is low, disconnecting the second terminal of the driving transistor T9 from the control terminal.

[0118] The first terminal of the driving transistor T9 serves as the first terminal of the data writing circuit 4037, its control terminal serves as the second terminal of the data writing circuit 4037, its second terminal serves as the output terminal of the data writing circuit 4037, and its second terminal is electrically connected to the first terminal of the light-emitting control transistor T11. It is configured to obtain the first power signal REF from the power line 80 at its first terminal, and when its second terminal and the control terminal are shorted, it determines the first power signal REF after compensation of the first threshold voltage Vth9 from its control terminal.

[0119] The driving transistor T9 is also configured such that when it is turned on and its second terminal and control terminal are open-circuited, its control terminal obtains the drive data PAMD compensated for the first threshold voltage Vth9 from the second capacitor C2, with the voltage value being VREF + Vth9 + (V PAMD -V REF The first terminal of the drive signal is obtained from the power supply line 80, and a drive signal is generated based on the first power supply signal REF and the first threshold voltage Vth9, and the drive signal is compensated based on the drive data after the first threshold voltage compensation. The current value of the drive signal is k(Vgs-Vth9)=k(V REF +Vth9+(V PAMD -V REF )*c1 / (c1+c2)-V REF -Vth9)=k((V PAMD -V REF )*c1 / (c1+c2)).

[0120] The driving transistor T9 transmits the driving signal to the light-emitting control transistor T11. When the light-emitting control transistor T11 is turned on, the driving signal is transmitted to the light-emitting element LED. Since the current value of the driving signal generated by the driving transistor T9 is independent of the first threshold voltage Vth9, the uniformity of light emission of the light-emitting element LED is ensured.

[0121] The first terminal of the data writing transistor T8 is electrically connected to the data line 50, and its second terminal serves as the third terminal of the data writing circuit 4037. Its control terminal is electrically connected to the gate line 60 and is configured to obtain drive data PAMD from the data line 50 at its first terminal and obtain the third scan signal SN+1 from the gate line 60 at its control terminal. The third scan signal SN+1 controls its conduction state, and when it is on, it outputs drive data PAMD from its second terminal.

[0122] The data writing transistor T8 is configured to turn on when the third scan signal SN+1 is high, and transmit the driving data PAMD acquired by its first terminal to the second terminal of the first capacitor C1; and to turn off when the third scan signal SN+1 is low, stopping the transmission of electrical signals.

[0123] In the above technical solution, based on the circuit structure composed of a driving transistor and a compensation transistor, when the first power signal is acquired, a first power signal after compensation of the first threshold voltage of the driving transistor can be generated. The first terminal of the first capacitor acquires the first power signal after compensation of the first threshold voltage, and its second terminal acquires the first power signal. The first threshold voltage can be determined according to the voltage difference between the signals acquired at the two terminals. When the driving data is acquired at the second terminal of the first capacitor, the driving data can be compensated using the first threshold voltage, so that when the driving transistor generates a driving signal according to the electrical signal obtained from its control terminal, the first threshold voltage can be canceled, so that the driving signal is not affected by the first threshold voltage, thereby increasing the display uniformity of the light-emitting element.

[0124] The shutdown control signal generation circuit 4035 includes a third capacitor C3, a first transistor T1, a third transistor T3, a fifth transistor T5, a second transistor T2, a fourth transistor T4, and a sixth transistor T6.

[0125] The first terminal of the third transistor T3 is electrically connected to the data line 50, its second terminal is electrically connected to the first terminal of the first transistor T1, and its control terminal is electrically connected to the gate line 60. It is configured to obtain the pulse width modulation signal PWMD from the data line 50 at its first terminal and obtain the second scan signal SN from the gate line 60 at its control terminal. The second scan signal SN controls its conduction state. When it is on, it transmits the pulse width modulation signal PAMD to the first transistor T1.

[0126] The third transistor T3 is configured to turn on when the second scan signal SN is high, transmitting the pulse width modulation signal PWMD to the first terminal of the first transistor T1; and to turn off when the second scan signal SN is low, stopping the transmission of electrical signals.

[0127] The first terminal of the fifth transistor T5 is electrically connected to the second terminal of the first transistor T1, and its second terminal is electrically connected to the control terminal of the first transistor T1. Its control terminal is electrically connected to the gate line 60. It is configured to obtain the second scan signal SN from the gate line 60 and control its conduction state by the second scan signal SN.

[0128] The fifth transistor T5 is configured to turn on when the second scan signal SN is high, shorting the second terminal and the control terminal of the first transistor T1; and to turn off when the second scan signal SN is low, disconnecting the control terminal and the second terminal of the first transistor T1.

[0129] The first transistor T1 is configured to acquire the pulse width modulation signal PWMD from its first terminal. When its second terminal and its control terminal are shorted, the pulse width modulation signal PWMD after compensation of the second threshold voltage Vth1 is determined according to the pulse width modulation signal PWMD and its second threshold voltage Vth1.

[0130] The first terminal of the third capacitor C3 is electrically connected to the control terminal of the first transistor T1, and its second terminal is electrically connected to the power supply line 80. It is configured to store the pulse width modulation signal PWMD after compensation of the second threshold voltage Vth1.

[0131] The third capacitor C3 is also configured to obtain a third power supply signal SWEEP from its second terminal and adjust the potential value of its first terminal according to the third power supply signal SWEEP.

[0132] The first transistor T1 is also configured such that when its second terminal and its control terminal are disconnected, its control terminal obtains an electrical signal from the first terminal of the third capacitor C3 and obtains a first power supply signal REF from its first terminal, and controls its conduction state according to the voltage difference between its first terminal and the control terminal and the second threshold voltage Vth1.

[0133] The first transistor T1 turns on when the absolute value of the voltage difference between its first terminal and its control terminal is greater than or equal to the absolute value of the second threshold voltage Vth1, and transmits the first power supply signal REF obtained at its first terminal to the first terminal of the sixth transistor T6; it turns off when the absolute value of the voltage difference between its first terminal and its control terminal is less than the absolute value of the second threshold voltage Vth1.

[0134] The first terminal of the second transistor T2 is electrically connected to the power supply line 80, its second terminal is electrically connected to the first terminal of the third capacitor C3, and its control terminal is electrically connected to the gate line 60. It is configured to obtain a first scan signal SN-1 from its control terminal and a second power supply signal VDD from its first terminal, and its conduction state is controlled by the first scan signal SN-1.

[0135] The second transistor T2 is configured to turn on when the first scan signal SN-1 is high, and transmit the second power supply signal VDD obtained from its first terminal to the first terminal of the third capacitor C3 and the control terminal of the first transistor T1; and turn off when the first scan signal SN-1 is low, stopping the transmission of electrical signals.

[0136] The first terminal of the fourth transistor T4 is electrically connected to the power supply line 80, its second terminal is electrically connected to the first terminal of the first transistor T1, and its control terminal is electrically connected to the gate line 60. It is configured to obtain a first power supply signal REF from its first terminal and a light emission control signal EM from its control terminal, and to control its conduction state by the light emission control signal EM.

[0137] The fourth transistor T4 is configured to turn on when the light emission control signal EM is high, and transmit the first power supply signal REF obtained at its first terminal to the first terminal of the first transistor T1; and to turn off when the light emission control signal EM is low, stopping the transmission of electrical signals.

[0138] The first terminal of the sixth transistor T6 is electrically connected to the second terminal of the first transistor T1. Its second terminal serves as the output terminal of the turn-off control signal generation circuit 4035 and is electrically connected to point F. Its control terminal is electrically connected to the gate line 60 and is configured to obtain the light emission control signal EM from its control terminal, and control its conduction state by the light emission control signal EM.

[0139] The sixth transistor T6 is configured to turn on when the light emission control signal EM is high, and transmit the first power supply signal REF obtained from its first terminal to point F; and to turn off when the light emission control signal EM is low, stopping the transmission of electrical signals.

[0140] When the sixth transistor T6 outputs the first power supply signal REF, it determines the first power supply signal REF as the turn-off control signal S. BD .

[0141] Figure 4 The circuit structure shown is composed of Figure 5 The driving signal timing diagram shown is used for driving.

[0142] The following is about Figure 4 The operation of the circuit structure shown will be explained.

[0143] The circuit operation within one display cycle is explained below. One display cycle T includes the reset phase t1, the compensation phase t2, the data writing phase t3, and the display phase t4 in sequence.

[0144] During the reset phase t1 in the drive signal timing diagram, the first scan signal SN-1 and the second power supply signal VDD are at high level, while the second scan signal SN, the third scan signal SN+1, and the light emission control signal EM are at low level. Therefore, the light emission threshold compensation circuit 4034 does not receive the turn-off control signal S. BD .

[0145] Since the first scan signal SN-1 is high, the reset transistor T10 is turned on, and the second power supply signal VDD obtained from its first terminal is transmitted to point B.

[0146] The second capacitor C2 obtains and stores the second power supply signal VDD from point B.

[0147] Since the light-emitting control signal EM is at a low level, the light-emitting control transistor T11 is turned off and does not transmit electrical signals.

[0148] The LED light-emitting element does not receive an electrical signal and therefore does not emit light.

[0149] When the control signal S is turned off BD When the power supply signal is provided by the shutdown control signal generation circuit 4035, the third power supply signal SWEEP is adjusted from high level to low level during the reset phase t1.

[0150] exist Figure 5 In the driving signal timing diagram shown, the third power supply signal SWEEP is adjusted from high level to low level at the initial moment of the reset phase t1.

[0151] Since the first scan signal SN-1 is at a high level, the second transistor T2 is turned on, and the second power supply signal VDD obtained from its first terminal is transmitted to point G.

[0152] The third capacitor C3 obtains the second power signal VDD from point G, adjusts the potential value of its first terminal according to the second power signal VDD, and adjusts the potential value of its second terminal according to the third power signal SWEEP. Due to the coupling effect of the third capacitor C3, the potential values ​​of its first and second terminals do not affect each other.

[0153] The sixth transistor T6 is turned off according to the light emission control signal EM, and does not output the turn-off control signal S. BD .

[0154] In the above technical solution, during the reset phase, the third capacitor obtains the second power supply signal from its first terminal and the third power supply signal that jumps from the first level to the second level from its second terminal. Due to the coupling effect of the third capacitor, the potential value of its first terminal is not affected by the third power supply signal obtained from its second terminal. This helps to ensure that the potential value of its first terminal is only related to the obtained electrical signal and is not related to the third power supply signal during the subsequent compensation phase and data writing phase, thus preventing the jump of the third power supply signal from affecting the operation of each device in the pixel driving circuit.

[0155] During the compensation phase t2 in the driving signal timing diagram, the second scan signal SN is at a high level, while the first scan signal, the third scan signal, and the light emission control signal are at a low level. Therefore, the light emission threshold compensation circuit 4034 does not receive the turn-off control signal S. BD .

[0156] Since the second scan signal SN is high, the compensation transistor T7 is turned on, shorting the second terminal and the control terminal of the drive transistor T9.

[0157] Since the second terminal and the control terminal of the ninth transistor T9 are shorted, the ninth transistor T9 determines the first power supply signal REF after compensation of the first threshold voltage Vth9 from its control terminal based on the first power supply signal REF obtained from its first terminal and its first threshold voltage Vth9, and synchronizes the electrical signal with the potential value of point B.

[0158] The electrical potential at point B is V. REF +Vth9.

[0159] Since the second scan signal SN is high, the first input transistor T12 is turned on, transmitting the first power supply signal REF acquired at its first terminal to the second terminal of the first capacitor C1. The potential value of the second terminal of the first capacitor C1 is adjusted to V. REF .

[0160] Since the potential value obtained by the first terminal of the first capacitor C1 from point B is V REF +Vth9, the potential value of its second terminal is V REF Then, the voltage difference across the first capacitor C1 is determined to be the first threshold voltage Vth9.

[0161] Since the light-emitting control signal EM is at a low level, the light-emitting control transistor T11 is turned off and does not transmit electrical signals.

[0162] The LED light-emitting element does not receive an electrical signal and therefore does not emit light.

[0163] When the control signal S is turned off BDWhen the power supply signal is provided by the shutdown control signal generation circuit 4035, the third power supply signal SWEEP is at a low level during the reset phase t2.

[0164] Since the second scan signal SN is high, the third transistor T3 is turned on, and the pulse width modulation signal PWMD obtained from its first terminal is transmitted to the first terminal of the first transistor T1.

[0165] Since the second scan signal SN is high, the fifth transistor T5 is turned on, shorting the second terminal of the first transistor T1 and the control terminal.

[0166] Since the second terminal of the first transistor T1 is shorted to the control terminal, it forms a diode structure with the fifth transistor T5. The potential value of its control terminal is the sum of the potential value of its first terminal and its threshold voltage.

[0167] Since the potential value of the electrical signal acquired at the first terminal of the first transistor T1 is V PWMD If its threshold voltage is the second threshold voltage Vth1, then the potential value of its control terminal is V. PWMD +Vth1.

[0168] The first transistor T1 synchronizes the potential value of its control terminal to point G. C3 obtains the potential value from point G, stores it, and adjusts the potential value of its first terminal according to the potential value.

[0169] Since the light emission control signal EM is not yet low, the sixth transistor T6 remains off and does not output the off control signal S. BD .

[0170] During the data writing phase t3 in the drive signal timing diagram, the third scan signal SN+1 is high, while the first scan signal SN-1, the second scan signal SN, and the light emission control signal EM are low. Therefore, the light emission threshold compensation circuit 4034 does not receive the turn-off control signal S. BD .

[0171] Since the second scan signal SN is at a low level, the first input transistor T12 is turned off, stopping the transmission of the first power supply signal REF to the first capacitor C1.

[0172] Since the third scan signal SN+1 is high, the data writing transistor T8 is turned on, and the drive data PAMD obtained from its first terminal is transmitted to the second terminal of the first capacitor C1.

[0173] The voltage change at the second terminal of the first capacitor C1 is ΔV = V PAMD -V REFSince the first terminal of the first capacitor C1 and the second terminal of the second capacitor C2 are electrically connected, and the first terminal of the second transistor C2 receives a stable first power supply signal REF, the potential value of the first terminal of the first capacitor C1 is adjusted based on the bootstrap effect of the first capacitor C1.

[0174] The potential value at the first terminal of the first capacitor C1, i.e., the potential value at point B, is V. B =V REF +Vth9+ΔV*c1 / (c1+c2)=V REF +Vth9+(V PAMD -V REF )*c1 / (c1+c2). Where c1 is the capacitance of the first capacitor C1 and c2 is the capacitance of the second capacitor C2.

[0175] Since the light-emitting control signal EM is at a low level, the light-emitting control transistor T11 is turned off and does not transmit electrical signals.

[0176] The LED light-emitting element does not receive an electrical signal and therefore does not emit light.

[0177] When the control signal S is turned off BD When the power supply signal is provided by the shutdown control signal generation circuit 4035, the third power supply signal SWEEP is at a low level during the time period corresponding to the data writing stage t3.

[0178] Since the second scan signal SN is low, the third transistor T3 is turned off, stopping the transmission of the pulse width modulation signal PWMD to the first transistor T1.

[0179] Since the second scan signal SN is low, the fifth transistor T5 is turned off, and the second terminal and the control terminal of the first transistor T1 are disconnected.

[0180] The first transistor T1 is turned off according to the potential value at point G.

[0181] Since the light emission control signal EM is low, the sixth transistor T6 remains off and does not output the turn-off control signal S. BD .

[0182] During the time period corresponding to stage t4 shown in the driving signal timing diagram, the light emission control signal EM is at a high level, while the first scan signal SN-1, the second scan signal SN, and the third scan signal SN+1 are at a low level.

[0183] The display stage t4 includes the light-emitting stage t41 and the non-light-emitting stage t42.

[0184] The light emission threshold compensation circuit 4034 did not receive the turn-off control signal S during the light emission stage t41. BD During the non-light-emitting phase, t42 acquires the turn-off control signal S.BD .

[0185] During the period corresponding to the light emission stage t41, since the third scan signal SN+1 is at a low level, the data writing transistor T8 is turned off, and the transmission of the PAMD signal stops.

[0186] Since the second scan signal SN is low, the compensation transistor T7 is turned off, and the second terminal and the control terminal of the driving transistor T9 are disconnected.

[0187] Because the shutdown control signal S was not acquired. BD The potential value of the control terminal of the driving transistor T9 is V. REF +Vth9+(V PAMD -V REF The potential value at the first terminal of the )*c1 / (c1+c2) is V. REF When the driving transistor T9 is turned on, the current value of the generated driving signal is k((V) PAMD -V REF )*c1 / (c1+c2)).

[0188] The driving transistor T9 transmits the driving signal to the first terminal of the light-emitting control transistor T11.

[0189] Since the light-emitting control signal EM is at a high level, the light-emitting control transistor T11 is turned on, and the driving signal obtained from its first terminal is transmitted to the light-emitting element LED.

[0190] The light-emitting element LED emits light according to the driving signal, and its light intensity is not affected by the drift of the first threshold voltage Vth9 of the driving transistor T9.

[0191] During the non-light-emitting phase t42, the turn-off control signal S is acquired at point B. BD The potential values ​​at the second terminal of the second capacitor C2 and the first terminal of the first capacitor C1 are both adjusted to the off control signal S. BD The corresponding potential value.

[0192] When the control signal S is turned off BD When the first power supply signal REF is applied, the potential values ​​of the first terminal and the control terminal of the ninth transistor T9 are the same, the ninth transistor T9 is turned off, and the generation of drive signals is stopped.

[0193] The light-emitting control transistor T11 remains in the on state. Since its first terminal no longer receives a drive signal, its second terminal no longer transmits a drive signal to the light-emitting element LED.

[0194] The LED light-emitting element stops emitting light.

[0195] When the control signal S is turned off BDWhen the power supply signal is provided by the shutdown control signal generation circuit 4035, during the time period corresponding to the display stage t4, the third power supply signal SWEEP is a ramp signal that is adjusted from low level to high level.

[0196] During the period corresponding to the light-emitting stage t41, the third power supply signal SWEEP is adjusted from a low level to a third level, which is greater than the low level and less than the high level.

[0197] The potential value at the first terminal of the third capacitor C3 increases as the third power supply signal SWEEP acquired at its second terminal increases.

[0198] The third level is the level that controls the first transistor T1 to turn on.

[0199] Therefore, during the light-emitting stage t41, the first transistor T1 is not turned on.

[0200] Since the light emission control signal EM is at a high level, the fourth transistor T4 is turned on, and the first power supply signal REF obtained from its first terminal is transmitted to the first terminal of the first transistor T1.

[0201] Since the first transistor T1 is not conducting, the electrical signal acquired at its first terminal cannot be transmitted to the sixth transistor T6.

[0202] Since the light emission control signal EM is high, the sixth transistor T6 is turned on. Because its first terminal does not receive an electrical signal, it still does not output the turn-off control signal S. BD .

[0203] During the non-light-emitting period t42, the third power supply signal SWEEP is adjusted from the third level to the high level.

[0204] Since the voltage at the first terminal of the third capacitor C3 controls the first transistor T1 to turn on when the third power supply signal SWEEP is at the third level, the first transistor T1 does not turn on during the non-light-emitting stage t42.

[0205] As the fourth transistor T4 is turned on, it transmits the first power signal REF to the first transistor T1.

[0206] As the first transistor T1 is turned on, it transmits the first power supply signal REF to the sixth transistor T6.

[0207] Because the sixth transistor T6 is turned on, it outputs the first power supply signal REF to point F, so that point B, which is electrically connected to point F, receives the turn-off control signal S. BD .

[0208] During the above driving process, when the pixel driving circuit 4032 includes a shutdown control signal generation circuit 4035 and the data lines of the pixel driving circuit 4032 are multiplexed, the data driving circuit 201 outputs a pulse width modulation signal PWMD during the time period corresponding to the compensation stage t2 and outputs driving data PAMD during the time period corresponding to the data writing stage t3.

[0209] The reuse of data lines reduces the number of wires on the pixel circuit, which helps to improve the flexibility of circuit layout.

[0210] Figure 6 This is a schematic diagram of a pixel driving circuit provided according to another exemplary embodiment of this application. All transistors in this pixel driving circuit are P-type transistors.

[0211] like Figure 6 As shown, the pixel driving circuit 4032 provided in this application includes an emission threshold compensation circuit 4034.

[0212] Since all transistors in the pixel driving circuit are P-type transistors, therefore, compared to Figure 4 The circuit structure shown is Figure 6 The circuit structure shown has been adjusted as follows:

[0213] In the light emission threshold compensation circuit 4034, the first terminal of the ninth transistor T9 and the first terminal of the second capacitor C2 are electrically connected to the power line 80 through point D, and the electrical signal obtained from the power line 80 is the first power signal VDD.

[0214] The first terminal of the first input transistor T12 is electrically connected to the power line 80 through point A, and the electrical signal obtained from the power line 80 is the first power signal VDD.

[0215] The second terminal of the light-emitting control transistor T11 is electrically connected to the input terminal of the light-emitting element LED.

[0216] The remaining circuit structure in the luminous threshold compensation circuit 4034 is the same as... Figure 4 The circuit structure shown is the same, so it will not be described again here.

[0217] In the shutdown control signal generation circuit 4035, the first terminal of the fourth transistor T4 is electrically connected to the power supply line 80, and the electrical signal obtained from the power supply line 80 is the first power supply signal VDD.

[0218] The first terminal of the second transistor T2 is electrically connected to the power supply line 80, and the electrical signal obtained from the power supply line 80 is the second power supply signal REF.

[0219] The remaining circuit structure in the 4035 shutdown control signal generation circuit is the same as... Figure 4 The circuit structure shown is the same, so it will not be described again here.

[0220] Correspondingly, Figure 6 Each transistor in the circuit is turned on when it receives a low level at its control terminal and turned off when it receives a high level at its control terminal.

[0221] based on Figure 6 The described circuit structure and its corresponding driving signal timing diagram are as follows: Figure 7 As shown.

[0222] The following is about Figure 6 The operation of the circuit structure shown will be explained.

[0223] The circuit operation within one display cycle is explained below. One display cycle T includes the reset phase t1, the compensation phase t2, the data writing phase t3, and the display phase t4 in sequence.

[0224] During the reset phase t1 in the drive signal timing diagram, the first scan signal SN-1 and the second power supply signal VDD are at low levels, while the second scan signal SN, the third scan signal SN+1, and the light emission control signal EM are at high levels. Therefore, the light emission threshold compensation circuit 4034 does not receive the turn-off control signal S. BD .

[0225] Since the first scan signal SN-1 is low, the reset transistor T10 is turned on, and the second power supply signal REF obtained from its first terminal is transmitted to point B.

[0226] The second capacitor C2 obtains and stores the second power supply signal REF from point B.

[0227] Since the light-emitting control signal EM is at a high level, the light-emitting control transistor T11 is turned off and does not transmit electrical signals.

[0228] The LED light-emitting element does not receive an electrical signal and therefore does not emit light.

[0229] When the control signal S is turned off BD When the power supply signal is provided by the shutdown control signal generation circuit 4035, the third power supply signal SWEEP is adjusted from low level to high level during the reset phase t1.

[0230] Since the first scan signal SN-1 is at a low level, the second transistor T2 is turned on, and the second power supply signal REF obtained from its first terminal is transmitted to point G.

[0231] The third capacitor C3 obtains the second power signal REF from point G, adjusts the potential value of its first terminal according to the second power signal REF, and adjusts the potential value of its second terminal according to the third power signal SWEEP. Due to the coupling effect of the third capacitor C3, the potential values ​​of its first and second terminals do not affect each other.

[0232] The sixth transistor T6 is turned off according to the light emission control signal EM, and does not output the turn-off control signal S. BD .

[0233] During the compensation phase t2 in the driving signal timing diagram, the second scan signal SN is low, while the first scan signal, the third scan signal, and the light emission control signal are high. Therefore, the light emission threshold compensation circuit 4034 does not receive the turn-off control signal S. BD .

[0234] Since the second scan signal SN is low, the compensation transistor T7 is turned on, shorting the second terminal and the control terminal of the drive transistor T9.

[0235] Since the second terminal and the control terminal of the ninth transistor T9 are shorted, the ninth transistor T9 determines the first power supply signal VDD after compensation of the first threshold voltage Vth9 from its control terminal based on the first power supply signal VDD obtained from its first terminal and its first threshold voltage Vth9, and synchronizes the electrical signal with the potential value of point B.

[0236] The electrical potential at point B is V. VDD +Vth9.

[0237] Since the second scan signal SN is low, the first input transistor T12 is turned on, transmitting the first power supply signal VDD acquired at its first terminal to the second terminal of the first capacitor C1. The potential value of the second terminal of the first capacitor C1 is adjusted to V. VDD .

[0238] Since the potential value obtained by the first terminal of the first capacitor C1 from point B is V VDD +Vth9, the potential value at its second terminal is V VDD Then, the voltage difference across the first capacitor C1 is determined to be the first threshold voltage Vth9.

[0239] Since the light-emitting control signal EM is at a high level, the light-emitting control transistor T11 is turned off and does not transmit electrical signals.

[0240] The LED light-emitting element does not receive an electrical signal and therefore does not emit light.

[0241] When the control signal S is turned off BD When the power supply signal is provided by the shutdown control signal generation circuit 4035, the third power supply signal SWEEP is at a high level during the time period corresponding to the reset phase t2.

[0242] Since the second scan signal SN is low, the third transistor T3 is turned on, and the pulse width modulation signal PWMD obtained from its first terminal is transmitted to the first terminal of the first transistor T1.

[0243] Since the second scan signal SN is low, the fifth transistor T5 is turned on, shorting the second terminal of the first transistor T1 and the control terminal.

[0244] Since the second terminal of the first transistor T1 is shorted to the control terminal, it forms a diode structure with the fifth transistor T5. The potential value of its control terminal is the sum of the potential value of its first terminal and its threshold voltage.

[0245] Since the potential value of the electrical signal acquired at the first terminal of the first transistor T1 is V PWMD If its threshold voltage is the second threshold voltage Vth1, then the potential value of its control terminal is V. PWMD +Vth1.

[0246] The first transistor T1 synchronizes the potential value of its control terminal to point G. C3 obtains the potential value from point G, stores it, and adjusts the potential value of its first terminal according to the potential value.

[0247] Since the light emission control signal EM is not yet high, the sixth transistor T6 remains off and does not output the off control signal S. BD .

[0248] During the data writing phase t3 in the drive signal timing diagram, the third scan signal SN+1 is low, while the first scan signal SN-1, the second scan signal SN, and the light emission control signal EM are high. Therefore, the light emission threshold compensation circuit 4034 does not receive the turn-off control signal S. BD .

[0249] Since the second scan signal SN is high, the first input transistor T12 is turned off, stopping the transmission of the first power supply signal VDD to the first capacitor C1.

[0250] Since the third scan signal SN+1 is low, the data writing transistor T8 is turned on, and the drive data PAMD obtained from its first terminal is transmitted to the second terminal of the first capacitor C1.

[0251] The voltage change at the second terminal of the first capacitor C1 is ΔV = V VDD -V PAMD Since the first terminal of the first capacitor C1 and the second terminal of the second capacitor C2 are electrically connected, and the first terminal of the second transistor C2 receives a stable first power supply signal VDD, the potential value of the first terminal of the first capacitor C1 is adjusted based on the bootstrap effect of the first capacitor C1.

[0252] The potential value at the first terminal of the first capacitor C1, i.e., the potential value at point B, is V. B =V VDD +Vth9+ΔV*c1 / (c1+c2)=V VDD +Vth9+(V VDD -VPAMD )*c1 / (c1+c2). Where c1 is the capacitance of the first capacitor C1 and c2 is the capacitance of the second capacitor C2.

[0253] Since the light-emitting control signal EM is at a high level, the light-emitting control transistor T11 is turned off and does not transmit electrical signals.

[0254] The LED light-emitting element does not receive an electrical signal and therefore does not emit light.

[0255] When the control signal S is turned off BD When the power supply signal is provided by the shutdown control signal generation circuit 4035, the third power supply signal SWEEP is at a high level during the time period corresponding to the data writing stage t3.

[0256] Since the second scan signal SN is high, the third transistor T3 is turned off, stopping the transmission of the pulse width modulation signal PWMD to the first transistor T1.

[0257] Since the second scan signal SN is high, the fifth transistor T5 is turned off, and the second terminal and the control terminal of the first transistor T1 are disconnected.

[0258] The first transistor T1 is turned off according to the potential value at point G.

[0259] Since the light emission control signal EM is high, the sixth transistor T6 remains off and does not output the turn-off control signal S. BD .

[0260] During the time period corresponding to stage t4 shown in the driving signal timing diagram, the light emission control signal EM is at a low level, while the first scan signal SN-1, the second scan signal SN, and the third scan signal SN+1 are at a high level.

[0261] The display stage t4 includes the light-emitting stage t41 and the non-light-emitting stage t42.

[0262] The light emission threshold compensation circuit 4034 did not receive the turn-off control signal S during the light emission stage t41. BD During the non-light-emitting phase, t42 acquires the turn-off control signal S. BD .

[0263] During the period corresponding to the light emission stage t41, since the third scan signal SN+1 is at a high level, the data writing transistor T8 is turned off, and the transmission of the PAMD signal stops.

[0264] Since the second scan signal SN is high, the compensation transistor T7 is turned off, and the second terminal and the control terminal of the driving transistor T9 are disconnected.

[0265] Because the shutdown control signal S was not acquired. BDThe potential value of the control terminal of the driving transistor T9 is V. VDD +Vth9+(V VDD -V PAMD The potential value at the first terminal of the )*c1 / (c1+c2) is V. VDD When the driving transistor T9 is turned on, the current value of the generated driving signal is k((V) VDD -V PAMD )*c1 / (c1+c2)).

[0266] The driving transistor T9 transmits the driving signal to the first terminal of the light-emitting control transistor T11.

[0267] Since the light-emitting control signal EM is at a low level, the light-emitting control transistor T11 is turned on, and the driving signal obtained from its first terminal is transmitted to the light-emitting element LED.

[0268] The light-emitting element LED emits light according to the driving signal, and its light intensity is not affected by the drift of the first threshold voltage Vth9 of the driving transistor T9.

[0269] During the non-light-emitting phase t42, the turn-off control signal S is acquired at point B. BD The potential values ​​at the second terminal of the second capacitor C2 and the first terminal of the first capacitor C1 are both adjusted to the off control signal S. BD The corresponding potential value.

[0270] When the control signal S is turned off BD When the first power supply signal is VDD, the potential values ​​of the first terminal and the control terminal of the ninth transistor T9 are the same, the ninth transistor T9 is turned off, and the generation of drive signals is stopped.

[0271] The light-emitting control transistor T11 remains in the on state. Since its first terminal no longer receives a drive signal, its second terminal no longer transmits a drive signal to the light-emitting element LED.

[0272] The LED light-emitting element stops emitting light.

[0273] When the control signal S is turned off BD When the power supply signal is provided by the shutdown control signal generation circuit 4035, during the time period corresponding to the display stage t4, the third power supply signal SWEEP is a ramp signal that is adjusted from high level to low level.

[0274] During the period corresponding to the light-emitting stage t41, the third power supply signal SWEEP is adjusted from a high level to a third level, which is greater than a low level and less than a high level.

[0275] The potential value at the first terminal of the third capacitor C3 decreases as the third power supply signal SWEEP, which is obtained from its second terminal, decreases.

[0276] The third level is the level that controls the first transistor T1 to turn on.

[0277] Therefore, during the light-emitting stage t41, the first transistor T1 is not turned on.

[0278] Since the light emission control signal EM is at a low level, the fourth transistor T4 is turned on, and the first power supply signal VDD obtained from its first terminal is transmitted to the first terminal of the first transistor T1.

[0279] Since the first transistor T1 is not conducting, the electrical signal acquired at its first terminal cannot be transmitted to the sixth transistor T6.

[0280] Since the light emission control signal EM is low, the sixth transistor T6 is turned on. Because its first terminal does not receive an electrical signal, it still does not output the turn-off control signal S. BD .

[0281] During the non-light-emitting period t42, the third power supply signal SWEEP is adjusted from the third level to the low level.

[0282] Since the voltage at the first terminal of the third capacitor C3 controls the first transistor T1 to turn on when the third power supply signal SWEEP is at the third level, the first transistor T1 does not turn on during the non-light-emitting stage t42.

[0283] As the fourth transistor T4 is turned on, it transmits the first power supply signal VDD to the first transistor T1.

[0284] Since the first transistor T1 is turned on, it transmits the first power supply signal VDD to the sixth transistor T6.

[0285] Because the sixth transistor T6 is turned on, it outputs the first power supply signal VDD to point F, so that point B, which is electrically connected to point F, receives the turn-off control signal S. BD .

[0286] In the above technical solution, due to the adjustment of the third power supply signal level during the reset phase, the shutdown control signal generation circuit does not generate a shutdown control signal during the light emission phase of the display phase. This prevents it from affecting the first threshold voltage-compensated driving data stored in the storage circuit during the data writing phase. Consequently, the data writing circuit generates a driving signal independent of the first threshold voltage based on the first threshold voltage-compensated driving data. This ensures that the light emission intensity of the light-emitting element is only affected by the driving data when the light emission duration is consistent, thereby ensuring the uniformity of the light-emitting element during the display process. Furthermore, since the first end of the third capacitor is not affected by the third power supply signal before the display phase, the accuracy of the pulse width modulation signal written to its first end is ensured. This ensures the accuracy of adjusting the light emission duration of the light-emitting element according to the third power supply signal and the pulse width modulation signal during the display phase, thereby improving the light emission uniformity of the light-emitting element.

[0287] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0288] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A display device, comprising: The display panel is provided with multiple gate lines, multiple data lines, and multiple sub-pixel circuits, as well as power lines. Each of the sub-pixel circuits includes a pixel driving circuit and a light-emitting element; The pixel driving circuit is characterized in that it includes a light emission threshold compensation circuit, the light emission threshold compensation circuit includes a storage circuit and a data writing circuit, and the storage circuit includes a first input transistor, a first capacitor and a second capacitor. The second terminal of the second capacitor is electrically connected to the first terminal of the first capacitor, and the first terminal of the second capacitor is connected to the power supply line; The first terminal of the first input transistor serves as the first terminal of the storage circuit. The second terminal of the first input transistor is electrically connected to the second terminal of the first capacitor. The control terminal of the first input transistor is electrically connected to the gate line. It is configured to obtain a first power supply signal from the first terminal of the first input transistor, obtain a second scan signal from the control terminal of the first input transistor, control the conduction state of the first input transistor by the second scan signal, and transmit the first power supply signal to the second terminal of the first capacitor when the first input transistor is turned on. The first terminal of the first capacitor serves as the second terminal of the storage circuit, and the second terminal of the first capacitor serves as the third terminal of the storage circuit. It is configured to, when the first power signal is acquired at the second terminal of the first capacitor, acquire the first power signal after first threshold voltage compensation from the first terminal of the first capacitor, determine and store the first threshold voltage based on the voltage difference across the first capacitor; when driving data is acquired at the second terminal of the first capacitor, output the driving data after first threshold voltage compensation from the first terminal of the first capacitor based on the driving data and the first threshold voltage. The first end of the data writing circuit is electrically connected to the power line, and the second end of the data writing circuit is electrically connected to the second end of the storage circuit. It is configured such that during the compensation phase, the first end of the data writing circuit obtains a first power signal from the power line and obtains a first power signal after the first threshold voltage compensation from the second end of the data writing circuit; after the compensation phase, the first threshold voltage is used to compensate the driving data to generate a driving signal. The light-emitting element and the data writing circuit are electrically connected and configured to emit light according to the driving signal.

2. The display device according to claim 1, characterized in that, The third terminal of the storage circuit and the third terminal of the data writing circuit are electrically connected and configured to acquire driving data from the third terminal after the compensation stage and output the driving data after the first threshold voltage compensation from the second terminal. The data writing circuit is configured to generate a drive signal based on the drive data after the first threshold voltage compensation when its second terminal only acquires the drive data after the first threshold voltage compensation, and to stop generating the drive signal based on the turn-off control signal when its second terminal acquires the turn-off control signal.

3. The display device according to claim 2, characterized in that, The data writing circuit includes a compensation transistor, a driving transistor, and a data writing transistor; The first terminal of the compensation transistor is electrically connected to the second terminal of the driving transistor, and its first terminal is electrically connected to the control terminal of the driving transistor. Its control terminal is electrically connected to the gate line. It is configured to obtain a second scan signal from its control terminal and control its conduction state by the second scan signal. The first terminal of the driving transistor serves as the first terminal of the data writing circuit, and its control terminal serves as the second terminal of the data writing circuit. It is configured to obtain the first power signal from its first terminal, and when its second terminal and the control terminal are short-circuited, to determine the first power signal after the first threshold voltage compensation from its control terminal; when it is turned on and its second terminal and the control terminal are disconnected, its control terminal obtains the driving data after the first threshold voltage compensation from the second capacitor, and generates a driving signal based on the driving data after the first threshold voltage compensation. The first end of the data writing transistor is electrically connected to the data line, and its second end serves as the third end of the data writing circuit. Its control end is electrically connected to the gate line and is configured to obtain the driving data from its first end, obtain a third scan signal from its control end, control its conduction state by the third scan signal, and output the driving data from its second end when it is on.

4. The display device according to claim 3, characterized in that, The light emission threshold compensation circuit also includes a light emission control transistor and a reset transistor; The first terminal of the light-emitting control transistor is electrically connected to the first terminal of the driving transistor, its control terminal is electrically connected to the gate line, and its second terminal is electrically connected to the light-emitting element. It is configured to obtain a light-emitting control signal from its control terminal and control its conduction state by the light-emitting control signal. The first terminal of the reset transistor is electrically connected to the power supply line, and its second terminal is electrically connected to the control terminal of the drive transistor. Its control terminal is electrically connected to the gate line. It is configured to obtain a second power supply signal from its first terminal and a first scan signal from its control terminal, and to control its conduction state by the first scan signal.

5. The display device according to claim 4, characterized in that, The pixel driving circuit further includes a shutdown control signal generation circuit, which includes a third capacitor, a first transistor, a second transistor, a fourth transistor, and a sixth transistor. The first terminal of the third capacitor is electrically connected to the control terminal of the first transistor, and its second terminal is electrically connected to the power line. It is configured to obtain a third power signal from its second terminal and adjust the potential value of its first terminal according to the third power signal. The control terminal of the first transistor is electrically connected to the first terminal of the third capacitor, and its conduction state is controlled by the potential value of the first terminal of the third capacitor. The first terminal of the second transistor is electrically connected to the power line, its second terminal is electrically connected to the first terminal of the third capacitor, its control terminal is electrically connected to the gate line, and it is configured to obtain the first scan signal from its control terminal, obtain the first power signal from its first terminal, and control its conduction state by the first scan signal. The first terminal of the fourth transistor is electrically connected to the power line, its second terminal is electrically connected to the first terminal of the first transistor, and its control terminal is electrically connected to the gate line. It is configured to obtain the second power signal from its first terminal and the light emission control signal from its control terminal, and to control its conduction state by the light emission control signal. The first terminal of the sixth transistor is electrically connected to the second terminal of the first transistor, its second terminal is electrically connected to the second terminal of the data writing circuit, and its control terminal is electrically connected to the gate line. It is configured to obtain the light emission control signal from its control terminal and control its conduction state by the light emission control signal.

6. The display device according to claim 5, characterized in that, A display cycle consists of the following phases in sequence: reset phase, compensation phase, data writing phase, and display phase. During the reset phase, the first scan signal and the second power signal are at a first level, the second scan signal, the third scan signal, and the light emission control signal are at a second level, and the light emission threshold compensation circuit does not acquire the shutdown control signal; The reset transistor is turned on according to the first scan signal, and transmits the second power supply signal obtained by its first terminal to the second terminal of the second capacitor and the control terminal of the driving transistor. The second capacitor stores the second power signal; The driving transistor is turned on according to the second power supply signal.

7. The display device according to claim 6, characterized in that, During the reset phase, the third power supply signal is adjusted from the first level to the second level; The second transistor is turned on according to the first scan signal, and transmits the second power supply signal obtained at its first terminal to the first terminal of the third capacitor; The third capacitor adjusts the potential value of its first terminal according to the second power signal, and adjusts the potential value of its second terminal according to the third power signal. The sixth transistor is turned off according to the light emission control signal and does not output the turn-off control signal.

8. The display device according to claim 7, characterized in that, During the compensation phase, the second scanning signal is at a first level, the first scanning signal, the third scanning signal, and the light emission control signal are at a second level, and the light emission threshold compensation circuit does not acquire the turn-off control signal. The compensation transistor is turned on according to the second scan signal, shorting the second terminal and the control terminal of the driving transistor; The driving transistor remains in the on state, and the first power signal after the first threshold voltage compensation is determined from its control terminal based on the first power signal obtained from its first terminal and its threshold voltage. The first input transistor is turned on according to the second scan signal, and transmits the first power supply signal obtained at its first terminal to the second terminal of the first capacitor. The first terminal of the first capacitor acquires the first power supply signal after the first threshold voltage compensation, and determines the stored voltage difference as the threshold voltage of the driving transistor based on the first power supply signal after the first threshold voltage compensation and the first power supply signal.

9. The display device according to claim 8, characterized in that, During the data writing phase, the third scan signal is at a first level, the first scan signal, the second scan signal, and the light emission control signal are at a second level, and the light emission threshold compensation circuit does not acquire the shutdown control signal; The data writing transistor is turned on according to the third scan signal, and transmits the driving data acquired at its first terminal to the second terminal of the first capacitor; The first capacitor outputs the drive data after the first threshold voltage compensation from its first terminal based on the drive data, the capacitance value of the first capacitor, the capacitance value of the second capacitor, and the threshold voltage. The second capacitor stores the drive data after threshold voltage compensation.

10. The display device according to claim 9, characterized in that, During the display phase, the light emission control signal is at a first level, and the first scan signal, the second scan signal, and the third scan signal are at a second level. The display phase includes a light-emitting phase and a non-light-emitting phase. During the light-emitting phase, the light-emitting threshold compensation circuit does not receive the shutdown control signal. The compensation transistor is turned off according to the second scan signal; The second capacitor provides the compensation transistor with the drive data after threshold voltage compensation; The driving transistor generates a driving signal based on the driving data after threshold voltage compensation and the first power supply signal, and transmits the driving signal to the light-emitting control transistor; The light-emitting control transistor is turned on according to the light-emitting control signal, and transmits the driving signal to the light-emitting element; The light-emitting element emits light according to the driving signal.

11. The display device according to claim 10, characterized in that, During the non-light-emitting phase, the light-emitting threshold compensation circuit acquires the shutdown control signal; The light-emitting control transistor remains in the on state according to the light-emitting control signal, the driving transistor is turned off according to the turn-off control signal, stops generating the driving signal, and the light-emitting control transistor stops transmitting the driving signal; The light-emitting element stops emitting light.

12. The display device according to claim 11, characterized in that, During the display phase, the third power signal is a ramp signal adjusted from the second level to the first level; during the light-emitting phase, the third power signal is adjusted from the second level to the third level; and during the non-light-emitting phase, the third power signal is adjusted from the third level to the first level. The third level is located between the first level and the second level. The third capacitor adjusts the potential value of its first terminal according to the potential change at its second terminal and the pulse width modulation signal after compensation by the second threshold voltage. The second transistor is turned on according to the light emission control signal, and transmits the first power signal to the first transistor; The first transistor is turned on when the potential value at the first terminal of the third capacitor is between the third level and the first level, and transmits the first power signal to the sixth transistor. When the potential value at the first terminal of the third capacitor is between the second level and the third level, it is turned off and does not transmit the first power signal. The sixth transistor is turned on according to the light emission control signal. When the first power signal is acquired, the first power signal is used as a turn-off control signal and transmitted to the control terminal of the driving transistor.

Images