High bonding force copper bump structure and preparation method thereof

Abstract

The application discloses a high-bonding-force copper bump structure and a preparation method thereof. The preparation method comprises the following steps: etching and grooving on the front surface of bare silicon, and then embedding a matching chip in the groove; etching and electroplating a TSV through hole on the front surface of the bare silicon; manufacturing an RDL redistribution layer on the TSV through hole; bonding the obtained semi-finished product with glass; thinning the back surface of the bare silicon, manufacturing a photoresist pattern, and exposing a photoresist opening; etching silicon at the photoresist opening to form a pit, exposing the bottom of the front surface TSV through hole; depositing an insulating layer on the etched pit, then electroplating or filling a conductive polymer to form a bump in the groove, and then removing the photoresist pattern on the surface; removing the glass, etching the silicon on both sides of the bump in the groove to expose the bump in the groove and the back of the chip, and then pasting a heat sink on the back of the chip. The application can improve the uniformity of the bump and the bonding force between the bump and the substrate, and can simplify the process flow and reduce the packaging cost.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to a high-bonding copper bump structure and its preparation method. Background Technology

[0002] As electronic devices increasingly demand high performance, small size, and multifunctionality, 3D chip stacking technology has received growing attention in recent years. To meet the multifunctional requirements of next-generation electronic products, interconnects with high I / O and fine pitch are needed. Therefore, fine-pitch interconnects using through-silicon vias (TSVs) for 3D semiconductor chip integration have been extensively developed. High-density bump fabrication is a key technology for achieving good interconnects in 3D integration, requiring the physical stacking of chips or wafers onto one chip or wafer while forming permanent electrical and mechanical connections between the device's I / O pins. Copper pillar bumps with a Cu / Ni / SnAg structure are currently a widely adopted fine-pitch interconnect bump solution.

[0003] Common bump fabrication processes typically involve photoresist exposure to create bump openings, followed by electroplating to form the bump structure. For small-size bump technology, the choice of photoresist material is crucial. On one hand, the photoresist resolution needs to meet the bump exposure requirements; on the other hand, the unevenness of the bump morphology after electroplating and etching, coupled with a large undercut in the seed layer, leads to weaker adhesion between the bump and the substrate. Therefore, exploring new processes to fabricate high-adhesion bumps to improve bump reliability has become a key focus in the industry. Summary of the Invention

[0004] To achieve the above objectives and technical effects, the technical solution adopted by this invention is as follows:

[0005] A method for preparing a high-bonding copper bump structure includes the following steps:

[0006] Step 1: Etch trenches on the front side of the bare silicon, and then embed the matching chip in the trenches;

[0007] Step 2: Etching and electroplating of TSV vias on the front side of the bare silicon;

[0008] Step 3: Create the RDL redistribution layer on the TSV via;

[0009] Step 4: Bond the semi-finished product obtained in Step 3 to the glass;

[0010] Step 5: Thin the back side of the bare silicon and fabricate a photoresist pattern to expose the photoresist opening;

[0011] Step 6: Perform silicon etching at the photoresist opening to form a pit, exposing the bottom of the front TSV via;

[0012] Step 7: Deposit an insulating layer in the etched pits, then electroplate or fill with a conductive polymer to form bumps in the grooves, and then remove the photoresist pattern on the surface.

[0013] Step 8: Remove the glass and etch the silicon on both sides of the bumps in the groove to expose the bumps in the groove and the back of the chip, and attach a heat sink to the back of the chip.

[0014] Furthermore, in step one, the shape of the slot is rectangular, circular, or trapezoidal, and the type of chip 2 is a logic chip, a memory chip, or a system-on-a-chip (SoC).

[0015] Furthermore, in step five, the thickness of the photoresist pattern is 10-20 micrometers.

[0016] Furthermore, in step six, the pit is a deep straight hole with a diameter of 10-40 micrometers and an etching depth of 20-40 micrometers.

[0017] Furthermore, in step seven, the insulating layer is made of oxide or nitride and has a thickness of 0.5-2 micrometers.

[0018] Furthermore, in step seven, the height of the protrusions in the groove is 20-60 micrometers.

[0019] Furthermore, in step eight, the bumps inside the trench are exposed to a depth of 15-55 micrometers, leaving 3-5 micrometers of silicon at the bottom as a protective structure for the bumps, increasing the bonding strength and reliability between the bumps and the substrate.

[0020] Furthermore, in step eight, the thickness of the heat sink is 20-50 micrometers.

[0021] The present invention also discloses a method for preparing a high-bonding copper bump structure and the resulting high-bonding copper bump structure.

[0022] Furthermore, the high-bonding copper bump structure includes bare silicon and a chip. The front side of the bare silicon is etched and plated with TSV vias, and an RDL redistribution layer is formed on the TSV vias. The back side of the bare silicon is etched with pits corresponding to the positions of the TSV vias. An insulating layer is deposited in the pits and formed into groove bumps by electroplating or filling with conductive polymer. The silicon around the groove bumps is etched away. The height of the groove bumps is greater than the height of the bare silicon. The chip is mounted in the groove of the bare silicon, and a heat sink is provided on the back side of the chip.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] This invention discloses a high-adhesion copper bump structure and its preparation method, which can improve the uniformity of the bumps and enhance the adhesion between the bumps and the substrate. Compared with traditional bump preparation, it reduces one photolithography and CMP polishing step, simplifies the process flow, and reduces packaging costs. Attached Figure Description

[0025] Figure 1 This is a structural schematic diagram of step one of the present invention;

[0026] Figure 2 This is a schematic diagram of the structure of step two of the present invention;

[0027] Figure 3 This is a schematic diagram of step three of the present invention;

[0028] Figure 4 This is a structural schematic diagram of step four of the present invention;

[0029] Figure 5 This is a structural schematic diagram of step five of the present invention;

[0030] Figure 6 This is a schematic diagram of step six of the present invention;

[0031] Figure 7 This is a structural schematic diagram of step seven of the present invention;

[0032] Figure 8 This is a schematic diagram of step eight of the present invention. Detailed Implementation

[0033] The present invention will now be described in detail so that its advantages and features can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0034] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0035] like Figure 1-8 As shown, this invention discloses a method for preparing a high-bonding copper bump structure, comprising the following steps:

[0036] Step 1: As Figure 1 As shown, silicon etching trenches are made on the front side of bare silicon 1. The shape of the trenches can be rectangular, circular, trapezoidal, etc. Then, a matching chip 2 is embedded in the trenches. The type of chip 2 is logic chip, memory chip, or system chip (SoC).

[0037] Step Two: As Figure 2 As shown, TSV vias 3 are etched and electroplated on the front side of bare silicon 1, and the electroplating material is a metal such as copper.

[0038] Step 3: As Figure 3 As shown, the RDL redistribution layer 4 is fabricated on the TSV via 3;

[0039] Step Four: As Figure 4 As shown, the semi-finished product obtained in step three is temporarily bonded to glass 5;

[0040] Step 5: As Figure 5 As shown, wafer thinning and stress-relief thinning are performed on the back side of bare silicon 1, and a photoresist pattern 6 with a thickness of 10-20 micrometers is fabricated to expose the photoresist opening.

[0041] Step Six: As Figure 6 As shown, silicon etching is performed at the above-mentioned photoresist opening to form a pit with good uniformity, exposing the bottom of the front TSV via 3; the pit is preferably a deep straight hole with a diameter of 10-40 micrometers and an etching depth of 20-40 micrometers.

[0042] Step Seven: As Figure 7 As shown, an insulating layer is deposited in the etched pit. The insulating layer can be made of oxide, nitride, etc., with a thickness of 0.5-2 micrometers. Then, a conductive polymer is electroplated or filled to form bumps 7 in the groove with a height of 20-60 micrometers. Then, the photoresist pattern 6 on the surface is removed.

[0043] Step 8: As Figure 8 As shown, glass 5 is removed, and the silicon on both sides of the bump 7 in the groove is etched to expose the bump 7 by 15-55 micrometers, but leaving a certain height (3-5 micrometers) of silicon at the bottom as a protective structure for the bump, increasing the bonding force and reliability between the bump and the substrate. At the same time, the back of the embedded chip 2 is exposed, and a heat sink 8 with a thickness of 20-50 micrometers is attached. The heat sink 8 can be metal, ceramic, or other heat dissipation materials.

[0044] The in-groove bump 7 structure obtained by the above-disclosed preparation method of this invention can maintain good sidewall uniformity, eliminate the need for etching the seed layer after electroplating, reduce undercut, and increase the adhesion of the bottom of the in-groove bump 7 by forming a protective layer through bare silicon 1. Compared with traditional bump preparation, this invention reduces one photolithography and CMP polishing step, simplifies the process flow, reduces packaging costs, and makes the process relatively simpler.

[0045] The present invention also discloses a high-bonding copper bump structure, including bare silicon 1 and chip 2. The bare silicon 1 has TSV vias 3 etched and electroplated on the front side, and an RDL redistribution layer 4 formed on the TSV vias 3. The bare silicon 1 has pits etched on the back side corresponding to the positions of the TSV vias 3. An insulating layer is deposited in the pits and formed into in-groove bumps 7 by electroplating or filling with conductive polymer. The silicon around the in-groove bumps 7 is etched away. The height of the in-groove bumps 7 is greater than the height of the bare silicon 1. The chip 2 is mounted in the groove of the bare silicon 1. A heat sink 8 is provided on the back side of the chip 2.

[0046] Example 1

[0047] like Figure 1-8 As shown, a method for preparing a high-bonding copper bump structure includes the following steps:

[0048] Step 1: As Figure 1 As shown, a silicon etching trench is made on the front side of bare silicon 1. The trench is rectangular in shape, and then a matching chip 2 is embedded in the trench. The type of chip 2 is a logic chip.

[0049] Step Two: As Figure 2 As shown, TSV vias 3 are etched and electroplated on the front side of bare silicon 1, and copper is used as the electroplating material.

[0050] Step 3: As Figure 3 As shown, the RDL redistribution layer 4 is fabricated on the TSV via 3;

[0051] Step Four: As Figure 4 As shown, the semi-finished product obtained in step three is temporarily bonded to glass 5;

[0052] Step 5: As Figure 5 As shown, wafer thinning and stress relief thinning are performed on the back side of bare silicon 1, and a photoresist pattern 6 with a thickness of 10 micrometers is fabricated to expose the photoresist opening;

[0053] Step Six: As Figure 6 As shown, silicon etching is performed at the above-mentioned photoresist opening to form a pit with good uniformity, exposing the bottom of the front TSV via 3; the pit is a deep straight hole with a diameter of 10 micrometers and an etching depth of 30 micrometers.

[0054] Step Seven: As Figure 7 As shown, an insulating layer is deposited in the etched pit. The insulating layer is made of nitride and has a thickness of 1 micrometer. Then, a conductive polymer is electroplated or filled to form bumps 7 in the groove with a height of 20 micrometers. Then, the photoresist pattern 6 on the surface is removed.

[0055] Step 8: As Figure 8 As shown, glass 5 is removed, and the silicon on both sides of the bump 7 in the groove is etched, exposing 15 micrometers of the bump 7 in the groove, but leaving 3 micrometers of silicon at the bottom as a protective structure for the bump, increasing the bonding force and reliability between the bump and the substrate. At the same time, the back of the embedded chip 2 is exposed, and a heat sink 8 with a thickness of 20 micrometers is attached. The heat sink 8 is made of ceramic.

[0056] The in-groove bump 7 structure obtained by the above-described preparation method disclosed in this embodiment can maintain good sidewall uniformity, eliminate the need for etching the seed layer after electroplating, reduce undercut, and increase the bonding force at the bottom of the in-groove bump 7 by forming a protective layer through bare silicon 1. Compared with traditional bump preparation, this invention reduces one photolithography and CMP polishing step, simplifies the process flow, reduces packaging costs, and makes the process relatively simpler.

[0057] A high-bonding copper bump structure includes bare silicon 1 and a chip 2. The bare silicon 1 has TSV vias 3 etched and electroplated on the front side, and an RDL redistribution layer 4 formed on the TSV vias 3. The bare silicon 1 has pits etched on the back side corresponding to the positions of the TSV vias 3. An insulating layer is deposited in the pits and formed into in-groove bumps 7 by electroplating or filling with conductive polymer. The silicon around the in-groove bumps 7 is etched away. The height of the in-groove bumps 7 is greater than the height of the bare silicon 1. The chip 2 is mounted in the pits of the bare silicon 1. A heat sink 8 is provided on the back side of the chip 2.

[0058] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.

[0059] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for preparing a high-bonding copper bump structure, characterized in that, Includes the following steps: Step 1: Etch trenches on the front side of the bare silicon, and then embed the matching chip in the trenches; Step 2: Etching and electroplating of TSV vias on the front side of the bare silicon; Step 3: Create the RDL redistribution layer on the TSV via; Step 4: Bond the semi-finished product obtained in Step 3 to the glass; Step 5: Thin the back side of the bare silicon and fabricate a photoresist pattern to expose the photoresist opening; Step 6: Perform silicon etching at the photoresist opening to form a pit, exposing the bottom of the front TSV via; Step 7: Deposit an insulating layer in the etched pits, then electroplate or fill with a conductive polymer to form bumps in the grooves, and then remove the photoresist pattern on the surface. Step 8: Remove the glass and etch the silicon on both sides of the bumps in the groove to expose the bumps in the groove and the back of the chip, and attach a heat sink to the back of the chip. In step eight, the bumps inside the trench are exposed to a depth of 15-55 micrometers, leaving 3-5 micrometers of silicon at the bottom as a protective structure for the bumps, increasing the bonding strength and reliability between the bumps and the substrate.

2. The method for preparing a high-bonding copper bump structure according to claim 1, characterized in that, In step one, the slot is rectangular, circular, or trapezoidal in shape, and the chip type is a logic chip, a memory chip, or a system-on-a-chip (SoC).

3. The method for preparing a high-bonding copper bump structure according to claim 1, characterized in that, In step five, the thickness of the photoresist pattern is 10-20 micrometers.

4. The method for preparing a high-bonding copper bump structure according to claim 1, characterized in that, In step six, the pits are deep straight holes with a diameter of 10-40 micrometers and an etching depth of 20-40 micrometers.

5. The method for preparing a high-bonding copper bump structure according to claim 1, characterized in that, In step seven, the insulating layer is made of oxide or nitride and has a thickness of 0.5-2 micrometers.

6. The method for preparing a high-bonding copper bump structure according to claim 1, characterized in that, In step seven, the height of the protrusions in the groove is 20-60 micrometers.

7. The method for preparing a high-bonding copper bump structure according to claim 1, characterized in that, In step eight, the thickness of the heat sink is 20-50 micrometers.

8. The high-bonding copper bump structure prepared by the method for preparing a high-bonding copper bump structure according to any one of claims 1-7.

9. A high-bonding-strength copper bump structure according to claim 8, characterized in that, The device includes bare silicon and a chip. The bare silicon has TSV vias etched and plated on its front side, and an RDL redistribution layer is formed on the TSV vias. The bare silicon has pits etched on its back side corresponding to the positions of the TSV vias. An insulating layer is deposited in the pits and conductive polymer is plated or filled to form bumps in the pits. The silicon around the bumps in the pits is etched away. The height of the bumps in the pits is greater than the height of the bare silicon. The chip is mounted in the pits of the bare silicon. A heat sink is provided on the back side of the chip.

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