Imaging system and method of operation thereof

Abstract

The present disclosure relates to real GS and OFG timing design for 1x2 shared HDR VDGS. An imaging system includes a pixel array having odd and even pixel cells. Each of the odd and even pixel cells includes a photodiode, a floating diffusion region, a transfer transistor, a reset transistor, a lateral overflow integration capacitor (LOFIC), and an overflow gate (OFG) transistor. The imaging system further includes a readout circuit having a sample and hold (SH) circuit and an analog-to-digital converter. The OFG transistor of each of the odd and even pixel cells is configured to direct image charge photo-generated by the respective photodiode away from the respective transfer transistor and reduce photodiode exposure offset during LOFIC readout during a global transfer period.

Description

Technical Field

[0001] This disclosure generally relates to image sensors, and specifically, but not exclusively, to high dynamic range (HDR) complementary metal-oxide-semiconductor (CMOS) image sensors. Background Technology

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, mobile phones, webcams, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, there is a desire to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range) through device architecture design and image acquisition processing. The technologies used to manufacture image sensors continue to evolve rapidly. For example, the demand for higher resolution and lower power consumption is driving further miniaturization and integration of these devices.

[0003] A typical image sensor operates in response to incident image light from an external scene. The image sensor comprises an array of pixels with photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge upon absorption. The image charge generated by the pixel light is measurable as an analog output image signal on the bit lines, which varies depending on the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out as an analog image signal from the bit lines and converted into digital values ​​to produce a digital image (e.g., image data) representing the external scene. The analog image signal on the bit lines is coupled to a readout circuit, which includes an input stage with an analog-to-digital converter (ADC) to convert those analog image signals from the pixel array into digital image signals. Summary of the Invention

[0004] According to one aspect of this disclosure, an imaging system is provided. The imaging system includes: a pixel array comprising: a plurality of odd-numbered pixel units arranged in odd-numbered rows; and a plurality of even-numbered pixel units arranged in even-numbered rows, wherein each of the odd-numbered and even-numbered pixel units is configured to generate a corresponding image signal in response to incident light, and wherein each of the odd-numbered and even-numbered pixel units includes: a photodiode configured to generate an image charge in response to image light; a floating diffusion region coupled to receive the image charge from the photodiode; a transfer transistor coupled between the photodiode and the floating diffusion region to transfer the image charge from the photodiode to the floating diffusion region; and a reset transistor coupled between a variable voltage source and the floating diffusion region, wherein the reset transistor is configured to respond to a reset control. The signal is switched; a lateral overflow integrating capacitor (LOFIC) coupled between the variable voltage source and the floating diffusion region; and an overflow gate (OFG) transistor coupled between a fixed voltage source and the photodiode; and a readout circuit coupled to the pixel array to read the image charge from the pixel array, wherein the readout circuit includes sample and hold (SH) circuitry coupled to one of the odd-numbered pixel units, one of the even-numbered pixel units, and one of a plurality of bit lines, wherein the OFG transistor of each of the odd-numbered and even-numbered pixel units is configured to guide the image charge photogenerated by the corresponding photodiode away from the corresponding transfer transistor and reduce photodiode exposure offset during LOFIC readout during the global transfer cycle.

[0005] According to another aspect of this disclosure, a method of operating an imaging system is provided. The method includes: coupling odd-numbered pixel units and even-numbered pixel units of a pixel array to a sample-and-hold (SH) circuit of a readout circuit, wherein each of the odd-numbered and even-numbered pixel units includes a photodiode configured to generate an image charge in response to incident light, a floating diffusion region coupled to receive the image charge from the photodiode, a transfer transistor coupled between the photodiode and the floating diffusion region to transfer the image charge from the photodiode to the floating diffusion region, a reset transistor coupled between a variable voltage source and the floating diffusion region, a lateral overflow integral capacitor (LOFIC) coupled between the variable voltage source and the floating diffusion region, and an overflow gate (OFG) transistor coupled between a fixed voltage source and the photodiode, wherein the reset transistor is configured to switch in response to a reset control signal; configuring the OFG transistor of the odd-numbered and even-numbered pixel units to direct the image charge generated by the respective photodiode away from the respective transfer transistor and to reduce photodiode exposure offset during LOFIC readout during a global transfer cycle. Attached Figure Description

[0006] The following figures illustrate non-limiting and non-exhaustive embodiments of this disclosure, wherein, unless otherwise stated, the same reference numerals in the various views refer to the same components.

[0007] Figure 1 This describes an example of an imaging system based on the teachings of this disclosure.

[0008] Figure 2 The diagram illustrates two example pixel circuits and an example sample and hold circuit based on the teachings of this disclosure.

[0009] Figure 3 The timing diagrams of two example pixel circuits according to the teachings of this disclosure are shown.

[0010] Figure 4 The timing diagrams of two example pixel circuits according to the teachings of this disclosure are shown.

[0011] In several views of the accompanying drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will understand that the elements in the figures are for illustrative purposes and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be enlarged relative to other elements to aid in understanding the various embodiments of this disclosure. Additionally, common but well-known elements that are not typically depicted in commercially viable embodiments are provided to facilitate unobstructed viewing of these various embodiments of this disclosure. Detailed Implementation

[0012] Examples of imaging systems are disclosed, which include pixel circuitry and sample-and-hold circuitry to provide reduced photodiode exposure offset for both even and odd-numbered pixels. Numerous specific details are set forth in the following description to provide a comprehensive understanding of the examples. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more specific details or using other methods, components, materials, etc. In other examples, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects.

[0013] The terms "an example" or "an embodiment" used in this specification mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one instance of this disclosure. Therefore, the phrases "in an example" or "in an embodiment" appearing in different places in this specification do not necessarily refer to the same example. Furthermore, in one or more examples, a particular feature, structure, or characteristic may be combined in any suitable manner.

[0014] For ease of description, spatially related terms (e.g., “below,” “under,” “above,” “below,” “above,” “top,” “bottom,” “left,” “right,” “center,” “middle,” and the like) may be used herein to describe the relationship of one element or feature to another element(s), as illustrated in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figures is rotated or flipped, then an element described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Thus, the exemplary terms “below” and “below” may cover both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially relative descriptive terms used herein shall be interpreted accordingly. Furthermore, it should be understood that when an element is described as being “between” two other elements, it may be the only element between the two other elements or there may be one or more intervening elements.

[0015] Several technical terms are used in this specification. These terms take their general meaning in the field of their respective fields, unless expressly defined herein or otherwise implied by the context in which they are used. It should be noted that element names and symbols are used interchangeably in this document (e.g., Si and silicon), however, they have the same meaning.

[0016] As will be discussed, various examples of disclosed imaging systems are provided, which have pixel circuitry and sample-and-hold circuitry to provide reduced photodiode exposure offset for both even and odd pixels. In some imaging systems, photodiodes are read out row by row or column by column (i.e., rolling shutter). When the exposure times of each row or column are not precisely synchronized, photodiode exposure differences can exist between even and odd pixels due to timing differences in transistor on and off states, for example. Photodiode exposure differences can cause noticeable artifacts in the image, such as horizontal or vertical banding of different brightness and / or color. Floating diffusion exposure offset (another type of exposure offset) occurs when there is a difference in charge transfer efficiency between pixels. However, because floating diffusion sensitivity is much lower than photodiode sensitivity (e.g., 100 times lower), correcting photodiode exposure offset can be more important and effective than correcting floating diffusion exposure offset.

[0017] It should be understood that the circuit design and timing diagrams taught in this disclosure reduce the photodiode exposure offset of the high conversion gain (HCG) and lateral overflow integrating capacitor (LOFIC) readout to a negligible level.

[0018] Therefore, as will be shown and described in various examples below, an example imaging system includes a pixel array having a plurality of odd-numbered pixel units arranged in odd-numbered rows and a plurality of even-numbered pixel units arranged in even-numbered rows. Each of the odd-numbered and even-numbered pixel units is configured to generate a corresponding image signal in response to incident light, and each of the odd-numbered and even-numbered pixel units includes: a photodiode configured to generate image charge in response to image light; a floating diffusion region coupled to receive image charge from the photodiode; a transfer transistor coupled between the photodiode and the floating diffusion region to transfer image charge from the photodiode to the floating diffusion region; a reset transistor coupled between a variable voltage source and the floating diffusion region, wherein the reset transistor is configured to switch in response to a reset control signal; a lateral overflow integrating capacitor (LOFIC) coupled between the variable voltage source and the floating diffusion region; and an overflow gate (OFG) transistor coupled between a fixed voltage source and the photodiode. The imaging system also includes readout circuitry coupled to the pixel array to read out image charge from the pixel array. The readout circuitry includes sample-and-hold (SH) circuitry coupled to one of the odd-numbered pixel units, one of the even-numbered pixel units, and one of the multiple bit lines, as well as an analog-to-digital converter (ADC) coupled to the multiple bit lines. The OFG transistors in each of the odd-numbered and even-numbered pixel units are configured to guide the image charge generated by the corresponding photodiode away from the corresponding transfer transistor and reduce photodiode exposure offset during LOFIC readout in the global transfer cycle.

[0019] For example, Figure 1 This describes an example of an imaging system 100 according to the teachings of this disclosure. Specifically, Figure 1 The example depicted illustrates an imaging system 100 implemented as a stacked chip scheme for a CMOS image sensor (CIS), comprising a pixel die 128 stacked with a logic die or application-specific integrated circuit (ASIC) die 130. In this example, the pixel die 128 includes a pixel array 102, and the ASIC die 130 includes a sample-and-hold circuit array 167 coupled to the pixel array 102 via pixel-level connections 106. The ASIC die 130 also includes control circuitry 110, readout circuitry 108, and functional logic 112. In one example, the pixel array 102 is a two-dimensional (2D) array of photodiodes or image sensor pixel circuitry 104 (e.g., pixels P1, P2…Pn). As illustrated, photodiodes are arranged in rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx) to acquire image data of people, places, objects, etc., which can then be used to present 2D images of people, places, objects, etc. However, photodiodes may not necessarily be arranged in rows and columns and may employ other configurations.

[0020] In one example, the readout circuit 108 can read image data from multiple photodiodes in the pixel array 102 via a sample-and-hold circuit array 167. As will be described in more detail below, in one example, the sample-and-hold circuit array 167 includes multiple sample-and-hold circuits coupled to pixel-level pixel circuits 104 via pixel-level connections 106 to sample and hold reset values ​​and signal values ​​from the pixel array 102. The image data read out by the readout circuit 108 can then be transmitted to functional logic 112. In various examples, the readout circuit 108 may also include an amplifier circuit system, an analog-to-digital converter (ADC) circuit system 107 coupled to a bitline, or others.

[0021] In one instance, functional logic 112 may store only image data or even manipulate the image data by applying post-processing image effects (such as cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or others). In one instance, readout circuitry 108 may read one line of image data at a time along the readout column lines (described) (i.e., the bit lines between sample and hold circuitry array 167 and readout circuitry 108) or may use various other techniques (not described) to read out image data, such as simultaneous serial readout or fully parallel readout of all pixel circuitry 104.

[0022] In one example, control circuitry 110 is coupled to pixel array 102 to control the operation of multiple photodiodes within pixel array 102. As will be described in more detail below, control circuitry 110 also includes a switch driver 168, which is coupled to generate control signals to control the sample and hold reset voltage value of sample and hold circuit array 167 and signal voltage values ​​in the voltage domain (VD) from pixel array 102. In the depicted example, control circuitry 110 is also coupled to generate a global shutter signal for substantially simultaneous control of image acquisition from all pixel values ​​of the pixel array; this may also be referred to as voltage domain global shutter (VDGS). In one example, the shutter signal is a global shutter signal used to simultaneously enable all pixel circuits 104 within pixel array 102 to simultaneously capture their respective image data during a single acquisition window. In one example, image acquisition is synchronized with, for example, a flash illumination effect.

[0023] In one example, the imaging system 100 may be included in a digital camera, mobile phone, laptop computer, or the like. Additionally, the imaging system 100 may be coupled to other hardware, such as a processor (general purpose or other), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), lighting / flash, electronic inputs (keyboard, touchscreen, trackpad, mouse, microphone, etc.), and / or a display. Other hardware may send instructions to the imaging system 100, retrieve image data from the imaging system 100, or manipulate image data supplied by the imaging system 100.

[0024] Figure 2 The diagram illustrates the even-pixel circuit 204a, the odd-pixel circuit 204b, and the example sample-and-hold (SH) circuit 267 according to the teachings of this disclosure. It should be understood that... Figure 2 The even-numbered pixel circuit 204a, the odd-numbered pixel circuit 204b, and the SH circuit 267 can be respectively included in Figure 1 Examples of one of the even-row pixel circuits 104, one of the odd-row pixel circuits 104, and one of the SH circuits of the sample and hold circuit array 167 in the imaging system 100 shown herein, and similarly named and numbered elements are similarly coupled and functioned below.

[0025] In the illustrated example, each of the even and odd (distinguished by the symbols “e” and “o” or “a” and “b”, respectively) pixel circuits 204a and 204b includes a photodiode 216 configured to generate image charge in response to incident light. A first floating diffusion region 220 is coupled to receive image charge from the photodiode 216. A transfer transistor 218 is coupled between the photodiode 216 and the first floating diffusion region 220 to transfer image charge from the photodiode 216 to the first floating diffusion region 220. A reset transistor 222 is coupled between a variable voltage source VRFD 225 and the first floating diffusion region 220. The reset transistor 222 is configured to switch in response to a reset control signal. A dual floating diffusion transistor 221 is coupled between the first floating diffusion region 220 and the reset transistor 222. A second floating diffusion region 228 is coupled to receive image charge from the first floating diffusion region 220. A lateral overflow integrating capacitor (LOFIC) 227 is coupled between a variable voltage source VRFD 225 and a first floating diffusion region 220 and / or a second floating diffusion region 228. A source follower transistor 224 has a gate terminal coupled to the first floating diffusion region 220 and a drain terminal coupled to receive a high voltage level AVDD 260. The source follower transistor 224 is configured to convert image charge in the first floating diffusion region 220 into an image signal, which is configured to be output through a sampling transistor 226 coupled between the source follower transistor 224 and the SH circuit 267.

[0026] Each of the even-numbered and odd-numbered pixel circuits 204a and 204b further includes an overflow gate (OFG) transistor 223 coupled between a high-voltage level AVDD 260 and a photodiode 216. (See below for reference.) Figure 3 and 4 In more detail, the OFG transistor 223 of each of the even and odd pixel units 204a, 204b is configured to guide the image charge generated by the corresponding photodiode 216 away from the corresponding transfer transistor 218 and reduce photodiode exposure offset.

[0027] The SH circuit 267 can be coupled to both the even-numbered pixel circuit 204a and the odd-numbered pixel circuit 204b via a shared pixel-level connection 206 (e.g., a hybrid connection). In an imaging system utilizing correlated double sampling (CDS), a reset signal is obtained by reading the charge at the first floating diffusion region 220 via the pixel-level connection 206 after a floating diffusion reset operation, in response to signals controlling both the reset transistor 222 and the dual floating diffusion transistor 221 simultaneously. Then, after the image charge is transferred to the first floating diffusion region 220, the image charge is read out via the pixel-level connection 206 to obtain an image signal.

[0028] The SH circuit 267 includes a row reset transistor 247 coupled between a voltage buffer VD 264 and a pixel-level connection 206, a cascode transistor 274 coupled between the row reset transistor 247 and ground 278, and a bias transistor 276 coupled between the cascode transistor 274 and ground 278. The row reset transistor 247 is configured to be controlled by a row reset control signal RST_ROW 254. In the depicted example, the bias transistor 276 is biased with a bias voltage Vb and acts as an SH current source, providing a current with a typical value of about 20 nA to the source follower transistor 224 through the pixel-level connection 206. The SH enable transistor 245 is configured to transfer a signal from the pixel-level connection 206 to a third floating diffusion region 265 in response to the SH enable control signal PIXEN 258. The third floating diffusion region 265 is coupled to the gate terminal of the second source follower transistor 270. The second source follower transistor 270 is coupled between the high voltage level AVDD 260 and the global selection transistor 272, which is configured to send a signal to the bit line 280.

[0029] SH circuit 267 further includes even and odd high conversion gain (HCG) reset capacitors 234a and 234b coupled between the row reset transistor 247 and the SH voltage source VM 250; even and odd HCG reset transistors 232a and 232b coupled between the row reset transistor 247 and the corresponding even and odd HCG reset capacitors 234a and 234b; even and odd HCG image capacitors 238a and 238b coupled between the row reset transistor 247 and the SH voltage source VM 250; even and odd HCG image transistors 236a and 236b coupled between the row reset transistor 247 and the corresponding even and odd HCG image capacitors 238a and 238b; and even and odd HCG image transistors 236a and 236b coupled between the row reset transistor 247 and the SH voltage source VM 250. Even and odd LAFIC reset capacitors 244a and 244b between 250, even and odd LAFIC reset transistors 242a and 242b coupled between the row reset transistor 247 and the corresponding even and odd LAFIC reset capacitors 244a and 244b, even and odd LAFIC image capacitors 248a and 248b coupled between the row reset transistor 247 and the SH voltage source VM 250, and even and odd LAFIC image transistors 246a and 246b coupled between the row reset transistor 247 and the corresponding even and odd LAFIC image capacitors 248a and 248b.

[0030] Even and odd HCG reset transistors 232a and 232b are configured to sample and hold even and odd HCG reset signals in even and odd HCG reset capacitors 234a and 234b in response to even and odd HCG reset storage signals SHR_H_e 252a and SHR_H_o 252b, respectively. HCG image transistors 236a and 236b are configured to sample and hold even and odd HCG image signals in even and odd HCG image capacitors 238a and 238b in response to even and odd HCG image storage signals SHS_H_e 256a and SHS_H_o 256b, respectively. LOFIC reset transistors 244a and 244b are configured to sample and hold even and odd LOFIC reset signals in response to even and odd LOFIC reset storage signals SHR_L_e 262a and SHR_L_o 262b, respectively, into even and odd LOFIC reset capacitors 244a and 244b. LOFIC image transistors 246a and 246b are configured to sample and hold even and odd LOFIC image signals in response to even and odd LOFIC image storage signals SHS_L_e 266a and SHS_L_o 266b, respectively, into even and odd LOFIC image capacitors 248a and 248b. The stored signals SHR_H_e 252a, SHR_H_o 252b, SHS_H_e 256a, SHS_H_o 256b, SHR_L_e 262a, SHR_L_o 262b, SHS_L_e 266a, and SHS_L_o 266b can be generated by a sample-and-hold driver circuit system (e.g., the switch driver 168 of the control circuit 110).

[0031] In various instances, the SH circuit 267 includes additional transistor and capacitor pairs for performing correlated multiple sampling (CMS), which further reduces noise at the cost of a longer readout cycle. In various instances, the even and odd pixel circuits 204a, 204b are arranged on the pixel die 228, and the SH circuit 267 is arranged on the ASIC die 230.

[0032] Figure 3 The timing diagrams for two example pixel circuits according to the teachings of this disclosure are shown. The timing diagrams include a global precharge cycle, a readout cycle, and a global transfer cycle. It should be understood that... Figure 3 The timing diagram can be contained in Figure 1 The timing diagram of an example of one of the pixel circuits 104 in the imaging system 100 shown herein, and similarly named and numbered elements are similarly coupled and function in the following text.

[0033] In the illustrated example, the upper half of the timing diagram depicts the timing of components used in the even-numbered pixel circuitry, and the lower half depicts the timing of components used in the odd-numbered pixel circuitry. For each of the even and odd pixels (distinguished by the symbols “e” and “o” or “a” and “b”, respectively), the timing diagram shows the timing of the global select signal GS 326, the reset control signal RST 322, the dual float diffusion control signal DFD 321, the variable voltage source VRFD 325, the transfer control signal TX 318, and the overflow gate control signal OFG 323.

[0034] During the global precharge cycle, the even and odd dual floating diffusion control signal DFD 321 is configured to remain high, and the even and odd overflow gate control signal OFG 323 is configured to remain low. The even and odd variable voltage source VRFD 325 is configured to switch to high at approximately time t1. The even and odd reset control signal RST 322 and the even and odd transfer control signal TX 318 are configured to be pulse-modulated so that the falling edges of the even and odd transfer control signal TX 318 occur together at time t2. In a conventional imaging system, the global precharge cycle can be divided into a first global precharge cycle for even pixel circuits and a second global precharge cycle for odd pixel circuits, thus creating a significant timing gap between the even and odd pixel circuits. Therefore, by simultaneously pulse-modulating the transfer control signal 318 for both even and odd pixel circuits, the photodiode exposure offset attributable to the global precharge cycle is reduced (if not eliminated).

[0035] Around time t3, the global selection signal GS 326a and reset control signal RST 322a of the even-numbered pixel circuit are configured for pulse modulation. Around time t4, the global selection signal GS 326b and reset control signal RST 322b of the odd-numbered pixel circuit are configured for pulse modulation. Although the even-numbered reset control signal RST 322a and the odd-numbered reset control signal RST 322b are not configured for a second simultaneous pulse modulation during the global precharge cycle, this only results in a floating diffusion exposure offset between the even-numbered and odd-numbered pixel circuits. Because the photodiode sensitivity is significantly higher than the floating diffusion sensitivity (e.g., 100 times higher) in most imaging systems, the floating diffusion exposure offset is not significant or noticeable in most cases. At time t5, the even-numbered and odd-numbered variable voltage sources VRFD 325 are configured to switch back to a low state.

[0036] During the readout cycle (e.g., rolling readout cycle), the image charge generated by the photodiode is converted into an analog voltage signal. Since the timing diagrams described do not show the circuitry used for the SH circuit (e.g.,...),... Figure 2The timing of the components of the SH circuit 267 shown in the figure is omitted so as not to obscure the novel aspects of this disclosure.

[0037] During the global transfer cycle, high conversion gain (HCG) readout is configured to occur before lateral overflow integration capacitor (LOFIC) readout. At time t6, the even and odd variable voltage sources VRFD 325 are configured to switch to a high state. Then, the even and odd dual floating diffusion control signal DFD 321 is configured to switch to a low state, thereby cutting off access to and from LOFIC in preparation for HCG readout. Between times t6 and t7, the even and odd global selection signals GS 326a and 326b are configured to sequentially pulse modulate the HCG reset signal readout for the even and odd pixel circuits, respectively. Around time t7, the even and odd transfer control signal TX 318 is configured to simultaneously pulse modulate, thereby transferring the photogenerated image charge to the floating diffusion region. Then, the even and odd global selection signals GS 326a and 326b are again sequentially pulse modulated for the HCG image signal readout for the even and odd pixel circuits, respectively.

[0038] The even and odd global selection signals GS 326a and 326b are not configured for simultaneous pulse modulation, which would cause photodiode exposure offset. However, the even and odd transfer control signal TX 318 is configured for simultaneous pulse modulation at approximately time t2 during the global precharge cycle and at approximately time t7 during the global transfer cycle, resulting in no photodiode exposure offset in the HCG readout. This contrasts with conventional imaging systems, where the global transfer cycle is divided into a first global transfer cycle for both HCG and LOFIC readouts in the even-numbered pixel circuitry and a second global transfer cycle for both HCG and LOFIC readouts in the odd-numbered pixel circuitry. Furthermore, the even and odd transfer control signal TX 318 is not simultaneously turned on and off during the global precharge and global transfer cycles, creating a significant timing gap between the even and odd-numbered pixel circuits.

[0039] After HCG readout, the even and odd dual floating diffusion control signal DFD 321 is configured to switch to a high state, thereby allowing the readout of the image charge stored in the LOFIC. The even and odd transfer control signal TX 318 is then configured to be pulse-modulated simultaneously, such that its falling edge occurs at time t8. The even and odd global selection signals GS 326a and 326b are configured to read out the LOFIC image signal and LOFIC reset signal of the even and odd pixel circuits, respectively, with sequential pulse modulation twice.

[0040] Similar to HCG readout, the even and odd global selection signals GS 326a, 326b are not configured for simultaneous pulse modulation, which can cause photodiode exposure shift. To address this issue, the even and odd overflow gate control signal OFG 323 is configured to switch to a high state at time t8 (i.e., at the falling edge of the even and odd transfer control signal TX 318). Therefore, the photogenerated image charge that caused the photodiode exposure shift during LOFIC readout (e.g., image charge leaked through the transfer transistor between even and odd LOFIC image signal readouts) is directed away from the transfer transistor and flows through the overflow gate transistors (e.g., the even and odd overflow gate transistors OFGe 223a, OFGo 223b) to a high voltage source (e.g., Figure 2 The high voltage level AVDD 260 is shown in the figure. In other words, during LOFIC readout, once the even and odd overflow gate control signal OFG 323 goes high, photodiode exposure no longer contributes to the readout and significantly reduces (if not eliminated) photodiode exposure.

[0041] The even and odd reset control signals RST 322 are not configured to pulse modulate simultaneously during the global transfer cycle; however, this again only results in a floating diffusion exposure offset between the even and odd pixel circuits. As mentioned above, because the photodiode sensitivity is significantly higher than the floating diffusion sensitivity (e.g., 100 times higher) in most imaging systems, the floating diffusion exposure offset is insignificant or negligible in most cases.

[0042] Figure 4 The timing diagrams for two example pixel circuits according to the teachings of this disclosure are shown. The timing diagrams include a global precharge cycle, a readout cycle, and a global transfer cycle. It should be understood that... Figure 4 The timing diagram can be contained in Figure 1 The timing diagram of an example of one of the pixel circuits 104 in the imaging system 100 shown herein, and similarly named and numbered elements are similarly coupled and function in the following text.

[0043] Apart from the timing of the even and odd overflow gate control signals OFG 423 during global precharge, Figure 4 The timing diagrams described in the document and Figure 3 The timing diagrams described herein are the same. Therefore, details of other signals will not be repeated to avoid ambiguity. Figure 4 The novel aspects of this disclosure are embodied in it.

[0044] Under extreme light conditions, photogenerated image charge can overflow from the photodiode into the floating diffusion region during the global precharge cycle, even if the transfer transistor is turned off. This is problematic because the pulse-modulated reset control signal RST 422 will cause any loss of this overflow charge. The amount of overflow charge lost during the precharge cycle can differ for even and odd pixel circuits because although the even and odd transfer control signals TX 418 are pulse-modulated simultaneously at t2, the even and odd reset control signals RST 422 are pulse-modulated a second time at different times, approximately at t3 and t4, respectively.

[0045] To address this discrepancy and reduce the resulting photodiode exposure offset, the even and odd overflow gate control signals OFG 423 can be configured to simultaneously switch to a high state at time t1 and back to a low state at time t5, allowing any overflowed charge to be redirected through the overflow gate transistors (e.g., even and odd overflow gate transistors OFGe 223a, OFGo 223b) to a high voltage source (e.g., Figure 2 The high voltage level AVDD 260 is shown in the diagram. Therefore, when the even and odd overflow gate control signal OFG 423 switches to the low state at time t5, the exposure of the photodiodes begins simultaneously for both even and odd pixel circuits, thereby reducing (if not eliminating) the photodiode exposure offset that occurs during the global precharge cycle under extreme light conditions.

[0046] Although the amount of charge accumulated in the floating diffusion region between even and odd pixel circuits may differ due to the different timing of the second pulse of the even and odd reset control signal RST 422, as mentioned above, in most imaging systems, the photodiode sensitivity is significantly higher than the floating diffusion sensitivity (e.g., 100 times higher), so in most cases the floating diffusion exposure offset is not significant or noticeable.

[0047] In various instances, Figure 4 The timing diagrams described herein can be used to operate even and odd pixel circuits (regardless of brightness (e.g., even under low light conditions)) to, for example, have simpler and more uniform timing.

[0048] The above description of the illustrative examples in this disclosure (including those described in the abstract) is not intended to be exhaustive or to limit this disclosure to its precise form. Although specific examples of this disclosure have been described herein for illustrative purposes, those skilled in the art will recognize that various modifications can be made within the scope of this disclosure.

[0049] Based on the above detailed description, these modifications may be made to this disclosure. The terminology used in the appended claims should not be construed as limiting this disclosure to the specific instances disclosed in the specification. Rather, the scope of this disclosure will be determined entirely by the appended claims, which will be interpreted according to the established principles of claim interpretation.

Claims

1. An imaging system comprising: A pixel array comprising: Multiple odd-numbered pixel units arranged in an odd-numbered row; and Multiple even-numbered pixel units, arranged in an even-numbered row. Each of the plurality of odd-numbered pixel units and the plurality of even-numbered pixel units is configured to generate a corresponding image signal in response to incident light, and Each of the plurality of odd-numbered pixel units and the plurality of even-numbered pixel units comprises: A photodiode configured to generate image charge in response to image light; A floating diffusion region, which is coupled to receive the image charge from the photodiode; A transfer transistor coupled between the photodiode and the floating diffusion region to transfer the image charge from the photodiode to the floating diffusion region; A reset transistor coupled between a variable voltage source and the floating diffusion region, wherein the reset transistor is configured to switch in response to a reset control signal; A lateral overflow integrating capacitor is coupled between the variable voltage source and the floating diffusion region; and An overflow gate transistor is coupled between a fixed voltage source and the photodiode; and A readout circuit coupled to the pixel array to read the image charge from the pixel array, wherein the readout circuit includes sample and hold circuitry coupled to one of the plurality of odd-numbered pixel units, one of the plurality of even-numbered pixel units, and one of the plurality of bit lines. The overflow gate transistor of each of the plurality of odd-numbered pixel units and the plurality of even-numbered pixel units is configured to direct the image charge generated by the corresponding photodiode away from the corresponding transfer transistor and reduce photodiode exposure offset during the lateral overflow integral capacitor readout during the global transfer cycle.

2. The imaging system of claim 1, wherein the overflow gate transistor of one of the plurality of odd-numbered pixel units and the overflow gate transistor of one of the plurality of even-numbered pixel units are configured to be simultaneously turned on before the lateral overflow integration capacitor is read out during the global transfer cycle.

3. The imaging system of claim 2, wherein the transfer transistor of one of the plurality of odd-numbered pixel units and the transfer transistor of one of the plurality of even-numbered pixel units are configured to be pulse-modulated simultaneously during the global transfer cycle, such that their falling edges are aligned with the timing of the turn-on of the overflow gate transistor of one of the plurality of odd-numbered pixel units and the overflow gate transistor of one of the plurality of even-numbered pixel units.

4. The imaging system of claim 1, wherein the overflow gate transistor of one of the plurality of odd-numbered pixel units and the overflow gate transistor of one of the plurality of even-numbered pixel units are configured to be simultaneously turned on at the beginning of a global precharge cycle and simultaneously turned off at the end of the global precharge cycle.

5. The imaging system of claim 1, wherein the reset transistor of one of the plurality of odd-numbered pixel units and the reset transistor of one of the plurality of even-numbered pixel units are configured to be pulse-modulated simultaneously during a global precharge cycle.

6. The imaging system of claim 1, wherein the reset transistor of one of the plurality of odd-numbered pixel units and the reset transistor of one of the plurality of even-numbered pixel units are configured to pulse modulate at different times during the global precharge cycle and during the global transfer cycle.

7. The imaging system of claim 1, wherein each of the plurality of odd-numbered pixel units and the plurality of even-numbered pixel units further comprises: A source follower transistor having a gate terminal coupled to the floating diffusion region; and A global selection transistor is coupled between the source follower transistor and the sample-and-hold circuit. The global selection transistor of one of the plurality of odd-numbered pixel units and the global selection transistor of one of the plurality of even-numbered pixel units are configured to pulse modulate at different times during the global precharge cycle and during the global transfer cycle.

8. The imaging system of claim 1, wherein the transfer transistor of one of the plurality of odd-numbered pixel units and the transfer transistor of one of the plurality of even-numbered pixel units are configured to pulse modulate simultaneously during a global precharge cycle.

9. The imaging system of claim 1, wherein the variable voltage source of one of the plurality of odd-numbered pixel units and the variable voltage source of one of the plurality of even-numbered pixel units are configured to be simultaneously turned on at the beginning of a global precharge cycle and simultaneously turned off at the end of the global precharge cycle.

10. The imaging system of claim 1, wherein the variable voltage source of one of the plurality of odd-numbered pixel units and the variable voltage source of one of the plurality of even-numbered pixel units are configured to be simultaneously turned on at the beginning of the global transfer cycle and simultaneously turned off at the end of the global transfer cycle.

11. The imaging system of claim 1, wherein the high conversion gain readout of one of the plurality of odd pixel units and one of the plurality of even pixel units is performed before or after the lateral overflow integration capacitor readout of one of the plurality of odd pixel units and one of the plurality of even pixel units.

12. The imaging system of claim 11, wherein the transfer transistor of one of the plurality of odd-numbered pixel units and the transfer transistor of one of the plurality of even-numbered pixel units are configured to pulse-modulate simultaneously between high conversion gain reset signal readout and high conversion gain image signal readout during the global transfer cycle.

13. A method of operating an imaging system, comprising: A sample and hold circuit of a readout circuit is coupled to odd-numbered pixel units and even-numbered pixel units of a pixel array, wherein each of the odd-numbered pixel units and the even-numbered pixel units includes a photodiode configured to generate image charge in response to incident light, a floating diffusion region coupled to receive the image charge from the photodiode, a transfer transistor coupled between the photodiode and the floating diffusion region to transfer the image charge from the photodiode to the floating diffusion region, a reset transistor coupled between a variable voltage source and the floating diffusion region, a lateral overflow integrating capacitor coupled between the variable voltage source and the floating diffusion region, and an overflow gate transistor coupled between a fixed voltage source and the photodiode, wherein the reset transistor is configured to switch in response to a reset control signal; The overflow gate transistors of the odd-numbered pixel units and the even-numbered pixel units are configured to direct the image charge generated by the corresponding photodiode away from the corresponding transfer transistor and reduce the photodiode exposure offset during the lateral overflow integral capacitor readout period in the global transfer cycle.

14. The method of claim 13, further comprising: The overflow gate transistors of the odd-numbered pixel units and the even-numbered pixel units are simultaneously turned on during the global transfer cycle before the lateral overflow integration capacitor is read out.

15. The method of claim 14, further comprising: The transfer transistors of the odd-numbered pixel units and the even-numbered pixel units are configured to be pulse-modulated simultaneously during the global transfer cycle, such that their falling edges are aligned with the turn-on time of the overflow gate transistors of the odd-numbered pixel units and the even-numbered pixel units.

16. The method of claim 13, further comprising: The overflow gate transistors of the odd-numbered pixel units and the even-numbered pixel units are configured to be turned on simultaneously at the beginning of the global precharge cycle and turned off simultaneously at the end of the global precharge cycle.

17. The method of claim 13, further comprising: The reset transistors of the odd-numbered pixel units and the even-numbered pixel units are pulse-modulated simultaneously during the global precharge cycle.

18. The method of claim 13, further comprising: The reset transistors of the odd-numbered pixel units and the even-numbered pixel units are pulse-modulated at different times during the global precharge cycle and during the global transfer cycle.

19. The method of claim 13, wherein each of the odd-numbered pixel units and the even-numbered pixel units further comprises: A source follower transistor having a gate terminal coupled to the floating diffusion region; and A global selection transistor is coupled between the source follower transistor and the sample-and-hold circuit. And the method further includes: The global selection transistors of the odd-numbered pixel units and the even-numbered pixel units are configured to pulse modulate at different times during the global precharge cycle and during the global transfer cycle.

20. The method of claim 13, further comprising: The transfer transistors of the odd-numbered pixel units and the even-numbered pixel units are pulse-modulated simultaneously during the global precharge cycle.

21. The method of claim 13, further comprising: The variable voltage sources configured for the odd-numbered pixel units and the even-numbered pixel units are simultaneously turned on at the beginning of the global precharge cycle and simultaneously turned off at the end of the global precharge cycle.

22. The method of claim 13, further comprising: The variable voltage sources configured for the odd-numbered pixel units and the even-numbered pixel units are simultaneously turned on at the beginning of the global transfer cycle and simultaneously turned off at the end of the global transfer cycle.

23. The method of claim 13, further comprising: The high conversion gain readout of the odd-numbered pixel units and the even-numbered pixel units is performed before or after the readout of the lateral overflow integration capacitor of the odd-numbered pixel units and the even-numbered pixel units.

24. The method of claim 23, further comprising: The transfer transistors configured for the odd-numbered pixel units and the even-numbered pixel units are pulse-modulated simultaneously between the high-conversion-gain reset signal readout and the high-conversion-gain image signal readout during the global transfer cycle.

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