Method and apparatus for power saving in semiconductor devices

Abstract

A semiconductor device includes a clock gating circuit and a control circuit. The clock gating circuit outputs a gated clock signal based on a clock signal. Transitions of the clock signal are output in the gated clock signal in response to a clock enable signal having an enable value, and transitions of the clock signal are inhibited from being output in the gated clock signal in response to the clock enable signal having an inhibit value. The control circuit includes a first portion that operates based on the clock signal. The first portion sets the clock enable signal to the inhibit value in response to an inhibit control, and sets the clock enable signal to the enable value in response to a wake-up control. The control circuit includes a second portion that operates based on the gated clock signal. The second portion provides the inhibit control to the first portion during operation.

Description

[0001] This application is a divisional application of the invention patent application filed on May 25, 2021, with application number 202180001831.9 and title "Method and apparatus for power saving in semiconductor devices". Technical Field

[0002] This application describes examples that generally involve semiconductor devices. Background Technology

[0003] Semiconductor devices, such as semiconductor memory devices and semiconductor computing devices, can have significant power consumption. For a variety of reasons, it is generally desirable to reduce the power consumption of semiconductor devices.

[0004] In the field of storage devices, semiconductor storage devices can be classified into volatile storage devices and non-volatile storage devices. Volatile storage devices may lose data when the power is off. Non-volatile storage devices can retain stored data even when the power is disconnected. To achieve higher data storage density, semiconductor manufacturers have developed vertical device technologies, such as 3D NAND flash memory technology. 3D NAND flash memory devices are a type of non-volatile storage device. Summary of the Invention

[0005] This disclosure provides a semiconductor device including a clock gating circuit and a control circuit. The clock gating circuit outputs a gated clock signal based on a clock signal. It outputs the clock signal in the gated clock signal in response to a transition in the clock enable signal having an enable value, and prevents the transition in the gated clock signal from being output in response to a transition in the clock enable signal having a disable value. The control circuit includes a first portion that operates based on the clock signal. The first portion sets the clock enable signal to a disable value in response to a disable control, and sets the clock enable signal to an enable value in response to a wake-up control. The control circuit includes a second portion that operates based on the gated clock signal. The second portion provides disable control to the first portion during operation.

[0006] This disclosure also provides a semiconductor memory device. The semiconductor memory device includes a memory cell array having memory cell blocks and peripheral circuitry coupled to the memory cell array. The peripheral circuitry includes a microcontroller unit (MCU). The MCU includes a clock gating circuit, a polling module, and a processing core. The clock gating circuit outputs a gated clock signal based on a clock signal. It outputs a clock signal in the gated clock signal in response to a clock enable signal having an enable value, and it prevents the output of the clock signal in the gated clock signal in response to a clock enable signal having a disable value. The polling module operates based on the clock signal and sets the clock enable signal to a disable value in response to a disable control, and sets the clock enable signal to an enable value in response to a wake-up control. The processing core operates based on the gated clock signal. The processing core provides disable control to the polling module during operation.

[0007] This disclosure also provides a method for power saving in a microcontroller unit (MCU). The method includes: receiving a disable control from a second part of the MCU by a first part of the MCU; and disabling signal transitions in a gated clock signal provided to the second part of the MCU by the first part of the MCU in response to the disable control. Furthermore, the method includes: enabling signal transitions in the gated clock signal by the first part of the MCU in response to a wake-up control. Attached Figure Description

[0008] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased for clarity of discussion.

[0009] Figure 1 A block diagram of a semiconductor device according to some examples of this disclosure is shown.

[0010] Figure 2 A block diagram of a semiconductor memory device according to some examples of this disclosure is shown.

[0011] Figure 3 Cross-sectional views and schematic symbols of memory cell strings of semiconductor memory devices according to some examples of this disclosure are shown.

[0012] Figure 4 A wake-up source priority table is shown according to some examples of this disclosure.

[0013] Figure 5 A graph is shown to illustrate signals in a control circuit according to some examples of this disclosure.

[0014] Figure 6The changes from the first firmware control flow to the second firmware control flow are shown in some examples according to this disclosure.

[0015] Figure 7 A flowchart outlining some examples of the process according to this disclosure is shown.

[0016] Figure 8 A block diagram of a memory system device according to some examples of this disclosure is shown. Detailed Implementation

[0017] The following disclosure provides numerous different examples, or illustrations, of various features for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For instance, forming a first feature on or over a second feature in the following description may include examples where the first and second features are formed in direct contact, and may also include examples where an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself prescribe a relationship between the various examples and / or configurations discussed.

[0018] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly in a similar manner.

[0019] This disclosure provides a semiconductor device with a polling module in a control circuit for power saving. The control circuit can operate based on a clock signal and a gated clock signal. The gated clock signal is provided by a clock gating circuit based on the clock signal. A transition in the gated clock signal is output in response to a clock enable signal having an enable value, and a transition in the output clock signal is disabled in response to a clock enable signal having a disable value. The control circuit includes a first portion called a polling module, and the polling module operates based on the clock signal. The control circuit also includes a second portion that operates based on the gated clock signal. In some examples, the second portion may have a larger number of transistors than the first portion. In examples, the second portion is implemented using sequential circuitry that operates in response to transitions in the gated clock signal. The polling module sets the clock enable signal to a disable value in response to a disable control from the second portion, and sets the clock enable signal to an enable value in response to a wake-up control from an external source, such as the control circuit. The second portion of the control circuit operates based on the gated clock signal. Therefore, when the clock enable signal has a disable value, the gated clock signal does not undergo a signal transition (e.g., a constant low voltage corresponding to "0", a constant high voltage corresponding to "1", etc.), and the transistors in the second part of the control circuit do not switch, reducing dynamic power consumption and enabling power savings.

[0020] Figure 1 A block diagram of a semiconductor device 100 according to some examples of this disclosure is shown. The semiconductor device 100 includes control circuitry 130 having a polling module for power saving. Figure 1 In the example, the control circuit 130 includes a first part 131 that operates based on a regular clock signal CK and a second part 132 that operates based on a gated clock signal CK-G. The first part 131 is also referred to as a polling module (PM) 131.

[0021] A regular clock signal CK can be provided by clock source 101. In this example, when semiconductor device 100 is powered on, the regular clock signal CK oscillates continuously between high and low voltages. In this example, clock source 101 includes clock generation circuitry that generates the regular clock signal CK when semiconductor device 100 is powered on. In another example, clock source 101 receives a system clock (not shown) from an external source of semiconductor device 100 and provides the regular clock signal CK based on the system clock.

[0022] In some examples, semiconductor device 100 includes a clock gating circuit 135 configured to generate a gated clock signal CK-G based on a regular clock signal CK and a clock enable signal EN. Transitions in the regular clock signal CK (e.g., voltage transitions between high and low voltages) are enabled / disabled based on the clock enable signal EN to be output in the gated clock signal CK-G. For example, when the clock enable signal EN has, for example, a transition between high and low voltages, a transition between high and low voltages, is enabled / disabled based on the clock enable signal EN. Figure 1 In the example, when the first value of "1" (e.g., a high voltage level) is (also called the enable value), the clock gating circuit 135 outputs a transition (voltage transition) in the gated clock signal CK-G in response to a transition in the regular clock signal CK; when the clock enable signal EN has, for example, a transition (voltage transition) in the gated clock signal CK-G. Figure 1 When the second value of "0" (e.g., ground voltage level) in the example is used (also known as the disabled value), the clock gating circuit 135 outputs a constant voltage level (e.g., ground voltage level) as the gated clock signal CK-G, regardless of transitions in the regular clock signal CK.

[0023] According to one aspect of this disclosure, the clock enable signal EN is provided by polling module 131. Polling module 131 operates based on a regular clock signal CK and may include any suitable combinational and sequential circuitry (e.g., latches, flip-flops, etc.). In some examples, polling module 131 receives control signals from external sources from second section 132 and / or control circuitry 130. For example, polling module 131 receives a disable control from second section 132 and a wake-up control from one or more external sources from control circuitry 130. The disable control may cause polling module 131 to set the clock enable signal EN to a disabled value, while the wake-up control may cause polling module 131 to set the clock enable signal EN to an enabled value.

[0024] In some examples, the second part 132 includes a large number of transistors in a sequential circuit that operate in response to transitions in a gated clock signal CK-G. When the gated clock signal CK-G has a constant voltage level (the transition is gated), the transistors in the sequential circuit do not switch.

[0025] During operation, in this example, polling module 131 initially outputs a clock enable signal EN with an enable value. When the clock enable signal EN has an enable value, clock gating circuit 135 outputs a transition in the gated clock signal CK-G in response to a transition in the regular clock signal CK. The gated clock signal CK-G is provided to the second part 132, and the transistors in the second part 132 can switch in response to the gated clock signal CK-G.

[0026] In response to certain conditions (e.g., idle mode, sleep mode), the second part 132 provides a disable control to cause the polling module 131 to output a clock enable signal EN with a disable value. When the clock enable signal EN has a disable value, the clock gating circuit 135 outputs a gated clock signal CK-G with a constant voltage level. Then, the transistors in the second part 132 do not switch, thereby reducing dynamic power consumption and enabling power savings.

[0027] Note that the polling module 131 operates based on the regular clock signal CK and can continue operating even when the second part 132 stops. When an external source provides wake-up control, the polling module 131 can output a clock enable signal EN with an enable value, and then the clock gating circuit 135 responds to the transition in the regular clock signal CK by outputting a transition in the gated clock signal CK-G. The timing circuitry in the second part 132 can then continue operating.

[0028] Note that semiconductor device 100 can be any suitable device. In some examples, semiconductor device 100 is a reference. Figure 2 and Figure 3 A detailed description of a semiconductor memory device.

[0029] Figure 2 A block diagram of a semiconductor memory device 200 according to some examples of this disclosure is shown. The semiconductor memory device 200 includes a memory cell array 202 and peripheral circuitry 201 coupled together. In some examples, the memory cell array 202 and the peripheral circuitry 201 are disposed on the same die (chip). In other examples, the memory cell array 202 is disposed on an array die, while the peripheral circuitry 201 is disposed on a different die, such as a die implemented using complementary metal-oxide-semiconductor (CMOS) technology and referred to as a CMOS die. The array die and the CMOS die are properly bonded and electrically coupled together. Reference will be made to... Figure 3 Examples describing bonded array dies and CMOS dies.

[0030] In some examples, a CMOS die can be coupled to multiple array dies. In one example, semiconductor memory device 200 is an integrated circuit (IC) package that encapsulates one or more array dies and one or more CMOS dies.

[0031] Semiconductor storage device 200 is configured to store data in a cell array 202 and perform operations in response to received commands (CMDs). In some examples, semiconductor storage device 200 can receive write commands (also called programming commands in some examples), read commands, erase commands, etc., and operate accordingly. In one example, semiconductor storage device 200 receives a write command with an address (ADDR) and data (DATA), and then semiconductor storage device 200 stores the data at that address in cell array 202. In another example, semiconductor storage device 200 receives a read command with an address, and then semiconductor storage device 200 accesses cell array 202 and outputs the data stored at that address in cell array 202. In yet another example, semiconductor storage device 200 receives an erase command with an address, and then semiconductor storage device 200 resets one or more cell blocks at that address to an unprogrammed state (also called an erased state), such as a "1" in 1 bit, "11" in 2 bits, "111" in 3 bits, etc., in NAND flash memory technology.

[0032] Typically, the storage cell array 202 may include one or more storage planes 260, and each storage plane 260 may include multiple storage blocks, such as... Figure 2 The diagram shows blocks 1 through N (where N is a positive integer). In some examples, concurrent operations can occur at different storage planes 260. In some examples, each of the storage blocks 1 through N is the smallest unit for performing an erase operation. Each storage block comprises multiple pages. In some examples, a page is the smallest unit that can be programmed. In the examples, a page's storage units can share a single word line.

[0033] In some examples, the memory cell array 202 is a flash memory array and is implemented using 3D NAND flash memory technology. Each of the memory blocks 1 through N includes multiple vertically arranged strings of memory cells (e.g., perpendicular to the main surface of the die). Each string of memory cells includes multiple transistors connected in series. (See reference...) Figure 3 Describe the details of the storage unit string.

[0034] In some examples, the peripheral circuit 201 includes an interface circuit 210 and a controller 220 coupled together.

[0035] Interface circuitry 210 includes suitable circuitry for interfacing with memory cell array 202 or with external components (e.g., host devices) of semiconductor memory device 200. In some examples, interface circuitry 210 includes a first portion, referred to as a host interface, for interfacing with host devices, and a second portion, referred to as an array interface, for interfacing with memory cell array 202. Figure 2In the example, interface circuit 210 includes, for example, Figure 2 The command decoding circuit 214, address decoding circuit 215, page buffer circuit 212, data input / output (I / O) circuit 211, and voltage generator 213 are coupled together as shown.

[0036] In some examples, address decoding circuitry 215 can receive an address (ADDR) from an I / O pin coupled to external circuitry (e.g., a host device) and perform address decoding. In some examples, address decoding circuitry 215 can operate in conjunction with controller 220 to perform address decoding. In some examples, the address received from the host device is a file system logical block address. In some examples, address decoding circuitry 215 and controller 220 can perform the functions of a flash translation layer (FTL) to translate the block address used by the file system into the address of a physical cell in memory cell array 202. In these examples, the translation from the block address used by the file system to the physical cell in memory cell array 202 can be used to exclude bad memory cells. In some examples, the address of the physical cell is in the form of a row address (R-ADDR) and a column address (C-ADDR). In response to the row address, address decoding circuitry 215 can generate word line (WL) signals and select signals, such as a top select gate (TSG) signal, a bottom select gate (BSG) signal, etc., and can provide the WL signals and select signals to memory cell array 202. In some examples, during a write operation, address decoding circuit 215 provides a WL signal and a select signal to the memory cell array 202 to select the page to be programmed. During a read operation, address decoding circuit 215 can provide a WL signal and a select signal to select the page to be buffered. During an erase operation, address decoding circuit 215 can provide the appropriate WL signal and select signal.

[0037] Page buffer circuitry 212 is coupled to the bit lines (BL) of memory cell array 202 and configured to buffer data, such as one or more pages of data, during read and write operations. In one example, during a write operation, page buffer circuitry 212 may buffer the data to be programmed and drive the data to the bit lines of memory cell array 202 to write the data into memory cell array 202. In another example, during a read operation, page buffer circuitry 212 may sense data on the bit lines of memory cell array 202 and buffer the sensed data for output.

[0038] exist Figure 2In one example, data I / O circuitry 211 is coupled to page buffer circuitry 212 via a data line (DL). In this example (e.g., during a write operation), data I / O circuitry 211 is configured to receive data from external circuitry (e.g., a host device) of semiconductor memory device 200 and provide the received data to memory cell array 202 via page buffer circuitry 212. In another example (e.g., during a read operation), data I / O circuitry 211 is configured to output data from memory cell array 202 to external circuitry (e.g., a host device) based on column address (C-ADDR).

[0039] Voltage generator 213 is configured to generate voltages at appropriate levels for proper operation of semiconductor memory device 200. For example, during a read operation, voltage generator 213 can generate voltages at appropriate levels for source voltage, body voltage, various WL voltages, select voltage, etc., for the read operation. In some examples, during a read operation, the source voltage is provided as the array common source (ACS) voltage to the source terminals of memory cell array 202; during a read operation, the body voltage is provided to, for example, a P-well (PW) that serves as the body portion of a memory cell string. The WL voltage and select voltage are provided to address decoding circuit 215, so that address decoding circuit 215 can output WL signals and select signals (e.g., TSG and BSG signals) at appropriate voltage levels during a read operation.

[0040] In another example, during the erase operation, voltage generator 213 can generate voltages at appropriate levels for the source voltage, body voltage, various WL voltages, select voltage, BL voltage, etc., suitable for the erase operation. In some examples, the source voltage is provided as the ACS voltage to the source terminals of the memory cell array 202 during the erase operation; the PW voltage is provided to the P-type wells that constitute the body portion of the memory cell string during the erase operation. The WL voltage and select voltage are provided to the address decoding circuit 215, so that the address decoding circuit 215 can output the WL signal and the BSG and TSG signals at appropriate voltage levels during the erase operation. The BL voltage is provided to the page buffer circuit 212, so that the page buffer circuit 212 can drive the bit line (BL) at an appropriate voltage level during the erase operation. Note that in some examples, the BL voltage can be applied to the bit line without passing through the page buffer circuit 212.

[0041] In another example, during a write operation, voltage generator 213 can generate voltages at appropriate levels for the source voltage, body voltage, various WL voltages, select voltage, BL voltage, verification voltage, reference voltage, etc., suitable for the write operation. In some examples, the source voltage is provided as the ACS voltage to the source terminals of the memory cell array 202 during the write operation; the PW voltage is provided to the P-type wells that constitute the body portion of the memory cell string during the write operation. The WL voltage, select voltage, and verification voltage are provided to the address decoding circuit 215, so that the address decoding circuit 215 can output the WL signal, as well as the BSG and TSG signals, at appropriate voltage levels during the write operation. The BL voltage and reference voltage are provided to the page buffer circuit 212, so that the page buffer circuit 212 can drive the bit line (BL) at appropriate voltage levels during the write operation and can sense the programming state in the verification step during the write operation.

[0042] In some examples, the command decoding circuit 214 is configured to receive commands (CMDs) from, for example, a host device via I / O pins during a command cycle. In some examples, the I / O pins may transmit other information, such as an address in an address cycle or data in a data cycle. In some examples, the received command is a command based on some high-level protocol (such as the USB protocol).

[0043] In some examples, command decoding circuit 214 and controller 220 can operate together to decode received commands. In one example, command decoding circuit 214 performs initial decoding on the received command and provides the command decoded by command decoding circuit 214 to controller 220 for further processing. Controller 220 can further perform decoding and then generate control parameters based on the command for controlling other circuits such as page buffer circuit 212, data I / O circuit 211, voltage generator 213, etc.

[0044] In some examples, controller 220 can control voltage generator 213 to generate a voltage of an appropriate level based on commands. Controller 220 can coordinate other circuitry to provide signals to memory cell array 202 at the appropriate time and appropriate voltage level.

[0045] exist Figure 2 In the example, controller 220 is in conjunction with Figure 1 The control circuit 130 in the middle is implemented in a similar manner using a polling module for power saving. Figure 2In some examples, controller 220 includes multiple processing cores that can cooperate during operation. In some examples, while multiple processing cores can operate simultaneously, in some scenarios, some processing cores may need to wait for feedback signals from other processing cores or new commands from the host device before further processing operations. According to some aspects of this disclosure, in such scenarios where a processing core detects an idle state (e.g., waiting for feedback signals from other processing cores or new commands from the host device), the processing core can provide disable control to a polling module coupled to the processing core, and the polling module can provide a clock enable signal with a disable value to cause a clock gating circuit to output a gated clock signal with a constant voltage. The gated clock signal is provided to the processing core, and due to the constant voltage of the gated clock signal, the processing core can stop signal switching.

[0046] In some examples, controller 220 includes multiple microcontroller units (MCUs), such as MCU-1230, MCU-P250 (where P is a positive integer), etc. Each MCU includes a polling module (PM), one or more processing cores (PCs), a clock gating circuit (CGC), and some memory, such as read-only memory (ROM), random access memory (RAM), etc. The polling module is also referred to as the first part of the MCU, and the one or more processing cores can be referred to as the second part of the MCU. For example, MCU-1230 includes PC-1 232, PM-1 231, CGC-1 235, ROM-1 237, and RAM-1 238; and MCU-P 250 includes PC-P 252, PM-P251, CGC-P 255, ROM-P 257, and RAM-P258. Note that controller 220 may include other MCUs (not shown) with similar configurations to MCU-1 230 and MCU-P 250.

[0047] The MCU-1 230 is described in detail below as an example. This description can be appropriately applied to other MCUs, such as the MCU-P 250, etc.

[0048] exist Figure 2In the example, PM-1 231 operates based on a regular clock signal CK, while PC-1 232 operates based on a gated clock signal CK-G-1. The regular clock signal CK can be provided by a clock source (not shown). In the example, when the semiconductor memory device 200 is powered on, the regular clock signal CK oscillates continuously between high and low voltages. In the example, the clock source includes a clock generation circuit that generates the regular clock signal CK when the semiconductor memory device 200 is powered on. In another example, the clock source receives the system clock from an external source of the semiconductor memory device 200 via an I / O pin (not shown) and generates the regular clock signal CK based on the system clock.

[0049] In some examples, the CGC-1 235 can generate a gated clock signal CK-G-1 based on a regular clock signal CK and a clock enable signal EN-1. Transitions in the regular clock signal CK (e.g., voltage transitions between high and low voltages) are enabled / disabled based on the clock enable signal EN-1 to be output in the gated clock signal CK-G-1. For example, when the clock enable signal EN-1 has a first value such as "1" (e.g., a high voltage level), also known as an enable value, the CGC-1 235 outputs a transition (voltage transition) in the gated clock signal CK-G-1 in response to a transition in the regular clock signal CK; when the clock enable signal EN-1 has a second value such as "0" (e.g., a ground voltage level), also known as a disable value, the CGC-1 235 outputs a constant voltage level such as a ground voltage level as the gated clock signal CK-G-1, regardless of transitions in the regular clock signal CK.

[0050] According to one aspect of this disclosure, the clock enable signal EN-1 is provided by PM-1 231. PM-1 231 operates based on a regular clock signal CK and may include any suitable combinational and sequential circuitry (e.g., latches, flip-flops, etc.). In some examples, PM-1 231 receives a disable control DC-1 from PC-1232 and a wake-up control WC-1 from an external source from MCU-1 230. The disable control DC-1 can cause PM-1 231 to set the clock enable signal EN-1 to a disabled value, and the wake-up control WC-1 can cause PM-1 231 to set the clock enable signal EN-1 to an enabled value.

[0051] Typically, the PC-1 232 is implemented using sequential circuitry, such as a pipelined architecture. Transistors in the PC-1 232, such as those in a flip-flop, switch in response to transitions in CK-G-1 (e.g., a rising edge or falling edge of CK-G-1). When CK-G-1 is gated (e.g., the transition is disabled), CK-G-1 has a constant voltage level, such as ground, and the transistors in the PC-1 232 can stop switching. Therefore, dynamic power consumption can be reduced, and power savings can be achieved.

[0052] In some examples, PC-1 232 is suitably coupled to ROM-1 237 and RAM-1 238 and can access ROM-1 237 and RAM-1 238 during operation. For example, ROM-1 237 stores firmware instructions, and PC-1 232 can access ROM-1 237 to read and execute the firmware instructions. Furthermore, in some examples, PC-1 232 can access RAM-1 238 to store data and read the stored data during operation.

[0053] According to one aspect of this disclosure, PC-1 232 can execute firmware to generate a disable control DC-1. In some examples, PM-1 231 initially outputs a clock enable signal EN-1 with an enable value. When the clock enable signal EN-1 has an enable value, CGC-1 235 outputs a transition in a gated clock signal CK-G-1 in response to a transition in the regular clock signal CK. The gated clock signal CK-G-1 is provided to PC-1 232, and transistors in PC-1 232 can switch in response to the gated clock signal CK-G-1. For example, in response to the gated clock signal CK-G-1, PC-1 232 can execute firmware instructions to set a value in a register (not shown). For ease of description, this register is referred to as the MCU disable register and is an internal register of MCU-1 230. In some examples, the MCU disable register is in PM-1 231. In the example, PC-1 232 can execute firmware instructions to set the MCU disable register to "1". In addition, in response to the switching from "0" to "1" in the MCU disable register, the PM-1 231 can output EN-1 with a disabled value.

[0054] When the clock enable signal EN-1 has a disabled value, the CGC-1 235 outputs a gated clock signal CK-G-1 with a constant voltage level (e.g., ground level). Then, the transistors in the PC-1 232 (e.g., transistors in a flip-flop) do not switch, thereby reducing dynamic power consumption and achieving power savings.

[0055] Note that PM-1 231 operates based on the regular clock signal CK, and PM-1 231 can continue operating when PC-1 232 stops operating. When an external source, such as MCU-P 250 or a host device, provides a signal in the wake-up control WC-1 (e.g., a signal switching from "0" to "1" from the wake-up source), the MCU disable register can be cleared and can have a value of "0". In response to the MCU disable register having a value of "0", PM-1 231 outputs a clock enable signal EN-1 with an enable value. Therefore, CGC-1 235 outputs a transition in the gated clock signal CK-G-1 in response to a transition in the regular clock signal CK. In response to a transition in the gated clock signal CK-G-1, PC-1 232 can wake up and continue operating.

[0056] Note that the wake-up control WC-1 can include signals from multiple wake-up sources. In some examples, the multiple wake-up sources can be appropriately ordered according to priority, and the PM-1 231 can generate a wake-up state WU-1 to indicate which wake-up source triggered the current wake-up. In some examples, the wake-up state WU-1 can be used to locate parts of the firmware to resume firmware execution. In some relevant examples, without a wake-up state, the processing core needs time after each wake-up to determine where to continue operation, which may sacrifice performance.

[0057] According to one aspect of this disclosure, firmware-based clock gating is used to control clock gating operations in an MCU. The firmware module can be updated to include firmware-based clock gating, and the firmware module can be reused appropriately. Therefore, firmware-based clock gating provides implementation flexibility.

[0058] According to another aspect of this disclosure, disabling the processing core can save a significant portion of dynamic power consumption. Furthermore, the wake-up state can be used to resume MCU operation and maintain the continuity of MCU operation without sacrificing performance. (See also...) Figure 4 and Figure 5 Further discussion on wake-up states.

[0059] Figure 3 A cross-sectional view of a semiconductor memory device 300 according to some examples of the present disclosure is shown. In some examples, the semiconductor memory device 300 may be a semiconductor memory device 200. According to some examples of the present disclosure, the semiconductor memory device 300 includes an array die 302 and a CMOS die 301 bonded together.

[0060] Note that in some examples, the semiconductor memory device may include multiple array dies and CMOS dies. The multiple array dies and CMOS dies may be stacked and bonded together. The CMOS dies are individually coupled to the multiple array dies and can drive the respective array dies to operate in a manner similar to that of semiconductor memory device 300.

[0061] The array die 302 includes a substrate 303 and memory cells formed on the substrate 303. The CMOS die 301 includes a substrate 304 and peripheral circuitry formed on the substrate 304. For simplicity, the main surface of the substrate 303 is referred to as the XY plane, and the direction perpendicular to the main surface is referred to as the Z direction.

[0062] Substrates 303 and 304 can be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. Substrates 303 and 304 can each comprise a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. Group IV semiconductors can include Si, Ge, or SiGe. Substrates 303 and 304 can each be a bulk wafer or an epitaxial layer.

[0063] Semiconductor memory device 300 includes a memory cell array (e.g., memory cell array 202) and peripheral circuitry (e.g., address decoding circuitry 215, page buffer circuitry 212, data I / O circuitry 211, voltage generator 213, controller 220, etc.). Figure 3 In the example, the memory cell array is formed on the substrate 303 of the array die 302, and the peripheral circuitry is formed on the substrate 304 of the CMOS die 301. The array die 302 and the CMOS die 301 are arranged face-to-face (the surface on which the circuitry is disposed is called the front side, and the opposite surface is called the back side) and bonded together.

[0064] In some examples, block-forming wells can be used as the main body of the block in substrate 303. Figure 3In the example, a P-type well 305 is formed in a substrate 303, and a block of three-dimensional (3D) NAND memory cell strings can be formed in the P-type well 305. The P-type well 305 can form the main body portion of the main 3D NAND memory cell string (e.g., connected to a PW terminal), and a voltage referred to as PW can be applied to the P-type well 305 via the PW terminal. In some examples, the memory cell array is formed as an array of vertical memory cell strings in a core region 306. In addition to the core region 306 and the peripheral region, the array die 302 includes a stepped region 307 (also referred to as a connection region in some examples) to facilitate connection to, for example, the gates of memory cells in the vertical memory cell strings, the gates of select transistors, etc. The gates of the memory cells in the vertical memory cell strings correspond to word lines in the NAND memory architecture.

[0065] exist Figure 3 In the example, vertical memory cell string 380 is shown as a representation of an array of vertical memory cell strings formed in core region 306. Figure 3 A schematic symbolic version of a vertical memory cell string 380' corresponding to a vertical memory cell string 380 is also shown. The vertical memory cell string 380 is formed in a layer stack 390. The layer stack 390 includes alternately stacked gate layers 395 and insulating layers 394. The gate layers 395 and insulating layers 394 are configured to form vertically stacked transistors. In some examples, the transistor stack includes memory cells and select transistors, such as one or more bottom select transistors, one or more top select transistors, etc. In some examples, the transistor stack may include one or more dummy select transistors. The gate layer 395 corresponds to the gate of the transistor. The gate layer 395 is made of a gate stack material such as a high-k gate insulating layer or a metal gate (MG) electrode. The insulating layer 394 is made of an insulating material such as silicon nitride or silicon dioxide.

[0066] According to some aspects of this disclosure, a vertical memory cell string is formed by a channel structure 381 extending vertically (in the Z direction) into a layer stack 390. The channel structures 381 may be disposed separately in the XY plane. In some examples, the channel structures 381 are arranged in an array between gate wire-cut structures (not shown). The gate wire-cut structures facilitate the replacement of the sacrificial layer with the gate layer 395 in a post-gate process. The array of channel structures 381 can have any suitable array shape, such as a matrix array shape along the X and Y directions, a zigzag array shape along the X or Y direction, a honeycomb (e.g., hexagonal) array shape, etc. In some examples, each channel structure has a circular shape in the XY plane and a columnar shape in the XZ and YZ planes. In some examples, the number and arrangement of the channel structures between the gate wire-cut structures are not limited.

[0067] In some examples, the channel structure 381 has a cylindrical shape extending in the Z direction perpendicular to the direction of the main surface of the substrate 303. In some examples, the channel structure 381 is formed into a circular shape in the XY plane and extends in the Z direction. For example, the channel structure 381 includes functional layers such as a barrier insulating layer 382 (e.g., silicon oxide), a charge storage layer (e.g., silicon nitride) 383, a tunneling insulating layer 384 (e.g., silicon oxide), a semiconductor layer 385, and an insulating layer 386, which have a circular shape in the XY plane and extend in the Z direction. In some examples, the barrier insulating layer 382 (e.g., silicon oxide) is formed on the sidewalls of the holes (entry layer stack 390) for the channel structure 381, and then the charge storage layer (e.g., silicon nitride) 383, the tunneling insulating layer 384, the semiconductor layer 385, and the insulating layer 386 are sequentially stacked from the sidewalls. Semiconductor layer 385 can be any suitable semiconductor material, such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material can be undoped or may include p-type or n-type dopants. In some examples, the semiconductor material is undoped intrinsic silicon. However, due to defects, the intrinsic silicon material may have approximately 10⁻⁶ ppm in some examples. 10 cm -3 The carrier density. The insulating layer 386 is formed of an insulating material such as silicon oxide and / or silicon nitride, and / or may be formed as an air gap.

[0068] According to some aspects of this disclosure, the channel structure 381 and the layer stack 390 together form a memory cell string 380. For example, the semiconductor layer 385 corresponds to the channel portion of the transistors in the memory cell string 380, and the gate layer 395 corresponds to the gate of the transistors in the memory cell string 380. Typically, the transistors have a gate that controls the channel and a drain and a source on each side of the channel. For simplicity, in Figure 3 In the example, Figure 3 The upper side of the channel in a transistor is called the drain, and Figure 3 The bottom side of the channel in a transistor is called the source. Note that in certain drive configurations, the drain and source can be switched. Figure 3 In the example, semiconductor layer 385 corresponds to the connection channel of the transistor. For a particular transistor, the drain of the particular transistor is connected to the source of the upper transistor above the particular transistor, and the source of the particular transistor is connected to the drain of the lower transistor below the particular transistor. Therefore, the transistors in the memory cell string 380 are connected in series.

[0069] The storage cell string 380 includes storage cell transistors (or storage cells). Based on carrier capture in the portion of the charge storage layer 383 corresponding to the floating gate of the storage cell transistor, the storage cell transistor can have different threshold voltages. For example, when a large number of holes are captured (stored) in the floating gate of the storage cell transistor, the threshold voltage of the storage cell transistor is below a predetermined value, and the storage cell transistor is in an unprogrammed state (also called an erased state), corresponding to logic "11" in two binary bits. When holes are expelled from the floating gate (or electrons are captured in the floating gate), the threshold voltage of the storage cell transistor increases, so the storage cell transistor can be programmed to other suitable states.

[0070] The memory cell string 380 includes one or more top select transistors configured to couple / decouple memory cells in the memory cell string 380 to / from bit lines, and the memory cell string 380 includes one or more bottom select transistors configured to couple / decouple memory cells in the memory cell string 380 to / from ACS.

[0071] The top-select transistor is controlled by the top-select gate (TSG). For example, when the TSG voltage (the voltage applied to the TSG) is greater than the threshold voltage of the top-select transistor, the top-select transistor is turned on and the memory cell is coupled to the bit line; when the TSG voltage (the voltage applied to the TSG) is less than the threshold voltage of the top-select transistor, the top-select transistor is turned off and the memory cell is decoupled from the bit line.

[0072] Similarly, the bottom-select transistor is controlled by the bottom-select gate (BSG). For example, when the BSG voltage (the voltage applied to the BSG) is greater than the threshold voltage of the bottom-select transistor, the bottom-select transistor is turned on and the memory cell is coupled to the ACS; when the BSG voltage (the voltage applied to the BSG) is less than the threshold voltage of the bottom-select transistor, the bottom-select transistor is turned off and the memory cell is decoupled from the ACS.

[0073] According to some aspects of this disclosure, the bottom portion of the semiconductor layer 385 in the channel hole corresponds to the source side of the vertical memory cell string 380, and the bottom portion is marked 385(S). A common source layer 389 is formed to be electrically connected to the source of the vertical memory cell string 380. The common source layer 389 may include one or more layers. In some examples, the common source layer 389 includes a silicon material, such as intrinsic polysilicon, doped polysilicon (e.g., N-type doped silicon, P-type doped silicon), etc. In some examples, the common source layer 389 may include a metal silicide to improve conductivity. The common source layer 389 is similarly electrically connected to the source of other vertical memory cell strings (not shown) to form an array common source (ACS).

[0074] In some examples, when the vertical storage cell string 380 is configured to be erased by a block, the common source layer 389 can extend and cover the core area and the step area of ​​the block. In some examples, the common source layer 389 can be appropriately insulated for different blocks that are erased individually.

[0075] exist Figure 3 In the example, in the channel structure 381, the semiconductor layer 385 extends vertically upward from the source side of the channel structure 381 and forms a top portion corresponding to the drain side of the vertical memory cell string 380. The top portion of the semiconductor layer 385 is labeled 385(D). Note that for ease of description, it is named as the drain side and the source side. The functions of the drain side and the source side may differ from their names.

[0076] exist Figure 3 In the example, connection structures such as via structure 372 with metal line 373, bonding structure 374, etc., can be formed to electrically couple the top portion 385(D) of the semiconductor layer to the bit line (BL).

[0077] Further in Figure 3 In the example, the stepped region 307 includes a step formed to facilitate word line connections to the gates of transistors (e.g., memory cells, top-select transistors, bottom-select transistors). For example, the word line connection structure 370 includes a contact structure 371, a via structure 372, and a metal line 373 electrically coupled together. The word line connection structure 370 can electrically couple the word line (WL) to the gate terminals of transistors in the memory cell string 380.

[0078] exist Figure 3 In the example, array die 302 and CMOS die 301 are arranged face-to-face (circuit side is the front, substrate side is the back) and bonded together. Typically, peripheral circuitry on the CMOS die interfaces the semiconductor memory device 300 with external circuitry.

[0079] exist Figure 3 In the example, CMOS die 301 and array die 302 each include bonding structures that can be aligned with each other. For example, CMOS die 301 includes bonding structure 334, while array die 302 includes a corresponding bonding structure 374. Array die 302 and CMOS die 301 can be properly aligned, so bonding structure 334 is aligned with bonding structure 374. When array die 302 and CMOS die 301 are bonded together, bonding structure 334 is bonded to and electrically coupled to bonding structure 374.

[0080] Although reference Figure 2 and Figure 3 3D NAND flash memory devices have been described in detail, but some aspects of this disclosure are not limited to 3D NAND flash memory devices.

[0081] For reference Figure 2 As described, wake-up control, such as that of the WU-1, can include signals from multiple wake-up sources. In some examples, any one of the wake-up sources can cause the MCU disable register to be cleared (e.g., to "0") and the transition in the gating clock signal to resume. In some examples, wake-up signal information, such as priority, can be appropriately recorded, and a wake-up state can be generated accordingly. The wake-up state can be used to achieve operational continuity.

[0082] In some examples, more than one wake-up source can simultaneously possess wake-up conditions, and wake-up states can be generated to indicate the wake-up source with the highest priority. In examples, polling modules such as the PM-1 231 include a first-in, first-out (FIFO) queue that can queue information about wake-up sources (with wake-up conditions) according to priority. For example, the queue can store wake-up states associated with each wake-up source according to their priority order.

[0083] Figure 4 Table 400 illustrates wake-up source priorities according to some examples of this disclosure. For each operation type (e.g., read operation type, programming operation type, erase operation type), multiple wake-up conditions can be defined. For example, a read operation type may include a first wake-up condition from read wake-up source 0, a second wake-up condition from read wake-up source 1, and a third wake-up condition from read wake-up source 2. The wake-up conditions have a priority order of read wake-up source 0 (highest priority), read wake-up source 1, and read wake-up source 2 (lowest priority). When multiple wake-up conditions occur simultaneously, such as when the first wake-up condition from read wake-up source 0 and the third wake-up condition from read wake-up source 2 occur within the same clock cycle, wake-up signal information can be appropriately stored. For example, a first wake-up state indicating read wake-up source 0 and a second wake-up state indicating read wake-up source 2 can be stored, for example, in a queue. A first operation (first firmware portion) associated with the first wake-up state can then be executed, followed by a second operation (second firmware portion) associated with the second wake-up state.

[0084] According to one aspect of this disclosure, MCU clock gating can be selectively disabled for corresponding operation types (e.g., read operation type, programming operation type, erase operation type). In some examples, the semiconductor memory device 200 is tested at the factory before being sold to a customer. During testing, the factory may decide to disable MCU clock gating for one or more operation types due to performance issues, for example, under extreme conditions. The factory can store three factory setting parameters (referred to as mcu_cg_dis_read, mcu_cg_dis_pgm, and mcu_cg_dis_ers) in an initialization partition 265, for example, in the memory cell array 202. In the example, the factory setting parameter mcu_cg_dis_read indicates whether clock gating for read operation types is disabled (e.g., "1" for disabled); the factory setting parameter mcu_cg_dis_pgm indicates whether clock gating for programming operation types is disabled (e.g., "1" for disabled); and the factory setting parameter mcu_cg_dis_ers indicates whether clock gating for erase operation types is disabled (e.g., "1" for disabled).

[0085] When the semiconductor memory device 200 is powered on, the information in the initialization partition 265 can be loaded into the controller 220 (e.g., RAM-1 238, RAM-P 258, etc.). Clock gating for one or more operation types can be disabled based on three factory setting parameters: mcu_cg_dis_read, mcu_cg_dis_pgm, and mcu_cg_dis_ers. In the example, the factory setting parameter mcu_cg_dis_read has a value of "1" (disabling clock gating for read operation types), the factory setting parameter mcu_cg_dis_pgm has a value of "0", and mcu_cg_dis_ers has a value of "0". Clock gating for read operation types can then be disabled, and clock gating can be performed during programming and erasing operations. For read operations, even if the MCU disable register has a value of "1" (indicating clock gating), the clock enable signals (e.g., EN-1, EN-P, etc.) remain at a value of "1" (the transition is not gated). Note that in this example, for programming and erasing operations, when the MCU disable register has a value of "1" (indicating clock gating), the clock enable signal (e.g., EN-1, EN-P, etc.) can be a value of "0" (the transition is gated).

[0086] Figure 5 A graph 500 is shown illustrating signals in a control circuit according to an example of this disclosure. For example, the control circuit is... Figure 2The MCU-1 230 is shown in the graph. The graph includes a state graph 510 for the operating state of PC-1 232; a waveform 520 for the clock enable signal EN-1; a waveform 530 for the regular clock signal CK; a waveform 540 for the gated clock signal CK-G-1; a waveform 550 for the signal from wake-up source 0; a waveform 560 for the signal from wake-up source 1; and a waveform 570 for the wake-up state.

[0087] In the example, initially, as shown at 511 in state diagram 510, PC-1 232 executes firmware part 1 (FW-P1) during operations such as read operations, programming operations, erase operations, etc. At some point, such as shown at 512, PC-1 232 waits for signals from other MCUs or host devices, and firmware part 1 can cause PC-1 232 to set the value in the MCU disable register to "1".

[0088] In response to the MCU disable register having a value of "1", the PM-1 231 can generate a clock enable signal EN-1 with a disable value of "0", as shown in 522.

[0089] In response to the clock enable signal EN-1 having a disable value of "0", the CGC-1 235 can output a constant voltage level (e.g., ground) in the gated clock signal CK-G-1, as shown in 542, regardless of transitions in the regular clock signal CK. When there are no signal transitions in the gated clock signal CK-G-1, the PC-1232 is in an idle state, reducing dynamic power consumption to save power, as shown in 513.

[0090] exist Figure 5 In the example, WC-1 includes a signal from wake-up source 0 (as shown in 550) and a signal from wake-up source 1 (as shown in 560). When the signal from wake-up source 0 has a pulse as shown in 554, PM-1 231 can clear the MCU disable register (e.g., so the MCU disable register has a value "0") and output the wake-up status, as shown in 574. In response to the MCU disable register having a value "0", PM-1 231 can generate a clock enable signal EN-1 with an enable value "1", as shown in 524.

[0091] In response to the clock enable signal EN-1 having an enable value of "1", CGC-1 235 can output a transition in the gated clock signal CK-G-1 in response to a transition in the regular clock signal CK, as shown in 544. In response to a transition in the gated clock signal CK-G-1, PC-1 232 continues operation, for example, executing firmware part 2 (FW-P2), as shown in 515. In this example, firmware part 2 (FW-P2) is associated with a wake-up state of binary "01".

[0092] Furthermore, at a certain point, for example as shown in 516, when PC-1 232 executes Firmware Part 2 (FW-P2), PC-1 waits for signals from other MCUs or host devices, and Firmware Part 2 can cause PC-1 232 to set the value in the MCU disable register to "1".

[0093] In response to the MCU disable register having a value of "1", the PM-1 231 can generate a clock enable signal EN-1 with a disable value of "0", as shown in 526.

[0094] In response to the clock enable signal EN-1 having a disable value of "0", the CGC-1 235 can output a constant voltage level (e.g., ground level) in the gated clock signal CK-G-1, regardless of transitions in the regular clock signal CK, as shown in 546. When there is no signal transition in the gated clock signal CK-G-1, the PC-1 232 is in an idle state, reducing dynamic power consumption to save power, as shown in 517.

[0095] exist Figure 5 In the example, when the signal from wake-up source 1 has a pulse as shown in 568, PM-1231 can clear the MCU disable register (e.g., then the MCU disable register has a value "0") and output the wake-up status, as shown in 578. In response to the MCU disable register having a value "0", PM-1231 can generate a clock enable signal EN-1 with an enable value "1", as shown in 528.

[0096] In response to the clock enable signal EN-1 having an enable value of "1", CGC-1 235 can output a transition in the gated clock signal CK-G-1 in response to a transition in the regular clock signal CK, as shown in 548. In response to a transition in the gated clock signal CK-G-1, PC-1 232 continues operation, for example, executing firmware part 3 (FW-P3), as shown in 519. In the example, firmware part 3 (FW-P3) is associated with a wake-up state of binary "10".

[0097] In some related examples, when processing a core wake-up, the processing core spends some processing time determining a portion of the firmware to continue operation. In contrast, the PC-1 232 can directly execute the portion of firmware associated with the wake-up state without consuming additional processing time to maintain operational continuity.

[0098] Furthermore, according to one aspect of this disclosure, using firmware-based clock gating control allows for flexible upgrades to existing firmware and the reuse of firmware modules.

[0099] Figure 6Variations from a first firmware control flow 600A to a second firmware control flow 600B are shown according to some examples of this disclosure.

[0100] The first firmware control flow 600A can be an existing firmware flow for firmware with multiple parts.

[0101] In the S610A, the first part of the firmware is executed, for example, by the processing core.

[0102] In the S620A, the processing core waits for a feedback signal.

[0103] In the S630A, the second part of the firmware is executed in response to the feedback signal.

[0104] The first firmware control flow 600A can be modified to add a clock disable judgment for firmware-based clock gating control, as shown in the second firmware control flow 600B, for example. The second firmware control flow 600B can be used in the semiconductor memory device 200.

[0105] In the S610B, the first part of the firmware is executed, for example, by the processing core PC-1 232.

[0106] In S620B, the wake-up state queue can be checked to determine whether transitions in the clock are disabled. When the wake-up state queue is empty, the second firmware control flow proceeds to S625B; when the wake-up state queue is not empty, the second firmware control flow proceeds to S630B.

[0107] In the S625B, the MCU disable register is set to the value "1". When the MCU disable register has a value "1", the polling module PM-1 231 outputs a clock enable signal EN-1 with a disabled value (e.g., "0"). Then, the clock gating circuit CGC-1235 outputs a constant voltage (e.g., ground level) in the gated clock signal CK-G-1, regardless of transitions in the regular clock signal CK.

[0108] When the wake-up source provides a signal, for example, a pulse, the polling module PM-1 231 clears the MCU disable register (e.g., with a value "0") and outputs a clock enable signal EN-1 with an enable value (e.g., "1"). The polling module PM-1 231 also queues wake-up status indicators of the wake-up source in the wake-up status queue.

[0109] In the S630B, the wake-up state is obtained from the wake-up state queue, and the second part of the firmware associated with the wake-up state is executed.

[0110] Figure 7A flowchart outlining some examples of process 700 according to this disclosure is shown. In some examples, process 700 is executed in a semiconductor device, such as by a first portion 131 of control circuitry 130 in semiconductor device 100, PM-1231 of MCU-1230 in semiconductor storage device 200, etc., for power saving. Process 700 begins at S701 and proceeds to S710.

[0111] In the S710, receive disable control. Figure 2 Taking PM-1 231 as an example, PM-1 231 receives disable control DC-1 from PC-1232. In some examples, PC-1 232 executes the first instruction to generate the disable control. For example, PC-1 232 executes the first instruction and anticipates an idle state, such as waiting for feedback signals from other MCUs or input from the host device. In response to the anticipated idle state, PC-1 232 provides the disable control to PM-1 231.

[0112] In the S720, signal transitions in the gated clock signal are disabled in response to a disable control. For example, PM-1 231 disables signal transitions in CK-G-1 in response to DC-1. CK-G-1 is used by PC-1 232. In some examples, PM-1 231 includes storage elements, such as registers (MCU disable registers), etc. The storage element can be set to a first state in response to the disable control. The clock enable signal (e.g., EN-1) of the clock gating circuit (e.g., CGC-1 235) can then be set according to the stored state in the storage element.

[0113] Note that in some examples, when a semiconductor device or semiconductor memory device includes factory setting parameters (e.g., mcu_cg_dis_read, mcu_cg_dis_pgm, mcu_cg_dis_ers, etc.) to disable clock gating, the polling module can set the clock enable signal to an enabled value based on the factory setting parameters, regardless of the disable control.

[0114] In S730, in response to wake-up control, PM-1 231 enables the signal transition in CK-G-1. In the example, in response to wake-up control, the memory element is cleared to have a second state. Then, the clock enable signal (e.g., EN-1) of the clock gating circuit (e.g., CGC-1 235) is set according to the stored state in the memory element. In some examples, wake-up control includes signals from multiple wake-up sources. The polling module PM-1 231 can then output wake-up states of the wake-up sources from the multiple wake-up sources based on priority order. In some examples, in response to the signal transition in the gating clock signal CK-G-1, PC-1232 can execute a second instruction associated with the wake-up state.

[0115] Then, the process proceeds to S799 and terminates.

[0116] Note that the semiconductor memory device 200 can be used in memory systems.

[0117] Figure 8 A block diagram of a memory system device 800 according to some examples of this disclosure is shown. The memory system device 800 includes one or more semiconductor storage devices, such as those shown by semiconductor storage devices 811-814, which are configured similarly to semiconductor storage device 200. In some examples, the memory system device 800 is a solid-state drive (solid-state drive).

[0118] The memory system device 800 includes other suitable components. For example, the memory system device 800 includes, for instance, components such as... Figure 8 The interface 801 and the main controller 802 are shown coupled together. The memory system device 800 may include a bus 820 coupling the main controller 802 to semiconductor memory devices 811-814. Furthermore, the main controller 802 is connected to the semiconductor memory devices 811-814, for example, by corresponding control lines 821-824.

[0119] Interface 801 is appropriately configured to be mechanically and electrically connected between memory system device 800 and host device, and can be used to transfer data between memory system device 800 and host device.

[0120] The main controller 802 is configured to connect the respective semiconductor memory devices 811-814 to the interface 801 for data transfer. For example, the main controller 802 is configured to provide enable / disable signals to the semiconductor memory devices 811-814 respectively to activate one or more semiconductor memory devices 811-814 for data transfer.

[0121] The main controller 802 is responsible for executing various instructions within the memory system device 800. For example, the main controller 802 can perform bad block management, error checking and correction, garbage collection, etc.

[0122] In some embodiments, a processor chip is used to implement the main controller 802. In some examples, the main controller 802 is implemented using... Figure 1 The polling module for power saving shown is implemented using the techniques illustrated. In some examples, the main controller 802 is implemented using multiple MCUs, and can be implemented using the polling module for power saving used in controller 220.

[0123] The foregoing outlines the features of several examples to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or realize the same advantages of the examples described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A storage device, comprising: A storage cell array, comprising multiple storage cells, and Peripheral circuitry, coupled to the memory cell array, includes: A clock gating circuit, coupled to a clock source and configured to output a gated clock signal based on a clock enable signal and a clock signal from the clock source; A polling module, coupled to the clock gating circuit, is configured to receive wake-up control and disable control, and to output the clock enable signal based on the wake-up control or the disable control; and A processing core coupled to the clock gating circuit and the polling module, and configured to output the disable control during operation; The clock enable signal indicates whether to output a gated clock signal with signal transition, thereby controlling whether to switch the transistors of the processing core. The gated clock signal with signal transition is generated based on the transition of the clock signal.

2. The storage device according to claim 1, wherein, The polling module is configured as follows: In response to the disable control, a clock enable signal with a disable value is output; and In response to the wake-up control, a clock enable signal with an enable value is output.

3. The storage device according to claim 2, wherein, The clock gating circuit is configured as follows: In response to the clock enable signal having an enable value, the gated clock signal with a signal transition is output; and In response to the clock enable signal with the disabled value, a gated clock signal with a constant voltage is output.

4. The storage device according to claim 1, wherein, The processing core is configured to execute a first instruction during the operation, the first instruction instructing the processing core to output the disable control.

5. The storage device according to claim 1, wherein, The peripheral circuitry also includes a storage element, which is configured to: In response to the disable control, it is in a first state; and It enters the second state in response to the wake-up control.

6. The storage device according to claim 1, wherein, The wake-up control includes signals from multiple wake-up sources; and The polling module is configured to output a wake-up status in response to signals from the plurality of wake-up sources.

7. The storage device according to claim 6, wherein, The polling module is configured to respond to signals from the plurality of wake-up sources and output the wake-up status based on priority order.

8. The storage device according to claim 7, wherein, The operation includes one of a plurality of operation types, each of which is defined with a plurality of wake-up conditions, each of which corresponds to one of the plurality of wake-up sources, and the plurality of wake-up conditions have different priorities.

9. The storage device according to claim 8, wherein, For one or more of the aforementioned operation types, the clock gating function can be selectively disabled.

10. The storage device according to claim 6, wherein, The processing core is configured to execute a second instruction associated with the wake-up state.

11. The storage device according to claim 1, wherein, The number of processing cores includes at least two, and each processing core is configured with a corresponding clock gating circuit and a corresponding polling module.

12. The storage device according to claim 2, wherein, The polling module is configured to set the clock enable signal to the enable value based on factory setting parameters, regardless of the disable control.

13. The storage device according to claim 1, wherein, The storage device includes a NAND flash memory storage device.

14. A method for a storage device, comprising: Based on wake-up control or disable control received from the processing core of the peripheral circuit, the polling module of the peripheral circuit outputs a clock enable signal to the clock gating circuit of the peripheral circuit. and Based on the clock signal and the clock enable signal, the clock gating circuit outputs a gated clock signal to the processing core, wherein the clock enable signal is configured to indicate whether to output a gated clock signal with a signal transition, thereby controlling whether to switch the transistors of the processing core, and the gated clock signal with a signal transition is generated based on the transition of the clock signal.

15. The method according to claim 14, wherein, The output of the clock enable signal includes: In response to the disable control, the polling module outputs a clock enable signal with a disable value; and In response to the wake-up control, the polling module outputs a clock enable signal with an enable value.

16. The method according to claim 15, wherein, The output of the gated clock signal includes: In response to the clock enable signal with the enable value, the clock gating circuit outputs the gated clock signal with the signal transition; and In response to the clock enable signal with a disable value, the clock gating circuit outputs a gated clock signal with a constant voltage.

17. The method of claim 14, further comprising: The processing core executes a first instruction during operation to generate the disable control.

18. The method of claim 14, further comprising: In response to the disable control, the storage element of the peripheral circuit is set to a first state; In response to the wake-up control, the storage element is set to a second state; as well as The clock gating circuit outputs the gated clock signal based on the storage element.

19. The method of claim 14, wherein, The wake-up control includes signals from multiple wake-up sources; the method further includes: In response to signals from the plurality of wake-up sources, the wake-up status is output based on priority order.

20. The method of claim 19, further comprising: The processing core executes a second instruction associated with the wake-up state.

21. A memory system device, comprising: The main controller is coupled to the storage device; as well as The storage device includes: A storage cell array, comprising multiple storage cells; and The peripheral circuitry coupled to the memory cell array includes: A clock gating circuit, coupled to a clock source and configured to output a gated clock signal based on a clock enable signal and a clock signal from the clock source; A polling module, coupled to the clock gating circuit, is configured to receive wake-up control and disable control, and to output the clock enable signal based on the wake-up control or the disable control; and A processing core coupled to the clock gating circuit and the polling module, and configured to output the disable control during operation; The clock enable signal indicates whether to output a gated clock signal with signal transition, thereby controlling whether to switch the transistors of the processing core. The gated clock signal with signal transition is generated based on the transition of the clock signal.

22. The memory system device according to claim 21, wherein, The polling module is configured as follows: In response to the disable control, a clock enable signal with a disable value is output; and In response to the wake-up control, a clock enable signal with an enable value is output.

23. The memory system device according to claim 22, wherein, The clock gating circuit is configured as follows: In response to the clock enable signal having an enable value, the gated clock signal with a signal transition is output; and In response to the clock enable signal with the disabled value, a gated clock signal with a constant voltage is output.

24. The memory system device according to claim 21, wherein, The processing core is configured to execute a first instruction during the operation, the first instruction instructing the processing core to output the disable control.

25. The memory system device according to claim 21, wherein, The peripheral circuitry includes a storage element, which is configured to: In response to the disable control, it is in a first state; and It enters the second state in response to the wake-up control.

26. The memory system device of claim 21, wherein, The wake-up control includes signals from multiple wake-up sources; and The polling module is configured to output a wake-up status in response to signals from the plurality of wake-up sources.

27. The memory system device of claim 26, wherein, The polling module is configured to respond to signals from the plurality of wake-up sources and output the wake-up status based on priority order.

28. The memory system device of claim 27, wherein, The processing core is configured to execute a second instruction associated with the wake-up state.

29. The memory system device according to claim 21, wherein, The number of processing cores includes at least two, and each processing core is configured with a corresponding clock gating circuit and a corresponding polling module.

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