Panel and method of manufacturing the same

Abstract

The application discloses a panel and a manufacturing method and device thereof. The panel has a display area and a non-display area surrounding the display area. The panel comprises: oppositely arranged array substrate and color film substrate, and sealing frame glue between the array substrate and the color film substrate in the peripheral area, which surrounds the display area. The array substrate has a plurality of pixel circuits, which are distributed at least in the display area and the area covered by the part of the sealing frame glue.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a panel and its manufacturing method and apparatus. Background Technology

[0002] In some specialized fields, there is a need to customize display products of specific sizes and shapes. However, such display products often face difficulties in mold making, long sample delivery times, or even the lack of available screens due to small demand and high costs.

[0003] Therefore, how to enable display products of various sizes or shapes to be used in a common mold has become a technical problem that urgently needs to be solved. Summary of the Invention

[0004] This invention provides a panel and its manufacturing method and apparatus to solve the aforementioned technical problems existing in the prior art.

[0005] In a first aspect, to solve the above-mentioned technical problems, embodiments of the present invention provide a panel having a display area and a non-display area surrounding the display area, the panel comprising:

[0006] An array substrate and a color filter substrate are disposed opposite to each other, and a sealing adhesive is located between the array substrate and the color filter substrate in the peripheral area, the sealing adhesive surrounding the display area;

[0007] The array substrate has multiple pixel circuits, which are distributed at least in the area covered by the display area and a portion of the sealing adhesive.

[0008] In one possible implementation, the array substrate further includes:

[0009] Multiple gate lines and multiple data lines;

[0010] At least one data driving circuit, located in the peripheral area on the side of the sealing adhesive away from the display area in the direction of extension of the data line;

[0011] At least one scan driving circuit, located on at least one side outside the sealant in the peripheral region in the direction of extension of the gate line;

[0012] The aforementioned segment is located on a different side of the display area from the data driving circuit and the scan driving circuit.

[0013] In one possible implementation, the at least one scanning drive circuit is located on one side of the sealing adhesive;

[0014] The partial section is recessed along the straight edge of the array substrate, or recessed along at least two adjacent sides of the array substrate; wherein, any one of the at least two adjacent sides includes a straight side or a curved side, and there is a right angle transition or a rounded corner transition between the two adjacent sides.

[0015] In one possible implementation, the partial segment is recessed along the edge of the horizontal zigzag line, or the partial segment is recessed along the edge of the straight line, and the partial segment is located on the opposite side from the plurality of scan drive circuits;

[0016] The centerline of at least one data driving circuit is offset from the centerline of the display area.

[0017] In one possible implementation, the array substrate has a bonding region in the peripheral region, and the array substrate further includes:

[0018] Multiple conductive silver paste dots and multiple test pads are located on the side of the bonding area away from the partial segment.

[0019] In one possible implementation, the partial segment is recessed along the edge of the straight line, and the partial segment is located on the opposite side of the at least one data driving circuit;

[0020] The centerline of the at least one data driving circuit coincides with the centerline of the display area.

[0021] In one possible implementation, the array substrate includes a plurality of scan driving circuits, which are symmetrically arranged about the sealant.

[0022] The same gate line is electrically connected to two scanning drive circuits; the two scanning drive circuits are symmetrically arranged about the sealing adhesive.

[0023] In one possible implementation, the partial section is recessed along the straight edge of the array substrate.

[0024] In one possible implementation, the panel has an irregular cutout that extends through the array substrate and the color filter substrate, and the portion of the panel is recessed at least along the edge of the irregular cutout; the irregular cutout is symmetrical about the center line of the display area, and the cutouts of the irregular cutout on the array substrate and the color filter substrate are aligned.

[0025] One possible implementation, the partial segment includes:

[0026] Two straight segments and an arc segment, the arc segment connecting the two straight segments; the straight segments extend along the extension direction of the grid line, and the arc segment is recessed along the edge of the irregular cut.

[0027] In one possible implementation, the array substrate has a bonding region in the peripheral region, and the array substrate further includes:

[0028] Multiple conductive silver paste dots are distributed on both sides of the bonding area along the extension direction of the gate line;

[0029] Multiple test pads are distributed on both sides of the bonding area in the extension direction of the gate line.

[0030] In one possible implementation, the portion of the film layer corresponding to the pixel circuit located on the side of the partial segment in the peripheral region has a break, the break extending at least through the metal film layer in the film layer and having a shape similar to that of the partial segment.

[0031] In one possible implementation, the break is located on the side of the partial segment away from the display area;

[0032] Alternatively, the break may be covered by the partial section.

[0033] In one possible implementation, the color filter substrate further includes:

[0034] Second substrate;

[0035] A black matrix is ​​located on the side of the second substrate facing the array substrate; the black matrix has openings for each pixel;

[0036] A color resist layer is located on the side of the black matrix that is away from the second substrate; the color resist in the color resist layer covers the pixel opening, and the color resist in the color resist layer is at least distributed in the display area and the partial section;

[0037] A plurality of first support pillars are located on the side of the color resist layer away from the second substrate; the plurality of first support pillars are distributed at least in the area covered by the display area and the partial segment.

[0038] In one possible implementation, a portion of the plurality of first support columns are distributed in the display area, and another portion is distributed in the peripheral area.

[0039] In one possible implementation, the first density of the first support columns distributed within the periphery is less than the second density distributed within the display area;

[0040] Alternatively, the plurality of first support columns are evenly distributed in the display area and the peripheral area.

[0041] In one possible implementation, the first density is less than the second density; the overlap width between the sealing adhesive and the first support column is greater than or equal to 1 / 2 of the width of the sealing adhesive.

[0042] In one possible implementation, the orthographic projection of the first support post onto the second substrate lies within the orthographic projection of the color resist onto the second substrate.

[0043] Alternatively, the orthographic projection of the first support post onto the second substrate lies within the orthographic projection of the black matrix onto the second substrate.

[0044] In one possible implementation, the color filter substrate further includes:

[0045] A plurality of second support pillars are located on the side of the color resist layer away from the second substrate; the plurality of second support pillars are distributed at least in the display area and the area covered by the partial segment; wherein the height of the second support pillars is less than the height of the first support pillars.

[0046] In one possible implementation, the panel further includes:

[0047] A protective adhesive is applied to the area between the cut edge of the array substrate and the partial segment.

[0048] Secondly, embodiments of the present invention provide a method for manufacturing a panel, comprising:

[0049] A primary array substrate and a primary color filter substrate are provided; the primary array substrate and the primary color filter substrate have a primary display area and a primary peripheral area surrounding the primary display area; the primary array substrate has pixel circuits uniformly distributed in the primary display area, and the primary peripheral area has no pixel circuits.

[0050] The original array substrate and the original color filter substrate are combined to obtain an original panel; wherein, the original panel includes a display area and a sealing adhesive surrounding the display area, the display area is a part of the original display area, and the pixel circuits are distributed in the area covered by a portion of the sealing adhesive.

[0051] The original panel is cut along a cutting line to change its shape or size, thus obtaining the panel; wherein the cutting line is located on the side of the partial segment away from the display area, and the shape of the cutting line is the same as the shape of the partial segment.

[0052] One possible implementation, after cutting the original panel along the cutting line, further includes:

[0053] A protective adhesive is applied between the cutting line and the partial section;

[0054] And / or, along the extension direction of the cutting line, at least the area between the cutting line and the partial segment or the area covered by the partial segment is interrupted by a metal film layer.

[0055] Thirdly, embodiments of the present invention provide an apparatus including a panel as described in the first aspect. Attached Figure Description

[0056] Figure 1 and Figure 2 A schematic diagram illustrating the fabrication of a panel according to an embodiment of the present invention;

[0057] Figure 3 A schematic diagram illustrating the fabrication of another panel provided in an embodiment of the present invention;

[0058] Figure 4 This is a schematic diagram of the structure of a primitive array substrate provided in an embodiment of the present invention;

[0059] Figure 5 The diagram shown is a schematic diagram of another cutting line provided in an embodiment of the present invention;

[0060] Figure 6 This is a schematic diagram of another original array substrate provided in an embodiment of the present invention;

[0061] Figure 7 This is a schematic diagram of another original array substrate provided in an embodiment of the present invention;

[0062] Figure 8 This is a schematic diagram of the cutting line planning of an original panel provided in an embodiment of the present invention;

[0063] Figure 9 This is a schematic diagram of another original array substrate provided in an embodiment of the present invention;

[0064] Figure 10 This is a schematic diagram showing the location of a broken line in a panel according to an embodiment of the present invention;

[0065] Figure 11 A schematic diagram of another panel provided in an embodiment of the present invention;

[0066] Figure 12 This is a schematic diagram of the structure of a primitive color filter substrate provided in an embodiment of the present invention;

[0067] Figure 13 This is a schematic diagram of another original color filter substrate provided in an embodiment of the present invention;

[0068] Figure 14 This is a schematic diagram of another original color filter substrate provided in an embodiment of the present invention;

[0069] Figure 15 and Figure 16 This is a schematic diagram of another original panel shape provided in an embodiment of the present invention;

[0070] Figure 17 A top view of a panel provided in an embodiment of the present invention;

[0071] Figures 18-20 This is a schematic diagram of the structure of an array substrate provided in an embodiment of the present invention;

[0072] Figure 21 This is a schematic diagram of another array substrate provided in an embodiment of the present invention;

[0073] Figure 22 This is a schematic diagram of another array substrate provided in an embodiment of the present invention;

[0074] Figure 23 This is a schematic diagram of another panel structure provided in an embodiment of the present invention;

[0075] Figure 24 This is a schematic diagram of another panel structure provided in an embodiment of the present invention;

[0076] Figure 25 This is a partial schematic diagram of the array substrate near the irregular area in an irregularly shaped display panel in related technologies;

[0077] Figure 26 This is a schematic diagram of another array substrate provided in an embodiment of the present invention;

[0078] Figure 27 This is a schematic diagram of the structure of a panel provided in an embodiment of the present invention;

[0079] Figure 28 This is a schematic diagram of another array substrate provided in an embodiment of the present invention;

[0080] Figure 29 This is a schematic diagram of the film layer of an array substrate provided in an embodiment of the present invention;

[0081] Figure 30 This is a partial schematic diagram of the vicinity of a physical panel interruption provided in an embodiment of the present invention;

[0082] Figure 31 This is a schematic diagram of another panel structure provided in an embodiment of the present invention;

[0083] Figure 32 Provided for embodiments of the present invention Figure 17 Cross-sectional view of the DD' position in the middle;

[0084] Figure 33 A method provided by an embodiment of the present invention Figure 17Cross-sectional view of the EE' position;

[0085] Figure 34 Another embodiment of the present invention Figure 17 Cross-sectional view of the EE' position;

[0086] Figure 35 This is a schematic diagram of another panel structure provided in an embodiment of the present invention;

[0087] Figure 36 This is a schematic diagram of another panel structure provided in an embodiment of the present invention.

[0088] Figure label:

[0089] Display area AA, peripheral area BB, bonding area CC, array substrate 1, color filter substrate 2, sealing glue 3, pixel circuit 11, partial segment 31, straight segment 311, arc segment 312, first substrate 10, second support pillar 26, irregular cut K, gate line GL, data line DL, data driving circuit COF, scan driving circuit GOA, conductive silver paste point Ag, test pad ET, protective glue 4, color resist 231, color resist layer 23, first support pillar 25, break K', black matrix 22;

[0090] Original array substrate 1', original color filter substrate 2', original display area AA', original peripheral area BB', original bonding area CC', cutting line L, break line L', second original substrate 21', original black matrix 22', original color resist layer 23', original planarization layer 24'. Detailed Implementation

[0091] This invention provides a panel and its manufacturing method and apparatus to solve the aforementioned technical problems existing in the prior art.

[0092] It should be understood that the specific structural and functional details disclosed in the embodiments of the present invention are merely representative and are intended to describe exemplary embodiments of this application. However, this application can be implemented in many alternative forms and should not be construed as being limited solely to the embodiments set forth herein.

[0093] In the description of this application, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0094] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0095] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0096] In this invention, the term "and / or" is merely a description of the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following associated objects have an "or" relationship.

[0097] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. However, the exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms describing position and direction in the present invention are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of the present invention. The accompanying drawings of the present invention are for illustrative purposes only and do not represent actual proportions.

[0098] It should be noted that specific details are set forth in the following description to provide a full understanding of the invention. However, the invention can be practiced in many ways other than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below. The following description is a preferred embodiment for carrying out the present application; however, the description is for the purpose of illustrating the general principles of the application and is not intended to limit the scope of the application. The scope of protection of this application shall be determined by the appended claims.

[0099] The following description, in conjunction with the accompanying drawings, details an embodiment of the present invention that provides a panel and its manufacturing method and apparatus.

[0100] Please see Figure 1 and Figure 2 This is a schematic diagram illustrating the fabrication of a panel according to an embodiment of the present invention. The fabrication method includes:

[0101] S11: Provide a raw array substrate 1' and a raw color filter substrate 2'; the raw array substrate 1' and the raw color filter substrate 2' have a raw display area AA' and a raw peripheral area BB' surrounding the raw display area AA'; the raw array substrate 1' has pixel circuits 11 uniformly distributed in the raw display area AA', and there are no pixel circuits 11 in the raw peripheral area BB'.

[0102] The pixel circuit 11 in the original display area AA' of the original array substrate 1' has the same structural design as the pixel circuit 11 in the prior art, but it does not have a shaped hole for placing the camera and related structures set around the edge of the shaped hole; the traces in the original peripheral area BB' do not include shaped (such as serpentine) traces set for load compensation, etc.

[0103] S12: The original array substrate 1' and the original color filter substrate 2' are combined to obtain the original panel; wherein, the original panel includes a display area AA and a sealing adhesive 3 surrounding the display area AA, the display area AA is a part of the original display area AA', and the pixel circuit 11 is distributed in the area covered by a part of the sealing adhesive 3 segment 31.

[0104] When assembling the original array substrate 1' and the original color filter substrate 2', a sealing adhesive 3 needs to be applied according to the final required panel size. A cutting line L is provided on a portion 31 of the sealing adhesive 3 on the side furthest from the display area AA. The shape of the cutting line L is similar to the shape of the portion 31, such as... Figure 1 The section 31 shown is a straight line, and the cutting line L is also a straight line. The cutting line L can be like... Figure 1 It can be set in the original surrounding area BB' as in the middle, or like Figure 2 It thus traverses the original display area AA'. During cell assembly, the liquid crystal material fills the space enclosed by the sealant 3, the original array substrate 1', and the original color filter substrate 2'.

[0105] If the original panel does not need to be cut, the original panel can be used like a normal panel by allowing the sealing adhesive 3 to surround the original display area AA'.

[0106] S13: Cut the original panel along the cutting line L to change the shape or size of the original panel and obtain the panel; wherein the cutting line L is located on the side of the partial segment 31 away from the display area AA, and the shape of the cutting line L is the same as the shape of the partial segment 31.

[0107] The cut original array substrate 1' constitutes the array substrate 1 of the panel, and the cut original color filter substrate 2' constitutes the color filter substrate 2 of the panel.

[0108] Figure 1 and Figure 2 The diagram illustrates a method of cutting the original panel to obtain a smaller-sized panel; in other embodiments, the original panel can also be cut to obtain an irregularly shaped panel, with the same manufacturing steps as described above, except that the shape of the sealing adhesive 3 and the shape of the cutting line L are changed. Please refer to... Figure 3 This is a schematic diagram illustrating the fabrication of another panel provided in an embodiment of the present invention. Figure 3 The cutting line L is arc-shaped. After cutting the original panel along the cutting line L, the resulting panel has an irregular cut K that penetrates the array substrate 1 and the color filter substrate 2.

[0109] In the embodiments provided by the present invention, when aligning the original array substrate 1' and the original color filter substrate 2', the sealing adhesive 3 is set according to the planned panel size or shape, and after alignment, the original panel is cut along the cutting line L with the same shape as a portion 31 of the sealing adhesive 3 to obtain a panel with a different shape or size than the original panel. In this way, it is not necessary to change the mask for panels of different sizes and shapes. Instead, the panel size and shape can be changed by changing the sealing adhesive 3 and cutting. Furthermore, the horizontal and vertical dimensions of the original panel can be changed. After cutting, the control timing can be changed according to the actual resolution of the panel to enable the panel to function normally, thereby reducing the mold opening cost of the panel. Even if the number of panels required is small, the mold opening cost will not increase.

[0110] Please see Figure 4 This is a schematic diagram of the structure of a primitive array substrate provided in an embodiment of the present invention.

[0111] The original array substrate 1' includes:

[0112] Multiple gate lines (GL) and multiple data lines (DL);

[0113] At least one data drive circuit COF, in the extension direction of the data line DL, the data drive circuit COF is located in the peripheral area BB on the side of the sealing glue 3 away from the display area AA;

[0114] At least one scan drive circuit GOA is located on at least one side outside the sealant 3 in the peripheral region BB, in the extension direction of the gate line GL.

[0115] like Figure 4 As shown, when the cutting line L is a straight line, the cutting line L can be in the same direction as the extension of the gate line GL or the scan line, but the cutting line L does not overlap with the scan drive circuit GOA and the data drive circuit COF. Figure 4 The two cutting lines L shown can be used to cut along one of the two cutting lines L after the box is assembled.

[0116] The tangent line L can also consist of multiple line segments, any one of which can be a straight line or a curve. Adjacent line segments can transition at a right angle or with an arc; there are no specific restrictions. Taking a horizontal zigzag line L as an example... Figure 5 The diagram shown is a schematic diagram of another cutting line provided in an embodiment of the present invention.

[0117] Please see Figure 6This is a schematic diagram of another original array substrate provided in an embodiment of the present invention. When the original array substrate 1' includes multiple scan driving circuits GOA, the multiple scan driving circuits GOA can be located on the same side of the original display area AA'; the multiple scan driving circuits GOA can also be located on opposite sides of the original display area AA' in the extension direction of the gate line GL, and the same gate line GL is electrically connected to the scan driving circuits GOA located on both sides of the original display area AA'.

[0118] By placing multiple scan drive circuits GOA on both sides of the original display area AA', and electrically connecting the two scan drive circuits GOA on both sides of the original display area AA' using the same gate line GL, these two scan drive circuits GOA can simultaneously provide scan signals to the electrically connected gate line GL. This allows the original panel to be cut into irregularly shaped panels (such as...). Figure 3 When shown, pixels in the display area AA located on both sides of the irregular cutout K can function normally.

[0119] Please see Figure 7 This is a schematic diagram of another original array substrate provided in an embodiment of the present invention. The original array substrate 1' may further include multiple scan driving circuits GOA and multiple data driving circuits COF. The multiple scan driving circuits GOA are distributed on both sides of the original display area AA'. The extension direction of the cutting line L is the same as the extension direction of the data line DL, and the cutting line L is located between two adjacent data driving circuits COF. In this way, the original panel can be cut into two small panels, improving the utilization rate of the original panel. The two small panels can be the same size or different sizes, and there is no specific limitation.

[0120] Please see Figure 8 This is a schematic diagram of the cutting line planning of an original panel provided in an embodiment of the present invention. Figure 8 The original display area AA' of the original panel is 65 inches in size, and the original display panel includes six data drive circuits (COF). If the scan drive circuits (GOA) of the original display panel are all located on one side of the original display area AA', then... Figure 8 The original panel can be cut into 5 smaller panel sizes, which is equivalent to a design of 6 panel sizes (including the original panel) using a single original array substrate 1' and color filter substrate 2. If the scanning drive circuit GOA of the original display panel is distributed on both sides of the original display area AA', the original panel can be cut into 2 smaller panels, each with 5 different sizes, which can be selected. Figure 8 Cutting can be performed using any one of the cutting lines L, or two cutting lines L can be selected. By setting multiple data driving circuits COF in the original array substrate 1', it is possible to cut an original panel into multiple panels of various sizes, which is beneficial to improving the utilization rate of the original panel.

[0121] Please see Figure 9 This is a schematic diagram of another original array substrate provided in an embodiment of the present invention. The original array substrate 1' has an original bonding region CC' in the original peripheral region BB', and the original array substrate 1' further includes:

[0122] Multiple conductive silver paste dots (Ag) and multiple test pads (ET) are symmetrically distributed on both sides of the original bonding area (CC').

[0123] If the cutting line L is as follows Figure 9 As shown, extending along the data line DL, after cutting the original panel along the cutting line L, the conductive silver paste point Ag and the test pad ET in the obtained panel are located in the original bonding area CC' (the bonding area CC of the panel after cutting).

[0124] Please see Figure 10 This is a schematic diagram showing the location of a broken line in a panel, provided as an embodiment of the present invention.

[0125] Before aligning the original array substrate 1' and the original color filter substrate 2', the metal lines in the film layer containing the pixel circuits 11 in the original array substrate 1' can be broken along the break line L' on the side where a portion 31 of the sealant 3 is located in the peripheral area BB. The metal lines include gate lines GL, data lines DL, etc. The break line L' can be covered by a portion 31 of the sealant 3, or it can be non-overlapping with a portion 31 of the sealant 3. This can prevent the final panel from exposing metal at the cut line L, causing signal defects.

[0126] Figure 10 In the process, along the extension direction of the cutting line L, at least the area between the cutting line L and a portion of the segment 31 or the area covered by a portion of the segment 31 is interrupted by the metal film layer. Alternatively, this process can be performed after cutting the original panel along the cutting line L. There are no specific restrictions.

[0127] Please see Figure 11 This is a schematic diagram of another panel provided in an embodiment of the present invention. After cutting the original panel, a protective adhesive 4 can be applied between the cutting line L and a portion 31 of the sealing adhesive 3 to wrap the cut portion of the panel. This can also prevent the final panel from exposing metal at the cutting line L, causing poor signal transmission. For example, when the break line L' is located in the area between the cutting line L and a portion 31 of the sealing adhesive 3, it is also necessary to apply adhesive along the break line L', such as a protective adhesive 4. Of course, when the break line L' is covered by a portion 31 of the sealing adhesive, a protective adhesive 4 can also be applied between the cutting line L and a portion 31 of the sealing adhesive 3.

[0128] In other embodiments, it is also possible Figure 10 and Figure 11The solutions described above all use this method, which can better prevent the final panel from having exposed metal at the cut line L position, causing poor signal quality.

[0129] Please see Figure 12 This is a schematic diagram of the structure of a primitive color filter substrate provided in an embodiment of the present invention.

[0130] The original color filter substrate 2' includes:

[0131] Second original substrate 21';

[0132] The original black matrix 22' is located on one side of the second original substrate 21'; the original black matrix 22' has multiple pixel openings;

[0133] The original color resist layer 23' is located on the side of the original black matrix 22' away from the second original substrate 21'; the original color resist layer 23' includes a plurality of color resists 231 located at least in the original display area AA', and the color resists 231 cover the pixel openings of the original black matrix 22'.

[0134] The original planarization layer 24' is located on the side of the original color resist layer 23' away from the second original substrate 21';

[0135] The first support pillar 25 is located on the side of the original planarization layer 24' away from the substrate, at least in the original display area AA'.

[0136] Figure 12 The first support column 25 is located in the display area AA, but in this way... Figures 1-3 In the original panel formed after the original array substrate 1' and the original color filter substrate 2' are assembled, the sealant 3 is usually doped with silicon balls as support. Since a portion 31 of the sealant 3 is located within the original display area AA', the first support pillar 25 of the original display area AA' is used as the support in the portion 31 of the sealant 3, while the silicon balls are used as the support in the portion outside the portion 31 of the sealant 3. This will result in a difference in strength between the portion 31 of the sealant 3 and the support outside the portion 31, which in turn causes the display area AA in the panel obtained by cutting the original panel to turn yellow near the portion 31.

[0137] Please see Figure 13 This is a schematic diagram of another original color filter substrate provided in an embodiment of the present invention. The first support pillar 25 is located between the original display area AA' and the original peripheral area BB'. In this manner... Figures 1-3In the original panel formed after the original array substrate 1' and the original color filter substrate 2' are assembled, the sealing adhesive 3 in the original panel, whether in part of section 31 or in part of section 31, is supported by the first support pillar 25 to support the thickness of the box. Therefore, the support strength of the entire area covered by the sealing adhesive 3 is the same, which can prevent the display area AA in the panel obtained by cutting the original panel from yellowing near part of section 31.

[0138] It is necessary to understand that Figure 13 Due to page size limitations, only one first support pillar 25 in the original peripheral area BB' is shown. However, this does not represent the actual number and distribution of first support pillars 25 in the original peripheral area BB'. In actual applications, the original peripheral area BB' actually includes more first support pillars 25.

[0139] Please see Figure 14 This is a schematic diagram of another original color filter substrate provided in an embodiment of the present invention. The color resist 231 is uniformly distributed in the original display area AA' and the original peripheral area BB'. This allows the film thickness between the first support pillar 25 and the second original substrate 21' in the original display area AA' and the original peripheral area BB' to be consistent. This makes the first support pillar 25 located in the original display area AA' and the original peripheral area BB' set on the same plane, thereby improving the uniformity of the cell thickness of the original panel obtained by cell assembly in the original display area AA' and the original peripheral area BB'.

[0140] Please see Figure 15 and Figure 16 This is a schematic diagram of another original panel shape provided in an embodiment of the present invention. The original panel shape can also be as follows: Figure 15 The hexagon shown, along Figure 15 The horizontal cutting line L shown can be used to cut the original panel to obtain square or rectangular panels. Figure 15 The longitudinal cutting line L shown can be used to cut the original panel to obtain other irregularly shaped panels; the original panel can also have the following shape. Figure 16 The arch shown, along Figure 16 The horizontal cutting line L shown can be used to cut the original panel to obtain square or rectangular panels. Figure 16 The longitudinal cutting line L shown can be used to cut the original panel to obtain other irregularly shaped panels.

[0141] Furthermore, when the original panel is used as a non-display panel (such as dimming glass, dimming glasses, etc.), the shape of the original panel can be any shape, without any specific restrictions.

[0142] Please see Figure 17 This invention provides a top view of a panel, which has a display area AA and a peripheral area BB surrounding the display area AA. The panel includes:

[0143] An array substrate 1 and a color filter substrate 2 are arranged opposite to each other, and a sealing adhesive 3 is located between the array substrate 1 and the color filter substrate 2 in the peripheral area BB, with the sealing adhesive 3 surrounding the display area AA;

[0144] The array substrate 1 has multiple pixel circuits 11, which are distributed at least in the area covered by the display area AA and a portion 31 of the sealing adhesive 3.

[0145] like Figure 17 As shown, the pixel circuit 11 is not only distributed in the display area AA, but also in the area covered by a portion 31 of the sealing adhesive 3; the pixel circuit 11 can also be as follows Figure 2 As shown in the panel, the distribution extends not only to the display area AA but also to the peripheral area BB on the side where the sealing adhesive 3 section 31 is located. This allows for... Figures 1-3 As shown in the panel manufacturing method, when forming the original panel with the box, the shape and size of the sealing adhesive 3 are planned according to the final required panel shape and size. A portion 31 of the sealing adhesive 3 is located in the original display area AA' of the original panel. This ensures that multiple pixel circuits in the panel are distributed in the display area AA of the final panel and the area covered by the portion 31 of the sealing adhesive 3. This allows panels of various sizes to share the original panel, improves panel sampling efficiency, and reduces panel production costs.

[0146] Please see Figures 18-20 This is a schematic diagram of an array substrate provided in an embodiment of the present invention. The array substrate 1 further includes:

[0147] Multiple gate lines (GL) and multiple data lines (DL);

[0148] At least one data drive circuit COF is located in the peripheral area BB on the side of the sealing glue 3 away from the display area AA in the extension direction of the data line DL. The data drive circuit COF can support adjustable resolution. After the corresponding original panel is cut into panels of different sizes, the resolution supported by the data drive circuit COF can be adjusted according to the actual size of the panel so that the panel can be displayed normally.

[0149] At least one scan drive circuit GOA, in the extension direction of the gate line GL, is located on at least one side outside the sealant 3 in the peripheral region BB;

[0150] Section 31 is located on a different side of the display area AA from the data driving circuit COF and the scan driving circuit GOA.

[0151] Figure 18 It is along Figure 4 The array substrate 1 is obtained in the panel after the original array substrate 1' is cut by the transverse cutting line L.

[0152] Figure 19 It is along Figure 4 The array substrate 1 is obtained in the panel after the original array substrate 1' is cut by the longitudinal cutting line L.

[0153] Figure 20 They are respectively along Figure 4 The original array substrate 1' is cut by two straight cutting lines L, or along... Figure 5 The original array substrate 1' was obtained by cutting the horizontal zigzag cutting line L.

[0154] Since the area covered by the partial section 31 of the sealing adhesive 3 contains pixel circuits 11, it can be determined that the cutting position of the array substrate 1 is located on the side of the partial section 31 away from the display area AA. Therefore, by placing the partial section 31, the data driving circuit COF, and the scan driving circuit GOA on different sides of the display area AA, it can be ensured that the scan driving circuit GOA and the data driving circuit COF in the panel will not be damaged due to cutting, so that the panel retains its driving function.

[0155] It is necessary to understand that Figures 18-20 To facilitate observation of the positional relationship between the partial section 31 and the data driving circuit COF, the scanning driving circuit GOA, and the display area AA, the orthographic projection position of the sealing adhesive 3 on the array substrate 1 is shown. It should not be understood that the sealing adhesive 3 is a component of the array substrate 1.

[0156] like Figure 18 and Figure 19 As shown, at least one scanning drive circuit GOA is located on one side of the sealing adhesive 3;

[0157] like Figure 18 The portion 31 shown is recessed along the straight edge of the array substrate 1, or as... Figure 19 The shown section 31 is recessed along at least two adjacent sides of the array substrate 1; wherein, any one of the at least two adjacent sides includes a straight side or a curved side, and there is a right angle transition or a rounded corner transition between the two adjacent sides. Figure 19 The two adjacent sides shown are both straight lines. These two adjacent sides can be as follows: Figure 19 The right-angle transition shown can also be a rounded corner transition. One of the two adjacent sides can be a curve, or both adjacent sides can be curves. There are no specific restrictions.

[0158] In some sections of section 31, besides... Figure 19 The section 31 is recessed along two adjacent sides of the array substrate 1. If the array substrate is hexagonal, some sections 31 can also be set along three or four adjacent sides of the array substrate 1. There are no specific restrictions.

[0159] By recessing a portion of the segment 31 along the straight edge of the array substrate 1, or recessing it along at least two adjacent edges of the array substrate 1, space can be reserved for the frame of the panel.

[0160] Please see Figure 19 and Figure 20 Some sections 31 are recessed along the edge of the horizontal zigzag line, or some sections 31 are recessed along the edge of the straight line, and some sections 31 are located on the other side opposite to the multiple scan drive circuits GOA;

[0161] At least one data drive circuit COF has its O2O'2 center line offset from the center line O1O'1 of the display area AA.

[0162] like Figure 18 As shown, a portion of segment 31 is recessed along a straight edge, and a portion of segment 31 is located on the opposite side of at least one data drive circuit COF;

[0163] The center line of at least one data drive circuit COF coincides with the center line of the display area AA.

[0164] Please see Figure 21 This is a schematic diagram of another array substrate provided in an embodiment of the present invention. The array substrate 1 has a bonding region CC in the peripheral region BB, and the array substrate 1 further includes:

[0165] Multiple conductive silver paste dots Ag and multiple test pads ET are located on the side of the bonding area CC away from part of segment 31.

[0166] Figure 21 It is along Figure 9 The array substrate 1 in the panel is obtained by cutting the original panel with the middle cutting line L.

[0167] By setting multiple conductive silver paste dots Ag and multiple test pads ET on the side of the bonding area CC of the array substrate 1 away from the partial section 31, the array substrate 1 can use the conductive silver paste dots Ag for anti-static purposes and the test pads ET for testing.

[0168] Please see Figure 22 This is a schematic diagram of another array substrate provided in an embodiment of the present invention.

[0169] The array substrate 1 includes multiple scan drive circuits (GOAs), which are symmetrically arranged about the sealant 3.

[0170] The same grid line GL is electrically connected to two scan drive circuits GOA; the two scan drive circuits GOA are symmetrically arranged about the sealing glue 3.

[0171] By symmetrically arranging multiple scan drive circuits GOA about the sealing adhesive 3, and electrically connecting two scan drive circuits GOA symmetrically arranged about the sealing adhesive 3 to the same gate line GL, the two scan drive circuits GOA can simultaneously provide scan signals to the same gate line GL, thereby improving the driving capability of the panel.

[0172] like Figure 22 As shown, a portion of section 31 is recessed along the straight edge of the array substrate 1.

[0173] Please see Figure 23 This is a schematic diagram of another panel structure provided in an embodiment of the present invention. The panel has an irregular cutout K that penetrates the array substrate 1 and the color filter substrate 2. A portion of the segment 31 is recessed at least along the edge of the irregular cutout K. The irregular cutout K is symmetrical about the center line O1O'1 of the display area AA. The cutouts of the irregular cutout K on the array substrate and the color filter substrate are aligned.

[0174] If according to Figure 3 By manufacturing the panel in this way, an irregular panel with an irregular cutout K can be obtained. Components such as cameras can be placed in the irregular cutout K. When the irregular panel is the panel of a display screen, the display screen can be a notch screen, an irregular screen, etc.

[0175] Figure 3 The cutting line L is set along the edge of the irregular cut K, therefore a portion 31 of the sealing adhesive 3 is recessed along the edge of the irregular cut K.

[0176] If you press first Figure 2 Cut the original panel in the following way, and then... Figure 3 The original panel was cut again using a method described above, and the structural diagram of the resulting panel is shown in the figure. Figure 24 The diagram shown is a schematic representation of another panel structure provided in an embodiment of the present invention. In this case, a portion 31 consists of two straight segments 311 and an arc segment 312, with the arc segment 312 connecting the two straight segments 311. The straight segments 311 extend along the extension direction of the grid line GL, and the arc segment 312 is recessed along the edge of the irregular cut K. That is, in the panel obtained using the above cutting scheme, a portion 31 of the sealing adhesive 3 is not only recessed along the edge of the irregular cut K, but also recessed along the straight edges on both sides of the irregular cut K.

[0177] In addition, to obtain Figure 24 The panel shown can be used first. Figure 2 Cut the original panel in the following way and then press Figure 3 In addition to re-cutting the original panel after it has been cut, you can also... Figure 2 and Figure 3 The two cutting lines L merge into one with Figure 24The middle section 31 has a similarly shaped cutting line L, which cuts the original panel once to obtain... Figure 24 The panel shown.

[0178] In the embodiments provided by the present invention, by setting an irregular cutout K through the array substrate 1 and the color filter substrate 2 in the panel, and setting a portion of the section 31 at least along the edge of the irregular cutout K, it can effectively support and protect the periphery of the irregular cutout K, and also set a camera in the irregular cutout K, which makes it easy to make the original panel irregular and smaller.

[0179] Please see Figure 25 This is a partial schematic diagram of the array substrate near the irregular area in an irregularly shaped display panel in related technologies.

[0180] In related technologies, a sealing adhesive 3 is provided around the irregularly shaped area, and a wiring area is provided on the side of the sealing adhesive 3 away from the irregularly shaped area. The wiring area typically contains wiring for the gate line GL layer. A load compensation area is provided on the side of the wiring area away from the irregularly shaped area, and a display area AA is provided on the side of the load compensation area away from the irregularly shaped area. However, in the embodiment provided by this invention, a section 31 of the sealing adhesive 3 away from the irregularly shaped cutout K is not provided with a wiring area like... Figure 25 The wiring area and load compensation area shown in the diagram ensure that even if the original panel is cut along the GL direction, the resulting panel can still function normally. For example, if the panel is a display panel, it can perform normal display functions.

[0181] Please see Figure 26 A schematic diagram of another array substrate provided in an embodiment of the present invention.

[0182] The array substrate 1 has a bonding region CC in the peripheral region BB, and the array substrate 1 further includes:

[0183] Multiple conductive silver paste dots Ag are distributed on both sides of the bonding region CC in the extension direction of the gate line GL;

[0184] Multiple test pads ET are distributed on both sides of the bonding area CC in the extension direction of the gate line GL.

[0185] Since a portion 31 of the sealing adhesive 3 is located on the side of the display area AA away from the data driving circuit COF, the panel obtained after cutting the original panel retains multiple conductive silver paste points Ag and multiple test pads ET that are symmetrically arranged about the bonding area CC in the original panel. The multiple conductive silver paste points Ag can be used to improve the anti-static effect of the array substrate 1, and the multiple test pads ET can also be used to test the array substrate 1.

[0186] In addition, Figure 26 Outside the array substrate 1 shown, the relative positional relationship between certain segments 31 and the data driving circuit COF is as follows: Figure 26 In the same array substrate 1, the relative positions of multiple conductive silver paste dots Ag and multiple test pads ET to the bonding area CC are as follows: Figure 26 Similarly, I will not go into detail here.

[0187] Please see Figure 27 This is a schematic diagram of the structure of a panel provided in an embodiment of the present invention.

[0188] The portion of the film layer corresponding to the pixel circuit 11 located on the side of the partial segment 31 in the peripheral region BB has a break K', the break K' at least penetrates the metal film layer in the film layer, and is similar in shape to the partial segment 31.

[0189] The fracture surface K' can be as follows Figure 27 That way, it can be partially covered by segment 31, and it can also be like Figure 28 In this way, the break point K' is set on the side of the partial section 31 away from the display area AA, and the break point K' is covered by protective glue 4. Figure 28 This is a schematic diagram of another array substrate provided in an embodiment of the present invention. The array substrate 1 further includes a first substrate 10, and the film layer corresponding to the pixel circuit 11 is located on the side of the first substrate 10 facing the color filter substrate 2.

[0190] In the embodiments provided by the present invention, by setting a break K' in the portion of the film layer corresponding to the pixel circuit 11 located on the side of the partial segment 31 in the peripheral region BB domain, and making the break K' penetrate through the thickness direction of the film layer corresponding to the pixel circuit 11 and similar in shape to the partial segment 31, and by covering the break K' with the sealing glue 3 or protective glue 4, the metal wire in the pixel circuit 11 can be broken, preventing the panel from having poor signal due to the exposed metal wire at the cutting position.

[0191] Please continue reading Figure 27 The distance d1 between the cut edge L” of the array substrate 1 and the partial segment 31 ranges from 50µm to 200µm. This prevents damage to the sealant 3 when the break K’ is located on the side of the sealant 3 away from the display area AA. The width W1 of the break K’ ranges from 50µm to 100µm. When the break K’ overlaps with the partial segment 31 of the sealant 3, the distance d2 between the break K’ and the outer edge of the sealant 3 ranges from 50µm to 200µm. This prevents the formation of the break K’ from affecting the liquid crystal layer and the color filter substrate 2. The width W2 of the sealant 3 ranges from 500µm to 1000µm.

[0192] Please see Figure 29 This is a schematic diagram of the film layers of an array substrate provided in an embodiment of the present invention. The array substrate 1 includes:

[0193] First substrate 10;

[0194] The gate layer Gtae is located on one side of the first substrate 10;

[0195] The active layer Act is located on the side of the gate layer Gtae away from the first substrate 10;

[0196] The source / drain layer SD is located on the side of the active layer Act that is away from the first substrate 10;

[0197] An insulating layer PVX is located on the side of the source / drain layer SD away from the first substrate 10;

[0198] The electrode layer ITO is located on the side of the insulating layer PVX away from the first substrate 10;

[0199] The alignment film layer PI is located on the side of the electrode layer ITO away from the first substrate 10.

[0200] The film layers corresponding to pixel circuit 11 include gate layer Gtae, active layer Act, source / drain layer SD, insulating layer PVX, and electrode layer ITO.

[0201] Please see Figure 30 This is a partial schematic diagram of the area near the break point of a physical panel, provided as an embodiment of the present invention. Figure 30 The diagram shows a metal line in one of the metal layers of the pixel circuit 11 on the array substrate 1. By using a laser to break at least the metal film layer corresponding to the pixel circuit 11, the metal lines in each metal film layer can be broken.

[0202] Please see Figure 31 This is a schematic diagram of another panel structure provided in an embodiment of the present invention. The panel further includes:

[0203] Protective adhesive 4 covers the area between the cut edge L” of the array substrate 1 and a portion of segment 31.

[0204] In the embodiments provided by the present invention, by providing protective adhesive 4 in the area between the cut edge L” and the partial section 31 of the array substrate 1, the panel can be prevented from having poor signal due to exposed metal lines at the cut edge L”.

[0205] also, Figure 31 Protective adhesive 4 and Figure 27 or Figure 28 The break K' in the middle can exist at the same time, which can further prevent the panel from having poor signal due to the exposed metal line at the cut edge L”.

[0206] Please see Figure 32 and Figure 33 , Figure 32 Provided for embodiments of the present invention Figure 17 Cross-sectional view at position DD' in the middle. Figure 33 A method provided by an embodiment of the present invention Figure 17 Cross-sectional view of the EE' position.

[0207] Color filter substrate 2 also includes:

[0208] Second substrate 21;

[0209] The black matrix 22 is located on the side of the second substrate 21 facing the array substrate 1; the black matrix 22 has multiple pixel openings, which are distributed at least in the display area and some sections.

[0210] Color resist layer 23 is located on the side of black matrix 22 away from second substrate 21; color resist 231 in color resist layer 23 covers pixel openings in black matrix 22, and color resist 231 in color resist layer 23 is distributed at least in display area AA and part of section 31.

[0211] Multiple first support pillars 25 are located on the side of the color resist layer 23 away from the second substrate 21; the multiple first support pillars 25 are distributed at least in the area covered by the display area AA and part of the segment 31.

[0212] like Figure 32 As shown, due to the portion 31 of the sealing adhesive 3 being located in Figure 1 In the original display area AA' of the original panel, a portion of segment 31 covers part of the first support pillar 25, part of the pixel openings of the black matrix 22, and the color resist 231. Figure 33 The sealing adhesive 3 in the middle refers to the part outside of section 31, which is located in Figure 1 The original peripheral area BB' of the original panel is doped with silicon spheres in the part outside section 31 of the sealing glue 3.

[0213] However, since part of the sealing adhesive 31 covers the first support pillar 25, and the part of the sealing adhesive 3 other than part of the sealing adhesive 31 is doped with silicon balls, the supporting strength of part of the sealing adhesive 31 is different from that of the part of the sealing adhesive 3 other than part of the sealing adhesive 3. This will lead to the risk of yellowing of the panel near part of the sealing adhesive 31.

[0214] Please see Figure 34 Another embodiment of the present invention Figure 17 Cross-sectional view of the EE' position.

[0215] A portion of the multiple first support columns 25 are distributed in the display area AA, and another portion is distributed in the peripheral area BB.

[0216] By distributing a portion of the multiple first support pillars 25 in the display area AA and another portion in the peripheral area BB, the first support pillars 25 can also be distributed in some areas of the sealing adhesive 3, except for some sections 31. This allows some sections 31 of the sealing adhesive 3 to have the same support strength as the parts outside of some sections 31, thereby improving the problem of yellowing of the panel near some sections 31 and ensuring uniform thickness of the display area AA and the peripheral area BB. In addition, it can also provide support for the area near the cutting line L when cutting the original panel, making cutting easier.

[0217] In some embodiments, the first density of the first support pillars 25 distributed in the periphery is less than the second density distributed in the display area AA, so as to meet the support requirements of the display panel in the display area AA and the peripheral area BB.

[0218] Please continue reading Figure 34 The overlap width W3 between the sealing adhesive 3 and the first support column 25 is greater than or equal to 1 / 2 of the width W2 of the sealing adhesive 3. This ensures the support strength of the first support column 25 for the perimeter area BB of the panel. The corresponding value range of the first density is (1 / 4 to 1 / 2) times the second density.

[0219] In other embodiments, a plurality of first support columns 25 are evenly distributed in the display area AA and the peripheral area BB, which can accommodate the support requirements of non-display panels for the display area AA and the peripheral area BB.

[0220] Please see Figure 35 This is a schematic diagram of another panel structure provided in an embodiment of the present invention.

[0221] Color resist layer 23 has color resist 231 in both the display area AA and the peripheral area BB, which can ensure that the cell thickness of the display area AA and the peripheral area BB is consistent and improve the uniformity of cell thickness.

[0222] Please see Figure 36 This is a schematic diagram of another panel structure provided in an embodiment of the present invention. The color filter substrate 2 further includes:

[0223] Multiple second support pillars 26 are located on the side of the color resist layer 23 away from the second substrate 21; the multiple second support pillars 26 are distributed at least in the area covered by the display area AA and part of the segment 31; wherein the height of the second support pillars 26 is less than the height of the first support pillar 25.

[0224] Typically, the distribution area of ​​the second support column 26 is the same as that of the first support column 25. For example, if the first support column 25 is distributed in the area covered by the display area AA and a portion 31 of the sealing adhesive 3, the second support column 26 is also distributed in the area covered by the display area AA and a portion 31 of the sealing adhesive 3; or if the first support column 25 is distributed in the area covered by the display area AA and the peripheral area BB, the second support column 26 is also distributed in the area covered by the display area AA and the peripheral area BB.

[0225] The first support pillar 25 and the second support pillar 26 can be located within the orthographic projection of the color resist 231 on the second substrate, or within the orthographic projection of the black matrix 22 on the second substrate, without any specific limitation.

[0226] The panel provided by this invention can be a display panel or a non-display panel.

[0227] The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a micro light-emitting diode (Micro LED) display panel, etc., and this invention does not specifically limit it.

[0228] Non-display panels include eyeglass panels, car window panels, and other products involving dimming glass technology.

[0229] Based on the same inventive concept, embodiments of the present invention provide an apparatus that includes a panel as described above.

[0230] The device can be a display device or a non-display device.

[0231] The display device can be a liquid crystal display (LCD), a liquid crystal screen, an LCD TV, or other display devices, or a mobile device such as a mobile phone, tablet computer, laptop, personal digital assistant (PDA), or in-vehicle computer. The display device includes a frame, a display panel housed within the frame, a circuit board, a display driver IC, and other electronic components.

[0232] Non-display devices can be products involving dimming glass technology, such as eyeglasses and smart car windows.

[0233] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0234] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A panel having a display area and a peripheral area surrounding the display area, characterized in that, include: An array substrate and a color filter substrate are disposed opposite to each other, and a sealing adhesive is located between the array substrate and the color filter substrate in the peripheral area, the sealing adhesive surrounding the display area; The array substrate has multiple pixel circuits, multiple data lines, and at least one data driving circuit. The multiple pixel circuits are distributed at least in the display area and the area covered by a portion of the sealing adhesive. The data lines are connected to the corresponding column of pixel circuits. In the extension direction of the data lines, the data driving circuit is located in the peripheral area on the side of the sealing adhesive away from the display area. The portion of the sealing adhesive and the data driving circuit are located on different sides of the display area. The film layer corresponding to the pixel circuit has a break in the portion of the peripheral region located on the side where the partial segment is located. The break at least penetrates the metal film layer in the film layer and is similar in shape to the partial segment. The portion of the data line located on the side of the break closer to the display area is electrically connected to the corresponding data driving circuit.

2. The panel as claimed in claim 1, characterized in that, The array substrate further includes: Multiple grid lines; At least one scan driving circuit, located on at least one side outside the sealant in the peripheral region in the direction of extension of the gate line; The portion of the area is located on a different side of the display area from the scanning drive circuit.

3. The panel as described in claim 2, characterized in that, The at least one scanning drive circuit is located on one side of the sealing adhesive; The partial section is recessed along the straight edge of the array substrate, or recessed along at least two adjacent sides of the array substrate; wherein, any one of the at least two adjacent sides includes a straight side or a curved side, and there is a right angle transition or a rounded corner transition between the two adjacent sides.

4. The panel as described in claim 3, characterized in that, The partial segment is recessed along the edge of the curve, or the partial segment is recessed along the edge of the straight line, and the partial segment is located on the opposite side to the plurality of scanning drive circuits; The centerline of at least one data driving circuit is offset from the centerline of the display area.

5. The panel as described in claim 4, characterized in that, The array substrate has a bonding region in the peripheral region, and the array substrate further includes: Multiple conductive silver paste dots and multiple test pads are located on the side of the bonding area away from the partial segment.

6. The panel as claimed in claim 3, characterized in that, The partial segment is recessed along the edge of the straight line, and the partial segment is located on the opposite side of the at least one data driving circuit; The centerline of the at least one data driving circuit coincides with the centerline of the display area.

7. The panel as claimed in claim 2, characterized in that, The array substrate includes multiple scanning drive circuits, which are symmetrically arranged about the sealant. The same gate line is electrically connected to two scanning drive circuits; the two scanning drive circuits are symmetrically arranged about the sealing adhesive.

8. The panel as claimed in claim 7, characterized in that, The aforementioned sections are recessed along the straight edge of the array substrate.

9. The panel as claimed in claim 7, characterized in that, The panel has an irregular cutout that penetrates the array substrate and the color filter substrate, and the portion of the panel is recessed at least along the edge of the irregular cutout; the irregular cutout is symmetrical about the center line of the display area, and the cutouts of the irregular cutout on the array substrate and the color filter substrate are aligned.

10. The panel as claimed in claim 9, characterized in that, The aforementioned section includes: Two straight segments and an arc segment, the arc segment connecting the two straight segments; the straight segments extend along the extension direction of the grid line, and the arc segment is recessed along the edge of the irregular cut.

11. The panel as claimed in any one of claims 6-10, characterized in that, The array substrate has a bonding region in the peripheral region, and the array substrate further includes: Multiple conductive silver paste dots are distributed on both sides of the bonding area along the extension direction of the gate line; Multiple test pads are distributed on both sides of the bonding area in the extension direction of the gate line.

12. The panel as claimed in any one of claims 1-10, characterized in that, The break is located on the side of the partial section away from the display area; Alternatively, the break may be covered by the partial section.

13. The panel as claimed in any one of claims 1-10, characterized in that, The color filter substrate further includes: Second substrate; A black matrix is ​​located on the side of the second substrate facing the array substrate; the black matrix has multiple pixel openings; A color resist layer is located on the side of the black matrix away from the second substrate; the color resist in the color resist layer covers the pixel opening, and the color resist in the color resist layer is at least distributed in the display area and the partial section; A plurality of first support pillars are located on the side of the color resist layer away from the second substrate; the plurality of first support pillars are distributed at least in the area covered by the display area and the partial segment.

14. The panel as claimed in claim 13, characterized in that, A portion of the plurality of first support columns are distributed in the display area, and another portion is distributed in the peripheral area.

15. The panel as claimed in claim 14, characterized in that, The first density of the first support column distributed in the periphery is less than the second density distributed in the display area; Alternatively, the plurality of first support columns are evenly distributed in the display area and the peripheral area.

16. The panel as claimed in claim 15, characterized in that, The first density is less than the second density; the overlap width between the sealing adhesive and the first support column is greater than or equal to 1 / 2 of the width of the sealing adhesive.

17. The panel as claimed in claim 13, characterized in that, The orthographic projection of the first support post onto the second substrate lies within the orthographic projection of the color resist onto the second substrate. Alternatively, the orthographic projection of the first support post onto the second substrate lies within the orthographic projection of the black matrix onto the second substrate.

18. The panel as claimed in claim 13, characterized in that, The color filter substrate further includes: A plurality of second support pillars are located on the side of the color resist layer away from the second substrate; the plurality of second support pillars are distributed at least in the display area and the area covered by the partial segment; wherein the height of the second support pillars is less than the height of the first support pillars.

19. The panel as claimed in any one of claims 1-10, characterized in that, The panel also includes: A protective adhesive is applied to the area between the cut edge of the array substrate and the partial segment.

20. A method for manufacturing a panel, characterized in that, include: Provide a raw array substrate and a raw color filter substrate; The original array substrate and the original color filter substrate have an original display area and an original peripheral area surrounding the original display area; the original array substrate has pixel circuits, multiple data lines and at least one data driving circuit uniformly distributed in the original display area, the data lines are connected to the pixel circuits of the corresponding column, and there are no pixel circuits in the original peripheral area. The original array substrate and the original color filter substrate are combined to obtain an original panel; wherein, the original panel includes a display area and a sealing adhesive surrounding the display area, the display area is a part of the original display area, and the pixel circuits are distributed in the area covered by a portion of the sealing adhesive within the original display area. The original panel is cut along a cutting line to change its shape or size, thus obtaining the panel; wherein the cutting line is located on the side of the partial segment away from the display area, and the shape of the cutting line is the same as the shape of the partial segment; in the extension direction of the data line, the data driving circuit is located in the peripheral area on the side of the sealing glue away from the display area; the partial segment and the data driving circuit are located on different sides of the display area; Along the extension direction of the cutting line, at least the area between the cutting line and the partial segment or the area covered by the partial segment is broken by a metal film layer, forming a break in the film layer corresponding to the pixel circuit on the side of the partial segment in the peripheral area. The break at least penetrates the metal film layer in the film layer and is similar in shape to the partial segment. The portion of the data line located on the side of the break closer to the display area is electrically connected to the corresponding data driving circuit.

21. The manufacturing method as described in claim 20, characterized in that, After cutting the original panel along the cutting line, the process further includes: A protective adhesive is applied between the cutting line and the partial section.

22. An apparatus, characterized in that, Includes the panel as described in any one of claims 1-19.

Images