Manufacturing methods for three-dimensional semiconductor devices

Abstract

This invention discloses a method for manufacturing a three-dimensional semiconductor device, comprising the steps of: providing a first wafer, wherein a first surface of the first wafer has a plurality of recesses; bonding a plurality of first chips within the plurality of recesses, wherein a first gap exists between two adjacent first chips; filling the first gap and planarizing the first surface; forming at least one first metal interconnect structure on the first surface to form a first chip assembly wafer; bonding the first chip assembly wafer to at least one second metal interconnect structure on a second surface of a second wafer via the first metal interconnect structure; thinning the back surface of the first chip assembly wafer and forming a plurality of vias extending to the first metal interconnect structure within the first gap; depositing a passivation layer and forming a redistribution layer on the thinned back surface; wherein the first metal interconnect structure forms an electrical connection structure with the redistribution layer through the plurality of vias.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a three-dimensional semiconductor device, and more particularly to a method for manufacturing a three-dimensional semiconductor device capable of achieving high-density interconnection between chip components. Background Technology

[0002] Traditional chip packaging is typically planar, with interconnections between chips achieved through wire bonding. In this configuration, a significant amount of power required for chip computation is wasted during data transmission. Therefore, a three-dimensional stacking method allows for vertical interconnection of chips or wafers with different functions, thereby shortening data transmission distances, increasing bandwidth, saving energy and cost, and improving computational efficiency.

[0003] Currently, common 3D integration methods include wafer-to-wafer, die-to-die, and die-to-wafer. Wafer-to-wafer integration offers high alignment accuracy but struggles with heterogeneous integration, while die-to-wafer integration enables heterogeneous integration but suffers from low alignment accuracy. Hybrid bonding processes, on the other hand, are difficult to implement for achieving high-density interconnects.

[0004] Therefore, it is necessary to provide a method for manufacturing three-dimensional semiconductor devices to solve the problems existing in the prior art. Summary of the Invention

[0005] The main objective of this invention is to provide a method for manufacturing a three-dimensional semiconductor device. First, a chip is fused to a wafer to encapsulate at least one small chip component in a carrier wafer. Then, wafer-to-wafer bonding is performed to achieve high-density interconnection between the small chip component and the logic chip.

[0006] To achieve the above objectives, an embodiment of the present invention provides a method for manufacturing a three-dimensional semiconductor device, characterized in that the manufacturing method includes the following steps:

[0007] (a) A first wafer is provided, wherein a first surface of the first wafer has at least one recess;

[0008] (b) A plurality of first chips are bonded in the recess, wherein there is a first gap between two adjacent first chips;

[0009] (c) Fill the first gap and flatten the first surface;

[0010] (d) Forming at least one first metal interconnect structure on the first surface to form a first chip assembly wafer;

[0011] (e) Bonding at least one second metal interconnect structure on a second surface of a second wafer to the first chip assembly wafer via the first metal interconnect structure;

[0012] (f) After thinning a back surface of the first chip assembly wafer, a plurality of through holes extending to the first metal interconnect structure are formed in the first gap, wherein the back surface and the first surface are opposite to each other.

[0013] (g) A passivation layer is deposited on the thinned back surface and a redistribution layer is formed;

[0014] (h) Forming multiple pad openings on the passivation layer;

[0015] The first metal interconnect structure forms an electrical connection structure with the redistribution layer through the plurality of vias.

[0016] In one embodiment of the present invention, the first wafer is a silicon / insulator / silicon multilayer structure.

[0017] In one embodiment of the present invention, the plurality of recesses are formed to a depth of 1 micrometer to 10 micrometers by a one-step etching process; or to a depth of 10 micrometers to 50 micrometers by a multi-step etching process.

[0018] In one embodiment of the present invention, in step (b), the plurality of first chips are fused and bonded within at least one of the plurality of recesses.

[0019] In one embodiment of the present invention, step (b) further includes first depositing a bonding medium in the recess, and then placing the first chiplet on the bonding medium.

[0020] In one embodiment of the present invention, the first metal interconnect structure includes at least one horizontal interconnect structure and at least one first bonding metal structure, wherein the horizontal interconnect structure is used for electrical connection between the plurality of first chips, and the first bonding metal structure is used for electrical connection between the first chip assembly wafer and the second wafer.

[0021] In one embodiment of the present invention, in step (e), the second wafer includes a substrate, at least one circuit structure and the second metal interconnect structure, and the first wafer and the second wafer are different wafers.

[0022] In one embodiment of the present invention, in step (e), the second wafer further includes a plurality of second chips, wherein the second chips and the first chips are chips of different types.

[0023] In one embodiment of the present invention, in step (e), the second metal interconnect structure includes at least one second bonding metal structure for electrically connecting to the first bonding metal structure of the first chip assembly wafer.

[0024] In one embodiment of the present invention, step (f) further includes filling the perforation with a conductive material.

[0025] In one embodiment of the present invention, the surface of each of the first small chips does not exceed the first surface of the first wafer.

[0026] In one embodiment of the present invention, after step (g), a further step is included: forming a plurality of pad openings on the passivation layer, and electrically connecting the plurality of pad openings to a third metal interconnect structure of a third component wafer.

[0027] In one embodiment of the present invention, the method for manufacturing the third component wafer includes the following steps:

[0028] (1) A third wafer is provided, wherein a third surface of the third wafer has a plurality of recesses;

[0029] (2) A plurality of third chips are bonded in at least one of the plurality of recesses, wherein there is a third gap between two adjacent third chips;

[0030] (3) Fill the third gap and flatten the third surface;

[0031] (4) A third metal interconnect structure is formed on the third surface to form a third chip assembly wafer.

[0032] In one embodiment of the present invention, the plurality of third chips and the plurality of first chips are the same or different types of chips.

[0033] In one embodiment of the present invention, after the first chiplet and the third chiplet are bonded, the surface of each third chiplet does not exceed the surface of the third wafer.

[0034] In one embodiment of the present invention, the plurality of first chips includes at least one thick chip, which has a greater thickness than the other first chips.

[0035] In one embodiment of the present invention, the plurality of first chips have the same thickness, and the types of the plurality of first chips are selected from one or more of the family of sensing chips, memory chips and logic chips.

[0036] In one embodiment of the present invention, at least one of the plurality of recesses includes a deep region and a shallow region, wherein the deep region is used to provide the thick chip.

[0037] In one embodiment of the present invention, the recess is divided into multiple regions and etched multiple times to form the deep region and the shallow region.

[0038] To make the above description of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings: Attached Figure Description

[0039] Figure 1 This is a flowchart of a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention;

[0040] Figures 2A to 2G This diagram illustrates the fabrication of a first chip component wafer according to one embodiment of the present invention.

[0041] Figures 2H to 2J This diagram shows an electrical network structure of a plurality of first small chips in one embodiment of the present invention.

[0042] Figure 3 This is a schematic diagram of a second wafer structure according to an embodiment of the present invention;

[0043] Figures 4A to 4E This diagram illustrates the bonding process and structure between a first chip component wafer and a second wafer in one embodiment of the present invention.

[0044] Figure 5 This diagram shows a stacked structure of a three-dimensional semiconductor device according to an embodiment of the present invention.

[0045] Figures 6A to 6B This diagram shows a structural schematic of a first chip assembly wafer carrying first small chips of different thicknesses, according to an embodiment of the present invention. Detailed Implementation

[0046] The following description of embodiments is with reference to the accompanying drawings, which illustrate specific embodiments in which the invention can be implemented. Directional terms used in this invention, such as "up," "down," "front," "back," "left," "right," "top," and "bottom," are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding the invention, and not for limiting the invention.

[0047] Please refer to Figure 1 An embodiment of the present invention provides a method for manufacturing a three-dimensional semiconductor device, the method mainly comprising the following steps:

[0048] S01: A first wafer is provided, wherein a first surface of the first wafer has at least one recess;

[0049] S02: A plurality of first small chips are bonded in the recess, wherein there is a first gap between two adjacent first small chips;

[0050] S03: Fill the first gap and flatten the first surface;

[0051] S04: At least one first metal interconnect structure is formed on the first surface to form a first chip assembly wafer;

[0052] S05: Bond the first chip assembly wafer to a second wafer;

[0053] S06: After thinning the first chip assembly wafer, a plurality of through holes extending to the first metal interconnect structure are formed within the first gap;

[0054] S07: Deposit a passivation layer on the thinned surface and form a redistribution layer; and

[0055] S08: Multiple pad openings are formed on the passivation layer.

[0056] Please refer to Figures 2A to 2B The manufacturing method of a three-dimensional semiconductor device according to an embodiment of the present invention first involves step S01: providing a first wafer 10, wherein a first surface 101 of the first wafer 10 has at least one recess 102. Preferably, the recess 102 can be formed by etching. The size of the recess 102 can be adjusted according to actual conditions, taking into account the number and size of the small chips to be subsequently carried therein. In one embodiment of the present invention, the recess 102 is formed to a depth of 1 micrometer to 10 micrometers by a one-step etching process; or to a depth of 10 micrometers to 50 micrometers by a multi-step etching process. The etching process can be dry etching, and the etching depth can range from 2 micrometers to 50 micrometers.

[0057] In one embodiment, the first wafer 10 may be a non-device wafer. Preferably, the first wafer 10 may have a multilayer structure of silicon / insulator / silicon on insulator (SOI), or may not have an SOI structure. Preferably, the first wafer 10 may include a substrate formed of a silicon-based semiconductor material, gallium arsenide (GaAs), indium phosphide, or diamond, etc. Figure 2AAs shown, the first wafer 10 further includes a hard mask 103 and an oxide layer 104. The hard mask 103 can be made of materials such as silicon nitride or silicon oxynitride, and is formed on the first surface 101 of the first wafer 10 by chemical vapor deposition. The thickness of the hard mask 103 can be from 1 micrometer to 5 micrometers. When etching the first wafer 10 to form the recess 102, the oxide layer 104 can serve as an etch barrier layer.

[0058] Please refer to Figures 2C to 2D The method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention then proceeds to step S02: bonding a plurality of first small chips 11 within the recess 102, wherein a first gap 1021 exists between two adjacent first small chips 11. In this step, at least one second gap 1022 may exist between the first small chip 11 and the sidewall of the recess 102. The widths of the first gap 1021 and the second gap 1022 are not particularly limited; they may be the same or different widths. Furthermore, the second gaps 1022 may also have the same or different widths.

[0059] In one embodiment, the first chip 11 is bonded to the recess 102 of the first wafer 10 in a back-to-back manner. Preferably, the first chip 11 can be bonded to the recess 102 using a fusion bonding method, specifically as follows: Figure 2C A bonding medium 12, such as one of silicon dioxide, silicon nitride, silicon carbide nitride, and silicon oxynitride, is deposited on the bottom of the recess 102, and then the first chip 11 is disposed on the bonding medium 12. Furthermore, referring to… Figure 2D Alternatively, the bonding medium 12 can be deposited on the back side of the first chip 11 before bonding, and then the first chip 11 can be placed on the bottom of the recess 102. It should be understood that the bonding medium deposited on the back side of the first chip 11 and the bonding medium deposited in the recess 102 do not necessarily have to be the same material; different materials can be used depending on the situation. The process for depositing the bonding medium 12 can be, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD), and the thickness of the bonding medium 12 can be in the range of 10 nanometers to 1000 nanometers.

[0060] In one embodiment, the number of the first small chips 11 within a recess 102 can be 2, 4, or 6, but is not limited thereto; the number can be adjusted according to actual needs. (Refer to...) Figure 2DThe specific structure of the first chip 11 is not particularly limited, but it can generally have the same or different substrate material as the first wafer. The first chip 11 also has a conductive metal layer 111, which may include multiple layers of metal wiring and multiple layers of metal vias (not shown). The metal wiring can be metal materials such as Cu, Al, W, Ag, and Au. In one embodiment of the present invention, after the first chip 11 is disposed in the recess 102, the surface of each first chip 11 preferably does not exceed the first surface 101 of the first wafer 10.

[0061] Please refer to Figure 2E The method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention then proceeds to step S03: filling the first gap 1021 and performing a planarization treatment on the first surface 101. In this step, the first gap 1021 can be filled with a filler material 13 by chemical vapor deposition (CVD) or spin coating. The filler material 13 can be a thermosetting polymer, a thermoplastic polymer, or a polymer composite material. The thermosetting polymer can be, for example, epoxy resin. The thermoplastic polymer can be, for example, polydimethylsiloxane (PDMS). The polymer composite material can be, for example, polymer fibers. The filler material 13 can also be silicon oxide, silicon nitride, or a low-k dielectric, which can be deposited by PECVD (plasma enhanced chemical vapor deposition). Preferably, the second gap 1022 is filled simultaneously with the first gap 1021. After filling the first gap 1021 and the second gap 1022, the first surface 101 is planarized. The planarization treatment can be performed using processes such as chemical mechanical polishing, wet etching, or dry etching.

[0062] Please refer to Figures 2F to 2G The method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention then proceeds to step S04: forming at least one first metal interconnect structure 14 on the first surface 101 to obtain a first chip assembly wafer. In this step, the first metal interconnect structure 14 includes at least one horizontal interconnect structure 141 (see...). Figure 2F ) and at least one first bonded metal structure 142 (see Figure 2G The horizontal interconnect structure 141 is used for electrical connection between the plurality of first chips 11, and the first bonding metal structure 142 can subsequently be used for electrical connection to other wafers or components.

[0063] Preferably, the spacing between the first bonding metal structures 142 can be from 0.5 micrometers to 5 micrometers. Specifically, the method for forming the first bonding metal structure 142 can be, for example, depositing one or more materials such as silicon nitride, silicon dioxide, silicon carbide, and silicon oxynitride as a bonding metal medium over the horizontal interconnect structure 141, and then forming the first bonding metal structure 142 using a damascus process. The first bonding metal structure 142 can be formed from materials such as Cu, Al, W, Ag, and Au, and the first bonding metal structure 142 is electrically connected to the horizontal interconnect structure 141.

[0064] Please refer to Figures 2H to 2J This illustrates the possible electrical network structure between the individual first chips 11 in the first chip assembly wafer. For example... Figures 2H to 2J As shown, the first chiplets 11 can form various network structures through the first metal interconnect structure 14, and the network structure is a reconfigurable electrical connection network. Although this invention only illustrates an example of four chiplets, practical applications are not limited to four, and more or fewer chiplets can be used to form other electrical connection networks.

[0065] The manufacturing method of a three-dimensional semiconductor device according to an embodiment of the present invention is followed by step S05: bonding the first chip assembly wafer to a second wafer 20.

[0066] Please refer to Figure 3 In this step, the second wafer 20 may include a substrate 21, which is made of silicon or other semiconductor materials. A circuit layer 22 is provided on the substrate 21, and the circuit layer 22 may include at least one circuit structure 221 and a second metal interconnect structure 223. The circuit structure 221 may be a logic circuit structure, a control circuit, an input / output circuit, a digital-to-analog converter circuit, or a combination thereof. The circuit layer 22 may also include the following device structures (not shown): for example, MOSFET, FINFET, GAAFET, or diode. The circuit layer 22 also includes an interlayer dielectric (ILD) 222, which may be a combination of one or more materials such as silicon dioxide, silicon nitride, silicon carbide nitride, and borosilicate glass (BOSG). Multiple contact holes may be formed in the interlayer dielectric 222 for electrically connecting the circuit structure 221 and the second metal interconnect structure 223. Specifically, the first metal interconnect structure 14 of the first chip assembly wafer is used to bond the first chip assembly wafer to the second metal interconnect structure 223 on a second surface 201 of the second wafer 20.

[0067] Preferably, the second wafer 20 may be, for example, a logic wafer containing multiple logic chips. In this step, it is clearly evident that the first chip assembly wafer formed by the first wafer 10 and the second wafer 20 are wafers of different types and functions. In one embodiment of the present invention, in this step, the second wafer 20 may further contain multiple second small chips (not shown), and the second small chips and the first small chip 11 are chips of different types.

[0068] Please refer to Figure 4A This is a schematic diagram showing the structure of the second wafer 20 and the first chip assembly wafer after bonding. Figure 4A In this process, the second wafer 20 and the first chip assembly wafer are bonded face-to-face, and a hybrid bonding method can be used. Before bonding, the bonding interface between the first chip assembly wafer and the second wafer 20 needs to be surface-treated, including hydrophilization, planarization, plasma activation, and wet cleaning. After bonding, high-temperature annealing is required. Specifically, hydrophilization can use deionized water or an acidic solution; planarization can be performed using chemical mechanical polishing; plasma activation can be performed using H2 or O2, or a mixture of the two; the annealing temperature can be 200 to 400°C, and the annealing time can be 30 to 120 minutes. Through hybrid bonding, an electrical connection is formed between the first small chip on the first chip assembly wafer and the second wafer.

[0069] In one embodiment of the present invention, the second metal interconnect structure 223 includes at least one second bonding metal structure 2231 for electrically connecting to the first bonding metal structure 142 of the first chip assembly wafer.

[0070] Reference Figures 4B to 4C The manufacturing method of a three-dimensional semiconductor device according to an embodiment of the present invention is then followed by step S06: after thinning the first chip assembly wafer, a plurality of through holes 15 extending to the first metal interconnect structure 14 are formed in the first gap 1021.

[0071] like Figure 4B As shown, the oxide layer 104 remains after the first chip assembly wafer is thinned. Thinning can be achieved, for example, by heating, causing the substrate of the first chip assembly wafer to expand, thereby causing the substrate to detach from the oxide layer 104. Alternatively, in addition to heating, appropriate thinning methods can be selected according to the type of the first wafer 10, such as mechanical polishing, wet etching, etc., all of which are applicable.

[0072] Next refer to Figure 4CThe via 15 can be formed, for example, by etching to remove a portion of the filling material 13. The via 15 is electrically connected to the first metal interconnect structure 14. The specific manufacturing process of the via 15 can be, for example, patterning the thinned surface of the first chip assembly wafer, and forming the via 15 through etching, wet cleaning, physical vapor deposition (PVD), and planarization. In one embodiment of the invention, this step further includes filling the via 15 with a conductive material. Preferably, the conductive material can be a metal such as Cu, Al, W, Ag, Au, or its metal alloy.

[0073] Reference Figures 4D to 4E The method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention then proceeds to step S07: depositing a passivation layer 16 on the thinned surface and forming a redistribution layer 17. In this step, the first metal interconnect structure 14 forms an electrical connection structure with the redistribution layer 17 through the plurality of vias 15.

[0074] Reference Figure 4D The redistribution layer 17 is formed on the thinned surface of the first chip component wafer. It may comprise a multi-layered metal structure, and can be a metal layer formed from materials such as Al, W, and Cu. The multi-layered structure of the redistribution layer 17 can be achieved, for example, using conventional techniques in the art, such as multiple vias (not shown), to form complete electrical connections between the metal layers, and is not particularly limited. Preferably, the uppermost metal portion of the redistribution layer 17 is formed of Al metal, while the lower metal portions of the redistribution layer 17 are formed of Cu metal. Preferably, the uppermost metal portion of the redistribution layer 17 can serve as a solder pad.

[0075] Alternatively, in one embodiment of the present invention, such as Figure 5 As shown, the redistribution layer 17 of the first chip component wafer can also be directly electrically connected to a third metal interconnect structure 34 of a third component wafer 30 by bonding. Preferably, the manufacturing process of the third component wafer 30 is basically the same as that of the first chip component wafer. The third component wafer 30 can also carry multiple third chips 31, and the type of the third chips 31 can be different from or the same as that of the first chips 11. Therefore, by using the steps disclosed in this invention, first forming the target component wafers and then bonding them together, a three-dimensional integrated stacked structure of multilayer chip component wafers can be realized.

[0076] In one embodiment of the present invention, the passivation layer 16 also includes a multilayer structure, such as... Figure 4EThe invention includes a first passivation layer 161 and a second passivation layer 162. The number of passivation layers can be adjusted according to the formation process of the redistribution layer 17. Specifically, the redistribution layer 17 is located within the passivation layer 16.

[0077] In one embodiment, the method for manufacturing a three-dimensional semiconductor device provided by the present invention further includes step S08: forming a plurality of pad openings 18 on the passivation layer 16. Referring again... Figure 4E In this step, a second passivation layer 162 is deposited above the redistribution layer 17. The material can be silicon nitride or silicon oxide. Then, the pad opening 18 is formed on the second passivation layer 162. The pad opening 18 can be formed by dry etching, in which a portion of the uppermost metal portion of the redistribution layer 17 exposed serves as the pad.

[0078] In one embodiment of the present invention, after step S08, a further step may be included: electrically connecting the third metal interconnect structure 34 of the third component wafer 30 through the plurality of pad openings 18, such as... Figure 5 As shown. The third metal interconnect structure 34 may also include a third horizontal interconnect structure 341 and at least a third bonding metal structure 342.

[0079] In one embodiment of the present invention, the method for manufacturing the third component wafer is similar to the method for manufacturing the first chip component wafer, and mainly includes the following steps:

[0080] (1) A third wafer is provided, wherein a third surface of the third wafer has a plurality of recesses;

[0081] (2) A plurality of third chips 31 are bonded in at least one of the plurality of recesses, wherein there is a third gap between two adjacent third chips 31;

[0082] (3) Fill the third gap and planarize the third surface; and

[0083] (4) A third metal interconnect structure 34 is formed on the third surface to form a third chip assembly wafer.

[0084] In one embodiment of the present invention, the plurality of third small chips 31 and the plurality of first small chips 11 are chips of the same or different types. In one embodiment of the present invention, after the first small chips 11 and the third small chips 31 are respectively bonded, the surface of each third small chip 31 does not exceed the surface of the third wafer.

[0085] Figures 6A to 6BThis diagram illustrates a structure comprising a plurality of first small chips 11 of varying thicknesses within a first component wafer. Specifically, this can be achieved by etching recesses 102 onto the first surface 101 of the first wafer 10. These recesses 102 include deep regions A1 and shallow regions A2. The etching can be performed, for example, in two steps: first, dry etching to form the shallower shallow regions A2, and then a second etching to form the deeper deep regions A1. In one embodiment, as... Figure 6B As shown, the recessed portion 102 can be divided into multiple regions and etched multiple times to form two deep regions A1 and one shallow region A2. The depth of the deep region A1 can be from 10 micrometers to 50 micrometers, and the depth of the shallow region A2 can be from 2 micrometers to 10 micrometers.

[0086] In one embodiment of the present invention, the plurality of first chips 11 may have significantly different thicknesses from each other, for example, including at least one thick chip 11A and at least one thin chip 11B. Preferably, the thick chip 11A has a greater thickness than the other first chips. Preferably, the deeper region A1 is used to provide the thicker chip 11A by the fusion bonding method described above, while the shallower region A2 is used to provide the thinner chip 11B. In one embodiment of the present invention, the plurality of first chips 11 have the same thickness. In one embodiment, the type of the plurality of first chips 11 is selected from one or more of the family of sensor chips, memory chips, and logic chips. Then, the first chip assembly wafers carrying different thicknesses are bonded to a second wafer and a third assembly wafer through the steps described in the above embodiments to form a three-dimensional semiconductor device.

[0087] The present invention has the following advantages compared with the prior art:

[0088] Compared to traditional direct adhesive bonding, fusion bonding avoids wafer contamination and ensures a certain level of bonding precision. This invention does not use TSV structures and does not create through-holes in the silicon material of the wafer, thus avoiding the impact of TSV stress on the electrical performance of the component. Furthermore, the implementation process is simple and highly reliable. In particular, the fabrication of through-holes in this invention is performed after the first chip component wafer is bonded to the second wafer, without affecting the bonding yield. Compared to traditional chip-to-wafer bonding, this invention creates a three-dimensional stacked structure of component wafers through wafer-to-wafer bonding, significantly improving bonding alignment precision and enabling extremely small interconnect pitches, thereby achieving high-density interconnects.

[0089] The present invention has been described by the above-described embodiments; however, these embodiments are merely examples for implementing the present invention. It must be noted that the disclosed embodiments do not limit the scope of the present invention. Conversely, modifications and equivalents contained within the spirit and scope of the claims are included within the scope of the present invention.

Claims

1. A method for manufacturing a three-dimensional semiconductor device, characterized in that, The manufacturing method includes the following steps: (a) A first wafer is provided, wherein a first surface of the first wafer has at least one recess; (b) A plurality of first chips are bonded in the recess, wherein there is a first gap between two adjacent first chips; (c) Fill the first gap and flatten the first surface; (d) Forming at least one first metal interconnect structure on the first surface to form a first chip assembly wafer; (e) Bonding at least one second metal interconnect structure on a second surface of a second wafer to the first chip assembly wafer via the first metal interconnect structure; (f) After thinning a back surface of the first chip assembly wafer, a plurality of through holes extending to the first metal interconnect structure are formed in the first gap, wherein the back surface and the first surface are opposite to each other. as well as (g) A passivation layer is deposited on the thinned back surface and a redistribution layer is formed; The first metal interconnect structure forms an electrical connection structure with the redistribution layer through the plurality of vias; the surface of each of the first chips does not exceed the first surface of the first wafer.

2. The method for manufacturing a three-dimensional semiconductor device as described in claim 1, characterized in that: The first wafer is a multilayer structure of silicon / insulator / silicon.

3. The method for manufacturing a three-dimensional semiconductor device as described in claim 1, characterized in that: The plurality of recesses are formed to a depth of 1 micrometer to 10 micrometers by a one-step etching process; or to a depth of 10 micrometers to 50 micrometers by a multi-step etching process.

4. The method for manufacturing a three-dimensional semiconductor device as described in claim 1, characterized in that: In step (b), the plurality of first chips are fused and bonded within at least one of the plurality of recesses.

5. The method for manufacturing a three-dimensional semiconductor device as described in claim 4, characterized in that: Step (b) further includes first depositing a bonding medium in the recess, and then placing the first chiplet on the bonding medium.

6. The method for manufacturing a three-dimensional semiconductor device as described in claim 1, characterized in that: The first metal interconnect structure includes at least one horizontal interconnect structure and at least one first bonding metal structure. The horizontal interconnect structure is used for electrical connection between the plurality of first chips, and the first bonding metal structure is used for electrical connection between the first chip assembly wafer and the second wafer.

7. The method for manufacturing a three-dimensional semiconductor device according to any one of claims 1 to 6, characterized in that: In step (e), the second wafer includes a substrate, at least one logic circuit structure, and the second metal interconnect structure, and the first wafer and the second wafer are different wafers.

8. The method for manufacturing a three-dimensional semiconductor device as described in claim 1, characterized in that: In step (e), the second wafer further includes a plurality of second chips, the second chips and the first chips being chips of different types.

9. The method for manufacturing a three-dimensional semiconductor device as described in claim 6, characterized in that: In step (e), the second metal interconnect structure includes at least one second bonding metal structure for electrically connecting to the first bonding metal structure of the first chip assembly wafer.

10. The method for manufacturing a three-dimensional semiconductor device according to any one of claims 1 to 6, characterized in that: In step (f), a conductive material is also filled into the perforation.

11. The method for manufacturing a three-dimensional semiconductor device as described in claim 1, characterized in that: Following step (g), a further step (h) is included: forming a plurality of pad openings on the passivation layer; electrically connecting to a third metal interconnect structure of a third component wafer through the plurality of pad openings.

12. The method for manufacturing a three-dimensional semiconductor device as described in claim 11, characterized in that: The method for manufacturing the third component wafer includes the following steps: (1) A third wafer is provided, wherein a third surface of the third wafer has a plurality of recesses; (2) A plurality of third chips are bonded in at least one of the plurality of recesses, wherein there is a third gap between two adjacent third chips; (3) Fill the third gap and flatten the third surface; (4) A third metal interconnect structure is formed on the third surface to form a third chip assembly wafer.

13. The method for manufacturing a three-dimensional semiconductor device as described in claim 12, characterized in that: The plurality of third chips and the plurality of first chips are the same or different types of chips.

14. The method for manufacturing a three-dimensional semiconductor device as described in claim 12, characterized in that: After the first chiplet and the third chiplet are bonded, the surface of each third chiplet does not exceed the surface of the third wafer.

15. The method for manufacturing a three-dimensional semiconductor device as described in claim 1, characterized in that: The plurality of first chips includes at least one thick chip, which has a greater thickness than the other first chips.

16. The method for manufacturing a three-dimensional semiconductor device as described in claim 1, characterized in that: The plurality of first small chips have the same thickness, and the types of the plurality of first small chips are selected from one or more of the family of sensing chips, memory chips and logic chips.

17. The method for manufacturing a three-dimensional semiconductor device as described in claim 15, characterized in that: At least one of the plurality of recesses includes a deep region and a shallow region, the deep region being used to house the thick chip.

18. The method for manufacturing a three-dimensional semiconductor device as described in claim 17, characterized in that: The recessed area is divided into multiple regions and etched multiple times to form the deep region and the shallow region.

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