A method for fabricating a semiconductor structure

Abstract

This invention provides a method for fabricating a semiconductor structure, applicable to the field of semiconductor technology. In this invention, multiple dielectric layers (such as a first dielectric layer) are first formed on a substrate. Then, grooves and vias of different depths and widths are sequentially formed in different dielectric layers. A portion of the dielectric layer is removed along the vias, thereby forming an air gap structure composed of the remaining multiple dielectric layers and vias. This air gap structure is then positioned between adjacent chips, components, and devices, thereby enhancing heat dissipation during device fabrication, reducing the impact of high temperatures on chips, components, and devices during the fabrication process, solving the problem of poor heat dissipation performance during device fabrication, and improving device reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Technology

[0002] With the rapid growth of the semiconductor industry, more chips, components, and devices need to be integrated into a given area. High temperatures can significantly impact the operating state of chips, components, and devices, leading to increased error rates and reduced stability. Therefore, how to enhance thermal diffusion in device manufacturing processes while meeting the requirements of high device integration has become a problem that those skilled in the art need to solve. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating a semiconductor structure to solve the problem of poor heat dissipation performance during device fabrication and improve device reliability.

[0004] To address the aforementioned technical problems, this invention provides a method for fabricating a semiconductor structure, which may include at least:

[0005] A substrate is provided, the substrate comprising a first region and a second region;

[0006] A first dielectric layer is formed on the first and second regions of the substrate;

[0007] Multiple mutually separated grooves are formed within the first dielectric layer of the first and second regions;

[0008] A second dielectric layer is formed within the groove, and the second dielectric layer also extends laterally to cover the first dielectric layer between adjacent grooves;

[0009] Multiple mutually spaced through holes are formed within the second dielectric layer, and the through holes also penetrate the second dielectric layer to expose the bottom of the first dielectric layer between adjacent grooves;

[0010] A portion of the first dielectric layer exposed at the bottom of the through-hole is removed along the through-hole to form a plurality of air gap structures surrounded by the second dielectric layer and a portion of the first dielectric layer, and the top of a portion of the air gap structure also has an opening;

[0011] A third dielectric layer is formed on the air gap structure.

[0012] In some optional examples, the groove includes a first groove located in the first region and a second groove located in the second region, wherein the width of the first groove in the horizontal direction is smaller than the width of the second groove in the horizontal direction.

[0013] In some alternative examples, the first dielectric layer includes a first nitride layer, an oxide layer, and a second nitride layer stacked sequentially from bottom to top.

[0014] In some optional examples, the step of forming the groove may include:

[0015] The second nitride layer, the oxide layer, and a portion of the first nitride layer in the first dielectric layer are etched to form a deep trench in the first dielectric layer, exposing the remaining portion of the first nitride layer at the bottom.

[0016] Remove the second nitride layer from the first dielectric layer on both sides of the top of the deep trench to form a groove surrounded by the oxide layer in the first dielectric layer and the remaining first nitride layer.

[0017] In some optional examples, the material of the second dielectric layer is the same as the material of the first nitride layer in the first dielectric layer.

[0018] In some optional examples, the bottom surface of the through-hole is lower than the upper surface of the oxide layer in the vertical direction.

[0019] In some optional examples, the distance between the top and bottom of the through hole is less than the distance between the upper and lower surfaces of the groove.

[0020] In some optional examples, the projection of the through hole in the vertical direction does not overlap with the projection of the groove in the vertical direction.

[0021] In some optional examples, the step of forming the air gap structure may include:

[0022] Remove the oxide layer in the first dielectric layer located between adjacent grooves at the bottom of the through hole to form an air gap structure surrounded by the second dielectric layer and the first nitride layer in the first dielectric layer.

[0023] In some optional examples, the third dielectric layer also extends to fill a portion of the height of the opening in the air gap structure.

[0024] In some optional examples, the formation of the second dielectric layer is located within the groove, and further includes:

[0025] The second medium layer is formed in the first groove to form the first support column, and the second medium layer is formed in the second groove to form the second support column.

[0026] In some optional examples, after forming the third dielectric layer, the following may also be included:

[0027] Forming a plug hole that penetrates the second support column;

[0028] A plug structure is formed within the plug hole, and the plug structure extends laterally to cover the third medium layer, while its bottom is in direct contact with the substrate.

[0029] In some optional examples, the density of the air gap structure located in the first region is different from the density of the air gap structure located in the second region.

[0030] In some alternative examples, when viewed from a direction perpendicular to the substrate, the total area of ​​the air gap structure located in the first region is greater than the total area of ​​the air gap structure located in the second region.

[0031] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects:

[0032] In the semiconductor structure fabrication method proposed in this invention, multiple dielectric layers (such as a first dielectric layer) are first formed on a substrate. Then, grooves and vias of different depths and widths are sequentially formed in different dielectric layers. A portion of the dielectric layer is removed along the vias, thereby forming an air gap structure composed of the remaining multiple dielectric layers and vias. The air gap structure is then placed between adjacent chips, components, and devices to enhance the thermal diffusion of heat generated during the device fabrication process, reduce the impact of high temperatures during the fabrication process on chips, components, and devices, solve the problem of poor heat dissipation performance during the device fabrication process, and improve the reliability of the device. Attached Figure Description

[0033] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0034] Figure 1 This is a schematic flowchart of the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0035] Figures 2-11 This is a schematic diagram of the semiconductor structure fabrication method provided in the embodiments of the present invention during the fabrication process;

[0036] Figure 12 To utilize Figure 1 A top view of the semiconductor structure formed by the method shown in the figure.

[0037] The attached figures are labeled as follows:

[0038] 100 - Substrate, 100A - First region of substrate, 100B - Second region of substrate, 110 / 110' / 110'' - First dielectric layer, 111 / 111' - First nitride layer, 112 / 112' / 112'' - Oxide layer, 113 - Second nitride layer, 120 - First photoresist layer, 101 - Groove, 101a - First groove, 101b - Second groove, 130 / 130' - Second dielectric layer, 140 / 140' - First isolation layer, 150 - Second photoresist layer, 102 - First opening, 103 - Through hole, 251 - Air gap structure, 160 - Third dielectric layer, 170 - Second isolation layer, 180 - Third photoresist layer, 104 - Plug hole, 190 - Plug structure.

[0039] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0040] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0041] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clarify the illustration of the embodiments of the invention. It is understood that the terms "on," "above," and "over" in this invention should be interpreted in the broadest sense, such that "on" means not only "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer.

[0042] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating the fabrication method of the semiconductor memory provided in this embodiment. Figure 1 As shown, the method for fabricating the semiconductor structure provided in this embodiment includes at least the following steps:

[0043] Step S101: Provide a substrate, the substrate including a first region and a second region.

[0044] Step S102: A first dielectric layer is formed on the first and second regions of the substrate.

[0045] Step S103: A plurality of mutually separated grooves are formed within the first dielectric layer of the first region and the second region.

[0046] Step S104: A second dielectric layer is formed within the groove, and the second dielectric layer also extends laterally to cover the first dielectric layer between adjacent grooves.

[0047] Step S105: A plurality of mutually spaced through holes are formed within the second dielectric layer, the through holes also penetrating the second dielectric layer to expose the bottom of the first dielectric layer between adjacent grooves.

[0048] Step S106: Remove a portion of the first dielectric layer exposed at the bottom of the through hole along the through hole to form a plurality of air gap structures surrounded by the second dielectric layer and a portion of the first dielectric layer, and the top of a portion of the air gap structure also has an opening.

[0049] Step S107: A third dielectric layer is formed on the air gap structure.

[0050] In the semiconductor structure fabrication method proposed in this invention, a first dielectric layer is first formed on a substrate, then multiple grooves are formed within the first dielectric layer, followed by the formation of a second dielectric layer and vias through the second dielectric layer with the bottom exposed between adjacent grooves. Then, the portion of the first dielectric layer between adjacent grooves is removed along the vias, thereby forming an air gap structure composed of the remaining first dielectric layer, second dielectric layer, and vias. This air gap structure is then positioned between adjacent chips, components, and devices to enhance heat dissipation during device fabrication, reduce the impact of high temperatures on chips, components, and devices, solve the problem of poor heat dissipation during device fabrication, and improve device reliability.

[0051] In order to enable those skilled in the art to easily understand the semiconductor structure preparation method in the embodiments of the present invention, the following will further explain the semiconductor structure preparation method proposed in the present invention with reference to the various structural schematic diagrams in the preparation process.

[0052] Figures 2-11 This is a schematic diagram of the semiconductor structure fabrication method provided in the embodiments of the present invention during the fabrication process.

[0053] Perform the above steps S101~S102: Please refer to... Figure 2A substrate 100 is provided, and the substrate 100 is divided into a first region 100A and a second region 100B disposed adjacently. In one embodiment, the substrate 100 is any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto. Furthermore, at least one semiconductor device (not shown), such as a MOS transistor, a gate-all-around (GAA) structure, etc., may be formed within the substrate 100. The first region 100A and the second region 100B may be defined by a trench isolation structure (not shown) formed within the substrate 100. Next, a first dielectric layer 110 and a first photoresist layer 120 can be sequentially formed on the surface of the substrate 100 using at least one deposition process, such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The first dielectric layer 110 may include a first nitride layer 111, an oxide layer 112, and a second nitride layer 113 stacked sequentially from bottom to top, with the first photoresist layer 120 located on the second nitride layer 113. In one embodiment, the materials of the first nitride layer 111 and the second nitride layer 113 may include silicon nitride, and the material of the oxide layer 112 may include silicon oxide, such as silicon dioxide, but is not limited thereto.

[0054] Perform the above step S103: Please refer to Figure 3 Using the first photoresist layer 120 as a mask, the second nitride layer 113, oxide layer 112, and part of the first nitride layer 111 in the first dielectric layer 110 are removed downwards using at least one of dry etching or wet etching processes to form a plurality of deep trenches in the first dielectric layer 110' with the bottom exposed to the remaining part of the first nitride layer 111'. Then, the second nitride layer 113 in the first dielectric layer 110' on both sides of the top of each deep trench is removed to form a groove 101 surrounded by the etched oxide layer 112' and the remaining first nitride layer 111' in the first dielectric layer 110'. In one embodiment, the grooves 101 formed in the first region 100A and the second region 100B may have different widths in a direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction). Based on this, the grooves 101 formed in this step can be divided into a first groove 100a in the first region 100A and a second groove 100b in the second region 100B according to their different widths in the horizontal direction. The width of the first groove 100a in the horizontal direction is smaller than the width of the second groove 100b in the horizontal direction, but this is not a limitation.

[0055] Perform the above step S104: Please refer to Figure 4A second dielectric layer 130 is formed on the first region 100A and the second region 100B of the substrate 100 using the deposition process described above. The second dielectric layer 130 fills the first groove 100a and the second groove 100b, and extends laterally in the horizontal direction to cover the first dielectric layer 110' between adjacent grooves 100. In one embodiment, the material of the second dielectric layer 130 may be the same as the material of the first nitride layer 111' in the first dielectric layer 110', such as silicon nitride. Based on this, the formed second dielectric layer 130 communicates with the first nitride layer 111' in the first dielectric layer 110' located below it through the portion filled in the groove 101. In another embodiment, after the second dielectric layer 130 is formed in the groove 100, the second dielectric layer 130 located in the first groove 100a can also be defined as a first support pillar (i.e., the area corresponding to the first groove 100a), and the second dielectric layer 130 located in the second groove 100b can be defined as a second support pillar (i.e., the area corresponding to the second groove 100b).

[0056] Following step S104 above: Please refer to Figure 5 First, a first isolation layer 140 and a second photoresist layer 150 can be sequentially formed on the second dielectric layer 130 using a deposition process. In one embodiment, the first isolation layer 140 may include a single layer or multiple layers of dielectric material. Suitable dielectric materials may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, nitrogen-doped silicon carbide, low dielectric constant dielectric materials such as fluorosilicone glass, silicon carbide oxide, spin-coated silicon glass, porous low dielectric constant dielectric materials, or combinations of the above materials, but are not limited thereto. For example, the material of the first isolation layer 140 is silicon oxide, such as silicon dioxide. The second photoresist layer 150 defines a plurality of via patterns, a portion of which is distributed in the second photoresist layer 150 located on the first region 100A, while the remainder is distributed in the second photoresist layer 150 located on the second region 100B.

[0057] Perform the above step S105: Please refer to... Figure 6Using an etching process, with the second photoresist layer 150 as a mask, the first isolation layer 140, the second dielectric layer 130, and a portion of the oxide layer 112' located in the first dielectric layer 110' between adjacent grooves 100 are sequentially etched downwards to form a plurality of horizontally spaced first openings 102 on the first region 100A and the second region 100B. At this time, the first opening 102 passes through the remaining first isolation layer 140', the remaining second dielectric layer 130', and the remaining portion of the oxide layer 112'' after etching in a direction perpendicular to the surface of the substrate 100 (hereinafter referred to as the vertical direction). Then, the first isolation layer 140' on both sides of the top of the first opening 102 is removed to reduce the height of the first opening 102 in the vertical direction, thus obtaining a through-hole 103 with the second dielectric layer 130' on both sides of the top. Figure 7 As shown, the second photoresist layer 150 is then removed. In one embodiment, the bottom surface of the via 103 may be lower than the upper surface of the oxide layer 112'' in the vertical direction, the distance between the top and bottom ends of the via 103 may be less than the distance between the upper and lower surfaces of the groove 101 (including the first groove 100a and the second groove 100b), and the projection of the via 103 in the vertical direction does not overlap with the projection of the groove 101 in the vertical direction. The number of vias 103 may be the same as or different from the number of grooves 101 (including the first groove 100a and / or the second groove 100b).

[0058] Perform the above step S106: Please refer to... Figure 7 Next, along the direction of the through hole 103, the portion of the first dielectric layer 110'' exposed at the bottom of the through hole 103 is removed, specifically, the oxide layer 112'' in the first dielectric layer 110'' is removed, to form a plurality of air gap structures 251 surrounded by the second dielectric layer 130' and a portion of the first dielectric layer 110'', that is, to form an air gap structure 251 surrounded by the second dielectric layer 130' and the first nitride layer 111' in the first dielectric layer 110'', and the top of a portion of the air gap structure 251 also has an opening (i.e., the area corresponding to the through hole 103), as described above. Figure 7 The area outlined by the dashed line is the air gap structure 251 in this embodiment of the invention.

[0059] Perform the above step S107: Please refer to... Figure 8Next, a third dielectric layer 160 is formed on the air gap structure 251 using a deposition process. Since the top of the air gap structure 251 has multiple openings, the bottom of the third dielectric layer 160 formed in this step extends vertically to fill a portion of the height of the openings in the air gap structure 251. In this embodiment of the invention, the air gap structure 251 formed using the above steps can be disposed between adjacent chips, semiconductor devices, or other components, thereby enhancing the thermal diffusion of heat generated during the device manufacturing process. Therefore, after forming the air gap structure 251 on the substrate 100, the following steps can be performed to form a plug structure 190 for electrically connecting adjacent semiconductor devices, as detailed below.

[0060] Following step S107 above, please refer to... Figure 9 After forming the third dielectric layer 160, a second isolation layer 170 and a third photoresist layer 180 may be sequentially formed on the top surface of the third dielectric layer 160. In one embodiment, the material of the second isolation layer 170 may be the same as that of the first isolation layer 140, such as silicon dioxide, or it may be different, such as silicon nitride, but is not limited thereto. The third photoresist layer 180 has a plug hole pattern, and the plug hole pattern is specifically located within the third photoresist layer 180 corresponding to the second region 100B. Next, please refer to... Figure 10 and Figure 11 A plug hole 104 can be formed in the second dielectric layer 130' (which can also be understood as the area corresponding to the second support post) filled in the second groove 100b in the second region 100B, penetrating the third dielectric layer 160 and the second support post. Then, a conductive material, such as a metal dock, is filled in the plug hole 104 to form a plug structure 190. The plug structure 190 also extends laterally to cover the third dielectric layer 160, and its bottom is in direct contact with the substrate 100, thereby allowing the semiconductor device subsequently formed on the plug structure 190 to be electrically connected to the semiconductor device formed in the substrate 100.

[0061] Please see Figure 12 , Figure 12 To utilize Figure 1 A top view of the semiconductor structure formed by the fabrication method shown. From Figure 12 It can be seen that the density of the air gap structure 251 in the first region 100A of the substrate 100 is different from that in the second region 100B. Moreover, from the perspective of the vertical direction, the total area of ​​the air gap structure 251 in the first region 100A is greater than the total area of ​​the air gap structure 251 in the second region 100B.

[0062] In summary, in the semiconductor structure fabrication method proposed in this invention, multiple dielectric layers (such as a first dielectric layer) are first formed on a substrate. Then, grooves and vias of different depths and widths are sequentially formed in different dielectric layers. A portion of the dielectric layer is removed along the vias, thereby forming an air gap structure composed of the remaining multiple dielectric layers and vias. The air gap structure is then placed between adjacent chips, components, and devices, thereby enhancing the thermal diffusion of heat generated during the device fabrication process, reducing the impact of high temperatures during the process on chips, components, and devices, solving the problem of poor heat dissipation performance during the device fabrication process, and improving the reliability of the device.

[0063] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0064] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, and computer-readable storage media are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0065] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A first dielectric layer is formed on the first and second regions of the substrate; Multiple mutually separated grooves are formed within the first dielectric layer of the first and second regions; A second dielectric layer is formed within the groove, and the second dielectric layer also extends laterally to cover the first dielectric layer between adjacent grooves; Multiple mutually spaced through holes are formed within the second dielectric layer, and the through holes also penetrate the second dielectric layer to expose the bottom of the first dielectric layer between adjacent grooves; A portion of the first dielectric layer exposed at the bottom of the through-hole is removed along the through-hole to form a plurality of air gap structures surrounded by the second dielectric layer and a portion of the first dielectric layer, wherein the top of a portion of the air gap structure also has an opening; A third dielectric layer is formed on the air gap structure.

2. The method for preparing the semiconductor structure according to claim 1, characterized in that, The groove includes a first groove located in the first region and a second groove located in the second region, wherein the width of the first groove in the horizontal direction is smaller than the width of the second groove in the horizontal direction.

3. The method for preparing the semiconductor structure as described in claim 1, characterized in that, The first dielectric layer comprises a first nitride layer, an oxide layer, and a second nitride layer stacked sequentially from bottom to top.

4. The method for preparing a semiconductor structure as described in claim 3, characterized in that, The step of forming the groove includes: The second nitride layer, the oxide layer, and a portion of the first nitride layer in the first dielectric layer are etched to form a deep trench in the first dielectric layer, exposing the remaining portion of the first nitride layer at the bottom. Remove the second nitride layer from the first dielectric layer on both sides of the top of the deep trench to form a groove surrounded by the oxide layer in the first dielectric layer and the remaining first nitride layer.

5. The method for preparing the semiconductor structure as described in claim 3, characterized in that, The material of the second dielectric layer is the same as the material of the first nitride layer in the first dielectric layer.

6. The method for preparing a semiconductor structure as described in claim 3, characterized in that, The bottom surface of the through hole is lower than the upper surface of the oxide layer in the vertical direction.

7. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The distance between the top and bottom of the through hole is less than the distance between the upper and lower surfaces of the groove.

8. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The projection of the through hole in the vertical direction does not overlap with the projection of the groove in the vertical direction.

9. The method for preparing a semiconductor structure as described in claim 3, characterized in that, The steps of forming the air gap structure include: Remove the oxide layer in the first dielectric layer located between adjacent grooves at the bottom of the through hole to form an air gap structure surrounded by the second dielectric layer and the first nitride layer in the first dielectric layer.

10. The method for preparing the semiconductor structure according to claim 1, characterized in that, The third dielectric layer also extends to fill a portion of the height of the opening in the air gap structure.

11. The method for preparing a semiconductor structure as described in claim 2, characterized in that, The formation of the second dielectric layer located within the groove further includes: The second medium layer is formed in the first groove to form the first support column, and the second medium layer is formed in the second groove to form the second support column.

12. The method for preparing a semiconductor structure as described in claim 11, characterized in that, After forming the third dielectric layer, the process further includes: Forming a plug hole that penetrates the second support column; A plug structure is formed within the plug hole, and the plug structure extends laterally to cover the third medium layer, while its bottom is in direct contact with the substrate.

13. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The density of the air gap structure located in the first region is different from the density of the air gap structure located in the second region.

14. The method for preparing a semiconductor structure as described in claim 1, characterized in that, Viewed from a direction perpendicular to the substrate, the total area of ​​the air gap structure located in the first region is greater than the total area of ​​the air gap structure located in the second region.

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