MOSFET with enhanced body diode freewheeling capability and method of manufacture
By fabricating a first heavily doped region spaced apart in the MOSFET and controlling the source trench depth, a Schottky contact diode is integrated to form a superjunction structure, which solves the problems of complex process and large reverse leakage current, and achieves the effect of simplifying the process and maintaining forward current carrying capacity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGZHOU YANGJIE ELECTRONIC TECH CO LTD
- Filing Date
- 2024-07-29
- Publication Date
- 2026-07-31
AI Technical Summary
Existing technologies for MOSFETs with integrated Schottky diodes suffer from complex process steps, large reverse leakage current, and compromised forward current carrying capacity.
Schottky contact diodes are integrated by fabricating mutually spaced first-doped regions within an epitaxial wafer and controlling the source trench depth. The low turn-on voltage and high current characteristics of Schottky diodes are utilized, and a superjunction structure is formed to shield the electric field strength and reduce reverse leakage current.
Without adding extra process steps, the reverse leakage current of the Schottky diode was reduced while the forward current carrying capacity was maintained, simplifying the fabrication process and promoting commercialization.
Smart Images
Figure CN118969737B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a MOSFET that enhances the freewheeling capability of a body diode and its fabrication method. Background Technology
[0002] In the field of power electronic device technology, MOSFET, as a commonly used power semiconductor, has replaced transistor as one of the most commonly used switching devices in the power semiconductor field.
[0003] Over the decades of iterations in MOSFETs, the freewheeling capability of the body diode has become increasingly important. Currently, an important technology to improve the freewheeling capability of the body diode is to integrate a Schottky diode, which utilizes the low turn-on voltage and high current characteristics of the Schottky diode to reduce the freewheeling loss of the body diode.
[0004] There are already patents related to MOSFETs with integrated Schottky diodes. Patent publication number CN117334748A discloses a source trench integrated SBD and HK dielectric SiCUMOS and its fabrication method. This method extends the source trench through the body region to the breakdown voltage region, utilizing the current spreading layer below the MOSFET body region and the Schottky contact metal within the trench to form the SBD. To reduce reverse leakage current of the integrated SBD, a high-k dielectric is fabricated below the Schottky contact metal. However, this approach is relatively different from conventional trench MOSFETs. First, additional process steps are required to prepare a current spreading layer to reduce the on-resistance of the SBD. Second, preparing a high-k dielectric under the Schottky contact metal can reduce the reverse leakage current of the integrated SBD, but it also weakens the forward current carrying capacity of the integrated SBD and the MOSFET, and also requires additional process steps. Other patent documents such as those with publication numbers CN117334746A, CN117334747A, CN117334745A, and CN110473914B have similar drawbacks. Summary of the Invention
[0005] This invention addresses the research and development direction of improving the freewheeling capability of body diodes by providing a MOSFET with enhanced freewheeling capability and its fabrication method. This reduces process steps and lowers process difficulty, while reducing the reverse leakage current of the integrated SBD without affecting the forward current carrying capacity of the integrated SBD and the MOSFET device.
[0006] The technical solution of this invention is: A method for fabricating a MOSFET that enhances the freewheeling capability of a body diode includes the following steps: Step S100: Prepare mutually spaced first doped regions within the epitaxial wafer; Step S200: Prepare a second doped source region within the epitaxial wafer; Step S300: A gate trench is fabricated within the epitaxial wafer; Step S400: Gate dielectric and polysilicon are sequentially fabricated in the trench; Step S500: Deposit an isolation layer on the epitaxial wafer, and prepare a source trench by opening a window. The bottom of the source trench extends into the interior of the first doped region, and the trench width is greater than the spacing width of the first doped region. In step S600, a Schottky contact metal is prepared at the bottom of the source trench to form a Schottky contact with the second lightly doped breakdown region. The upper surface of the Schottky contact metal is lower than the lower surface of the second heavily doped source region. Step S700: An ohmic contact metal is prepared in the source trench to form an ohmic contact with the first doped region and the second doped source region. The ohmic contact metal and the Schottky contact metal in the source trench together constitute the source metal. In step S800, a window is opened at the gate trench to prepare the gate metal, and the drain metal is prepared on the back side of the epitaxial wafer. The entire device is then fabricated.
[0007] Specifically, step S100 includes: Step S110: Using photolithography, a mask is used to protect the outer region of the first doped region; and through diffusion or ion implantation, mutually spaced first doped regions are formed.
[0008] Specifically, step S200 includes: In step S210, a photolithography process is used to protect the outer region of the second doped source region using a mask; the second doped source region is formed through a diffusion process or an ion implantation process.
[0009] Specifically, step S300 includes: Step S310: Using photolithography, a mask is used to protect the outer area of the gate trench; the gate trench is formed through etching. Specifically, step S400 includes: Step S410: Using photolithography, a mask is used to protect the outer region of the gate trench, and a thermal oxidation technique is used to prepare the gate dielectric in the gate trench. In step S420, polycrystalline silicon is prepared in the gate trench by chemical vapor deposition.
[0010] Specifically, step S500 includes: Step S510: An isolation layer is prepared by chemical vapor deposition. The external area of the source trench is protected by a mask using photolithography. A window is opened at the source trench by etching. The bottom of the source trench extends into the interior of the first doped region. The trench width is greater than the spacing width of the first doped region. Specifically, step S600 includes: Step S610: Schottky contact metal is prepared at the bottom of the source trench by stripping or etching process. Schottky contact metal forms a Schottky contact with the second lightly doped breakdown region. The upper surface of Schottky contact metal is lower than the lower surface of the second heavily doped source region. Specifically, step S700 includes: Step S710: An ohmic contact metal is prepared in the source trench by a stripping process or an etching process. The ohmic contact metal forms an ohmic contact with the first doped region and the second doped source region. The ohmic contact metal and the Schottky contact metal in the source trench together constitute the source metal. Specifically, step S800 includes: In step S810, the external area of the gate trench opening is protected by a mask through photolithography, the gate trench is opened by etching, and the gate metal is prepared. The drain metal is prepared on the bottom of the epitaxial wafer by thinning and back gold preparation, and the entire device is prepared. A MOSFET that enhances the freewheeling capability of a body diode includes a drain metal, an epitaxial wafer, and an isolation layer arranged sequentially from bottom to top; The epitaxial wafer contains: The first doped region is provided in several parts, which extend downward from the top of the epitaxial wafer and are spaced apart from each other; the bottom surface of the first doped region is higher than the bottom surface of the second lightly doped voltage-resistant region. The second doped source region extends downward from the top surface of the epitaxial wafer and connects to the top surface of the first doped body region; The gate dielectric has several U-shaped cross-sections, which extend downward from the top of the second heavily doped source region, pass through the first heavily doped body region, and extend into the second lightly doped breakdown voltage region. Polycrystalline silicon extends downward from the top surface of the gate dielectric to fill the gate dielectric; A Schottky contact metal is disposed between adjacent first heavily doped regions, with its end extending into the first heavily doped region; the Schottky contact metal is connected to the second lightly doped breakdown region to form a Schottky contact; the upper surface of the Schottky contact metal is lower than the lower surface of the second heavily doped source region; The ohmic contact metal extends upward from the top surface of the Schottky contact metal and passes sequentially through the first heavily doped region, the second heavily doped source region, and the isolation layer. A gate metal extends downward from the top surface of the isolation layer into the polysilicon, forming an ohmic contact with the polysilicon. The first and second doping regions have opposite doping types, namely P-region and N-region, or N-region and P-region, respectively.
[0011] Beneficial effects of this invention: This invention integrates a Schottky contact diode at the bottom of the source trench by fabricating a spaced first heavily doped body region and controlling the source trench depth. Utilizing the low turn-on voltage and high current characteristics of the Schottky diode, the freewheeling loss of the body diode is reduced. Simultaneously, the second lightly doped breakdown voltage region of the Schottky diode is flanked by spaced first heavily doped body regions, forming a superjunction structure of the first heavily doped body region, the second lightly doped breakdown voltage region, and the first heavily doped body region. This superjunction structure provides excellent shielding, effectively reducing the electric field strength of the second lightly doped breakdown voltage region, thereby reducing the reverse leakage current of the integrated Schottky diode.
[0012] The structure of the second lightly doped breakdown voltage region below the first heavily doped region of the device of this invention is consistent with that of a conventional trench MOSFET. It does not require special additional process steps to reduce the reverse leakage current of the integrated Schottky diode. The fabrication process of this invention is fully compatible with the fabrication process of conventional trench MOSFETs. It only requires two additional process steps to fabricate the source trench and the Schottky contact metal. Compared with existing prior art, it reduces the special additional process steps to reduce the reverse leakage current of the integrated Schottky diode without affecting the forward current carrying capacity of the integrated SBD and the MOSFET. This is conducive to the advancement of commercialization and has higher commercial value. Attached Figure Description
[0013] Figure 1 This is a process flow diagram of the present invention; Figure 2 This is a schematic diagram of the cross-sectional structure of the device in step S100; Figure 3 This is a schematic diagram of the cross-sectional structure of the device in step S200; Figure 4 This is a schematic diagram of the cross-sectional structure of the device in step S300; Figure 5 This is a schematic diagram of a structure for fabricating a gate dielectric within a trench. Figure 6 This is a schematic diagram of a structure for fabricating polycrystalline silicon within a trench. Figure 7 This is a schematic diagram of the cross-sectional structure for fabricating the isolation layer; Figure 8 This is a schematic diagram of the cross-sectional structure for fabricating the source trench; Figure 9 This is a schematic diagram of the structure for fabricating Schottky contact metal at the bottom of the source trench; Figure 10 This is a schematic diagram of the structure for fabricating ohmic contact metal inside the source trench; Figure 11 This is a schematic diagram of the cross-sectional structure of the gate metal window; Figure 12This is a schematic diagram of the cross-sectional structure of the gate metal; Figure 13 This is a schematic diagram of the structure for preparing the drain metal; In the figure, 1 is the epitaxial wafer, 2 is the first heavily doped body region, 3 is the second heavily doped source region, 4 is the gate trench, 5 is the gate dielectric, 6 is polysilicon, 7 is the isolation layer, 8 is the source trench, 9 is the Schottky contact metal, 10 is the ohmic contact metal, 11 is the gate metal window, 12 is the gate metal, 13 is the drain metal, 14 is the second heavily doped substrate region, and 15 is the second lightly doped breakdown voltage region. Detailed Implementation
[0014] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0015] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0016] The following is for reference. Figure 1-13 Describe the present invention; Step S100: A plurality of mutually spaced first heavily doped regions 2 are prepared within the epitaxial wafer 1, referring to... Figure 2 As shown; Step S110: Using photolithography, a mask is used to protect the outer region of the first doped region 2; and the first doped regions 2 are formed by diffusion or ion implantation. The first and second doped regions have opposite doping types, i.e., P-region and N-region respectively, or N-region and P-region respectively. Preferably, the first doped region (including the first heavily doped body region 2) is a P-region, and the second doped region (including the second heavily doped source region 3, the second heavily doped substrate region 14, and the second lightly doped breakdown voltage region 15) is an N-region.
[0017] Accordingly, in this embodiment, epitaxial wafer 1 is a Si-based N-type epitaxial wafer; Epitaxial wafer 1 consists of a second heavily doped substrate region 14 and a second lightly doped breakdown voltage region 15, arranged from bottom to top. The thickness of epitaxial wafer 1 is 100-2000 μm, the thickness of the second heavily doped substrate region 14 is 90-1500 μm, the thickness of the second lightly doped breakdown voltage region 15 is 10-500 μm, the thickness of the first heavily doped body region 2 is 1-5 μm, and the spacing between them is set to 1-10 μm. The N-type doping concentration range is 1e. 14 .cm -3 -1e 20 .cm -3 The doping concentration range for P-type doping is 1e. 15 .cm -3 -1e 20 .cm -3 The relevant parameter settings are related to the electrical design of the device; In this embodiment, the thickness of the epitaxial wafer 1 is 350 μm, the thickness of the second heavily doped substrate region 14 is 330 μm, and the doping concentration is 1e. 19 .cm -3 The second lightly doped breakdown region 15 has a thickness of 20 μm and a doping concentration of 1e. 16 .cm -3 The first doped region 2 has a thickness of 2 μm, a spacing of 1 μm, and a doping concentration of 3e. 18 .cm -3 The first doped region 2 was prepared using an ion implantation process.
[0018] Step S200: A second heavily doped source region 3 is prepared within the epitaxial wafer 1, referring to... Figure 3 As shown; Step S210: Using photolithography, a mask is used to protect the outer region of the second doped source region 3; the second doped source region 3 is formed by diffusion or ion implantation. Correspondingly, the second doped source region 3 extends downward from the top surface of the first doped body region 2, with its bottom surface higher than the bottom surface of the first doped body region 2. Its thickness is set to 0.5-3 μm, and the doping concentration range is 1e. 18 .cm -3 -1e 20 .cm -3 The relevant parameter settings are related to the electrical design of the device; In this embodiment, the thickness of the second doped source region 3 is 1 μm, and the doping concentration is 1e. 19. cm -3 The second doped source region 3 was prepared using an ion implantation process.
[0019] Step S300: A gate trench 4 is formed in the epitaxial wafer 1, extending downwards through the second heavily doped source region 3 and the first heavily doped body region 2, as shown in the figure. Figure 4 As shown; Step S310: Using photolithography, a mask is used to protect the external area of the gate trench 4; the gate trench 4 is formed by etching. Accordingly, the gate trench 4 extends downward from the top surface of the epitaxial wafer 1, and its bottom surface is lower than the bottom surface of the first heavily doped region 2 and higher than the bottom surface of the second lightly doped breakdown voltage region 15. The width range is set to 1-10 μm, and the relevant parameter settings are related to the electrical design of the device. In this embodiment, the gate trench 4 has a depth of 4µm and a width of 2µm, and the trench 4 is prepared using an ICP dry etching process.
[0020] In step S400, the gate dielectric 5 and polysilicon 6 are sequentially fabricated within the gate trench 4, referring to... Figure 5 , Figure 6 As shown; In step S410, the external region of the gate trench 4 is protected by a mask using photolithography, and the gate dielectric 5 is prepared in the gate trench 4 using thermal oxidation technology. In step S420, polycrystalline silicon 6 is prepared in the gate trench 4 by chemical vapor deposition; Accordingly, the gate dielectric 5 is located in the trench 4 and is in contact with the second heavily doped source region 3, the first heavily doped body region 2, and the second lightly doped breakdown voltage region 15, respectively. The polysilicon 6 is located in the trench 4, filling the trench 4 and in contact with the gate dielectric 5. The upper surface of the polysilicon 6 is horizontal with the upper surface of the gate trench 4. The gate dielectric 5 is made of SiO2 and its thickness is set to 40-500nm. In this embodiment, 80nm SiO2 is prepared using thermal oxidation technology as the gate dielectric 5, and polycrystalline silicon 6 is prepared using chemical vapor deposition.
[0021] In step S500, an isolation layer 7 is deposited on the epitaxial wafer 1, and a source trench 8 is fabricated by opening a window. The bottom of the source trench 8 extends into the interior of the adjacent first heavily doped region 2, and the trench width is greater than the spacing width of the first heavily doped region 2. (Refer to...) Figure 7 , Figure 8 As shown; Step S510: Prepare isolation layer 7 by chemical vapor deposition; protect the external area of source trench 8 by photolithography using a mask; and open a window at source trench 8 by etching. The bottom of source trench 8 extends into the interior of the first doped region 2, and the trench width is greater than the spacing width of the first doped region 2. Correspondingly, the isolation layer 7 serves a protective function. It is made of SiO2 or Si3N4 and has a thickness of 10-5000nm. The source trench 8 is prepared by ICP dry etching. The source trench 8 extends downward from the top surface of the isolation layer 7 into the interior of the first heavily doped region 2. Its bottom surface is higher than the bottom surface of the first heavily doped region 2. The trench width is greater than the spacing width of the first heavily doped region 2. The width range is set to 1-10um. The relevant parameter settings are related to the electrical design of the device. In this embodiment, Si3N4 is used as the isolation layer 7 with a thickness of 200nm. The source trench 8 is prepared by ICP dry etching with a depth of 2µm and a width of 1.5µm.
[0022] In step S600, a Schottky contact metal 9 is prepared at the bottom of the source trench 8 to form a Schottky contact with the second lightly doped breakdown region 15. The upper surface of the Schottky contact metal 9 is lower than the lower surface of the second heavily doped source region 3, as shown in the reference. Figure 9 As shown; In step S610, a Schottky contact metal 9 is prepared at the bottom of the source trench 8 by a stripping process or an etching process. The Schottky contact metal 9 forms a Schottky contact with the second lightly doped breakdown region 15. The upper surface of the Schottky contact metal 9 is lower than the lower surface of the second heavily doped source region 3. Correspondingly, the Schottky contact metal 9 is disposed at the bottom of the source trench 8 and forms a Schottky contact with the second lightly doped breakdown region 15, with its upper surface being lower than the lower surface of the second heavily doped source region 3. In this embodiment, a stripping process is used to prepare a 200nm thick Ni / Al double metal layer at the bottom of the source trench 8 as a Schottky contact metal 9, and Ni and the second lightly doped breakdown voltage region 15 form a Schottky contact.
[0023] Step S700: An ohmic contact metal 10 is prepared in the source trench 8 to form an ohmic contact with the first heavily doped region 2 and the second heavily doped source region 3. The ohmic contact metal 10 and the Schottky contact metal 9 together constitute the source metal in the source trench. (Refer to...) Figure 10 As shown; In step S710, an ohmic contact metal 10 is prepared in the source trench 8 by a stripping process or an etching process. The ohmic contact metal 10 forms an ohmic contact with the first doped region 2 and the second doped source region 3. The ohmic contact metal 10 and the Schottky contact metal 9 in the source trench together constitute the source metal. Correspondingly, the ohmic contact metal 10 is disposed inside the source trench 8, and its lower surface is horizontal with the upper surface of the Schottky contact metal 9 and the upper surface of the isolation layer 7, forming an ohmic contact with the first doped region 2 and the second doped source region 3. In this embodiment, a 1.8 μm thick Ti / Al double-layer metal is prepared in the source trench 8 as the ohmic contact metal 10, and Ti, the first doped region 2, and the second doped source region 3 form an ohmic contact.
[0024] In step S800, a window is opened at gate trench 4 to fabricate gate metal 12, and drain metal 13 is fabricated on the back side of epitaxial wafer 1. The entire device fabrication is now complete. Refer to... Figure 11 , Figure 12 , Figure 13 As shown.
[0025] In step S810, the external area of the opening of the gate trench 4 is protected by a mask through photolithography, the opening of the gate trench 4 is made by etching, and the gate metal 12 is prepared. The drain metal 13 is prepared at the bottom of the epitaxial wafer 1 through thinning and back gold processes, and the entire device is prepared. Correspondingly, the opening depth at the gate trench 4 is greater than the thickness of the isolation layer 7, the gate metal 12 extends downward from the top surface of the isolation layer 7 into the polysilicon 6, and forms an ohmic contact with the polysilicon 6, and the drain metal 13 forms an ohmic contact with the second heavily doped substrate region 14 on the bottom surface of the epitaxial wafer 1. In this embodiment, a window with a depth of 1 μm is opened at the gate trench 4 by etching process. A 1 μm thick Ti / Al double metal layer is prepared as gate metal 12 by peeling process to form an ohmic contact with polysilicon 6. The 350 μm thick epitaxial wafer 1 is thinned to 180 μm by thinning process. Drain metal 13 is prepared using Ti / Al double metal layer.
[0026] A MOSFET that enhances the freewheeling capability of a body diode includes a drain metal 13, an epitaxial wafer 1, and an isolation layer 7 arranged sequentially from bottom to top. The epitaxial wafer 1 contains: The first heavily doped region 2 is provided in a plurality of such regions, which extend downward from the top of the epitaxial wafer 1 and are spaced apart from each other; the top surface of the first heavily doped region 2 is lower than the top surface of the epitaxial wafer 1, and the bottom surface is higher than the bottom surface of the second lightly doped voltage-resistant region 15. The second doped source region 3 extends downward from the top surface of the epitaxial wafer 1 and connects to the top surface of the first doped body region 2. The gate dielectric 5 is provided in several U-shaped cross sections, extending downward from the top surface of the second heavily doped source region 3, passing through the first heavily doped body region 2, and extending into the second lightly doped breakdown voltage region 15; that is, the gate dielectric 5 is connected to the second heavily doped source region 3, the first heavily doped body region 2, and the second lightly doped breakdown voltage region 15 respectively. Polycrystalline silicon 6 extends downward from the top surface of the gate dielectric 5 and fills the gate dielectric 5; A Schottky contact metal 9 is disposed between adjacent first heavily doped regions 2, with its end extending into the first heavily doped region 2, meaning the lateral width of the Schottky contact metal 9 is greater than the spacing width between adjacent first heavily doped regions 2; the Schottky contact metal 9 is connected to the second lightly doped breakdown region 15 to form a Schottky contact; the upper surface of the Schottky contact metal 9 is lower than the lower surface of the second heavily doped source region 3; The ohmic contact metal 10 extends upward from the top surface of the Schottky contact metal 9 and passes sequentially through the first heavily doped region 2, the second heavily doped source region 3, and the isolation layer 7. Its upper surface is flush with the upper surface of the isolation layer 7. The ohmic contact metal 10 forms an ohmic contact with the first heavily doped region 2 and the second heavily doped source region 3, and together with the Schottky contact metal 9, it constitutes the source metal. The gate metal 12 extends downward from the top surface of the isolation layer 7 into the polysilicon 6, forming an ohmic contact with the polysilicon 6.
[0027] The drain metal 13 forms an ohmic contact with the second heavily doped substrate region 14 on the bottom surface of the epitaxial wafer 1.
[0028] The present invention has the following advantages: By fabricating a spaced first heavily doped body region 2 and controlling the depth of the source trench 8, a Schottky contact diode is integrated at the bottom of the source trench 8. Utilizing the low turn-on voltage and high current characteristics of the Schottky diode, the freewheeling loss of the body diode is reduced. Simultaneously, the second lightly doped breakdown voltage region 15 of the Schottky diode of this invention is flanked by spaced first heavily doped body regions 2, forming a superjunction structure of the first heavily doped body region 2, the second lightly doped breakdown voltage region 15, and the first heavily doped body region 2. The superjunction structure has excellent shielding properties, effectively reducing the electric field strength of the second lightly doped breakdown voltage region 15, thereby reducing the reverse leakage current of the integrated Schottky diode.
[0029] The structure of the second lightly doped breakdown voltage region 15 below the first heavily doped region 2 of the device of this invention is consistent with that of a conventional trench MOSFET. It does not require special additional process steps to reduce the reverse leakage current of the integrated Schottky diode. The fabrication process of this invention is fully compatible with the fabrication process of conventional trench MOSFETs. It only requires two additional process steps to fabricate the source trench 8 and the Schottky contact metal 9. Compared with existing prior art, this invention reduces the reverse leakage current of the integrated Schottky diode by reducing special additional process steps, without affecting the forward current carrying capacity of the integrated SBD and the MOSFET. This is conducive to the advancement of commercialization and has higher commercial value.
[0030] Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.
Claims
1. A method of fabricating a MOSFET with enhanced body diode freewheeling capability, characterized by, Includes the following steps: Step S100: Prepare mutually spaced first heavy doped regions (2) within the epitaxial wafer (1). Step S200: Prepare a second doped source region (3) in the epitaxial wafer (1); Step S300: A gate trench (4) is prepared in the epitaxial wafer (1). Step S400: Gate dielectric (5) and polysilicon (6) are sequentially prepared in the gate trench (4). Step S500: Deposit isolation layer (7) on epitaxial wafer (1), open window to prepare source trench (8), the bottom of source trench (8) extends into the interior of first doped region (2), and the width of source trench (8) is greater than the spacing width of first doped region (2); In step S600, a Schottky contact metal (9) is prepared at the bottom of the source trench (8) using a stripping process or an etching process. The Schottky contact metal (9) forms a Schottky contact with the second lightly doped breakdown region (15), and the end of the Schottky contact metal (9) extends into the first heavily doped body region (2), and its upper surface is lower than the lower surface of the second heavily doped source region (3). In step S700, an ohmic contact metal (10) is prepared in the source trench (8) using a stripping process or an etching process. The ohmic contact metal (10) and the Schottky contact metal (9) are stacked vertically, forming an ohmic contact only with the first doped region (2) and the second doped source region (3), and together with the Schottky contact metal (9), they form the source metal. The preparation sequence is Schottky contact metal (9) first, followed by ohmic contact metal (10), without the need for additional source contact metal preparation steps; In step S800, a window is opened at the gate trench (4) to prepare the gate metal (12). The drain metal (13) is prepared on the back side of the epitaxial wafer (1) through thinning and back gold processes. The entire device is then prepared.
2. The method of claim 1, wherein the MOSFET is a super-junction MOSFET. Step S100 includes: Step S110: Using photolithography, a mask is used to protect the outer region of the first doped region (2); through diffusion or ion implantation, several first doped regions (2) are formed that are spaced apart from each other.
3. The method of claim 1, wherein the MOSFET is a super-junction MOSFET. Step S200 includes: Step S210: Using photolithography, a mask is used to protect the outer region of the second doped source region (3); the second doped source region (3) is formed by diffusion or ion implantation.
4. The method of claim 1, wherein the MOSFET is a super-junction MOSFET. Step S300 includes: Step S310: Using photolithography, a mask is used to protect the outer area of the gate trench (4); and the gate trench (4) is formed by etching.
5. The method of claim 1, wherein the MOSFET is a super-junction MOSFET. Step S400 includes: Step S410: Using photolithography, a mask is used to protect the external area of the gate trench (4), and a gate dielectric (5) is prepared in the gate trench (4) using thermal oxidation technology. In step S420, polysilicon (6) is prepared in the gate trench (4) by chemical vapor deposition.
6. The method of claim 1, wherein the MOSFET is a super-junction MOSFET. Step S500 includes: Step S510: Prepare an isolation layer (7) by chemical vapor deposition, protect the outer area of the source trench (8) by photolithography using a mask, and open a window at the source trench (8) by etching. The bottom of the source trench (8) extends into the interior of the first doped region (2), and the width of the source trench (8) is greater than the spacing width of the first doped region (2).
7. The method of claim 1, wherein the MOSFET is a super-junction MOSFET. Step S800 includes: In step S810, the external area of the gate trench (4) is protected by a mask through photolithography, and a window is opened at the gate trench (4) through etching, and gate metal (12) is prepared. Drain metal (13) is prepared on the back side of the epitaxial wafer (1) using thinning and back gold processes, and the entire device is prepared.
8. A MOSFET with enhanced body diode freewheeling capability, fabricated by the method for fabricating a MOSFET with enhanced body diode freewheeling capability according to any one of claims 1-7, characterized in that, It includes a drain metal (13), an epitaxial wafer (1) and an isolation layer (7) arranged sequentially from bottom to top; The epitaxial wafer (1) contains: The first doped region (2) is provided in several parts, which extend downward from the top of the epitaxial wafer (1) and are spaced apart from each other; the bottom surface of the first doped region (2) is higher than the bottom surface of the second lightly doped voltage-resistant region (15); The second doped source region (3) extends downward from the top surface of the epitaxial wafer (1) and is connected to the top surface of the first doped body region (2); The gate dielectric (5) has several U-shaped cross sections, which extend downward from the top surface of the second heavily doped source region (3), pass through the first heavily doped body region (2), and extend into the second lightly doped breakdown voltage region (15); Polycrystalline silicon (6) extends downward from the top surface of the gate dielectric (5) and fills the gate dielectric (5); A Schottky contact metal (9) is disposed between adjacent first heavily doped regions (2), with its end extending into the first heavily doped region (2); the Schottky contact metal (9) is connected to the second lightly doped breakdown region (15) to form a Schottky contact; the upper surface of the Schottky contact metal (9) is lower than the lower surface of the second heavily doped source region (3); The ohmic contact metal (10) extends upward from the top surface of the Schottky contact metal (9) and is stacked vertically. It passes through the first doped region (2), the second doped source region (3) and the isolation layer (7) in sequence to form an ohmic contact with the first doped region (2) and the second doped source region (3), and together with the Schottky contact metal (9) forms the source metal. Gate metal (12) extends downward from the top surface of the isolation layer (7) into the polysilicon (6) and forms an ohmic contact with the polysilicon (6); The first and second doping regions have opposite doping types, namely P-region and N-region, or N-region and P-region, respectively; The first doped region includes a first heavily doped body region (2); the second doped region includes a second heavily doped source region (3), a second heavily doped substrate region (14), and a second lightly doped breakdown voltage region (15).