A gallium oxide device based on a radiation-cooling layer and its fabrication method

Abstract

This invention discloses a heat dissipation structure for gallium oxide devices using radiation cooling and its fabrication method. It primarily addresses the problems of severe self-heating, poor operational stability, and low reliability in existing gallium oxide devices due to the low thermal conductivity of gallium oxide itself. The key technology is to improve the heat dissipation performance of the device through radiation cooling. Specifically, a radiation cooling layer composed of multiple vertically stacked SiO2 / Si3N4 cylindrical structures is formed on the surface of the gallium oxide field-effect transistor, and a silver reflective layer is added to the substrate or below the radiation cooling layer. Heat is radiated to the outside of the device, thus improving its heat dissipation performance. For vertical gallium oxide Schottky diodes, a silver reflective layer that does not contact the metal electrode is directly grown on its Si3N4 passivation layer, and then a radiation cooling layer of the same shape is fabricated on the silver reflective layer. This invention effectively alleviates the self-heating effect of the device and improves its heat dissipation performance, making it suitable for use in microwave power devices and power electronic devices.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a gallium oxide device and its preparation method, which can be used as a microwave power device and a power electronic device. Background Technology

[0002] Ga2O3 is an ultra-wide bandgap semiconductor material, which can be classified into α-Ga2O3, β-Ga2O3, γ-Ga2O3, δ-Ga2O3, and ε-Ga2O3 based on different crystal structures. Among these different crystal structures, β-Ga2O3 is the most stable at room temperature and pressure and exhibits excellent chemical stability. Currently, most Ga2O3 devices use β-Ga2O3. Compared with third-generation semiconductor materials SiC and GaN, β-Ga2O3 possesses superior physical properties such as an ultra-wide bandgap of 4.8 eV and an ultra-high critical breakdown field of 8 MV / cm. Furthermore, Ga2O3 is the only wide bandgap semiconductor material that can be grown into wafers using a melt-grown process, which can significantly reduce wafer growth costs. Therefore, Ga2O3 has a natural low-cost advantage and is a strong competitor in the future electronic device field.

[0003] Ga2O3, as a key semiconductor material, performs exceptionally well in applications such as microwave power devices and power electronic devices. However, despite its numerous advantages, Ga2O3 has a relatively low thermal conductivity, only one-thirtieth that of SiC and one-tenth that of GaN. This low thermal conductivity limits the application of Ga2O3 in high-power and high-temperature environments. During high-power operation, insufficient heat dissipation can lead to a rapid temperature rise, which severely affects the device's electron mobility and stability. Furthermore, the thermal stress within the device caused by high temperatures can easily lead to device failure or shorten its lifespan. Therefore, addressing the low thermal conductivity of Ga2O3 is crucial for improving device performance and stability.

[0004] Patent document CN202311267759.1 discloses a Ga2O3LDMOSFET device with high heat dissipation performance and its fabrication method, such as... Figure 1As shown, from top to bottom, it includes: gate metal 8, high-k insulating layer 7, source metal 6, drain gold layer 5, N-channel region 4, N+ source region 3p-type light oxide drift region 2, and diamond insulating layer 1. That is, a lightly doped oxide drift layer is directly grown on a diamond substrate, followed by ion implantation to form the source / drain and channel regions. This method directly fabricates Ga2O3 devices on a diamond substrate, thereby enhancing the device's heat dissipation capability and improving its performance at high temperatures. However, the lattice matching between the oxide material and diamond is not ideal, which leads to an increase in lattice defects within the oxide material, preventing it from fully utilizing its material advantages. Furthermore, due to the large boundary thermal resistance between the high thermal conductivity substrate and Ga2O3, the device's heat dissipation performance needs further improvement. This method also directly fabricates Ga2O3 devices on a diamond substrate, thereby enhancing the device's heat dissipation capability and improving its performance at high temperatures. Nevertheless, due to the large boundary thermal resistance between the high thermal conductivity substrate and Ga2O3, the device's heat dissipation performance needs further improvement.

[0005] Patent application CN202311558965.8 discloses a double-sided heat dissipation gallium oxide chip flip-chip package structure and its fabrication method. This method uses flip-chip packaging to add high thermal conductivity materials to both sides of the device, aiding in heat dissipation and thus addressing the heat dissipation problem from the chip packaging perspective. However, the thermal conductivity of the materials used in this type of packaging is limited, and the heat dissipation effect needs further improvement.

[0006] Patent application CN202311555216.X discloses a diamond-based gallium oxide semiconductor structure and its fabrication method. A silicon carbide layer is prepared on a diamond substrate to form a diamond-silicon carbide composite structure, leveraging the high thermal conductivity of diamond and silicon carbide to enhance the heat dissipation capacity of the gallium oxide device. However, considering that gallium oxide is directly grown on the diamond-silicon carbide composite layer, due to factors such as lattice mismatch and thermal expansion coefficient mismatch, the lattice of the gallium oxide material may have many defects, resulting in a loss of electrical performance in the device. Summary of the Invention

[0007] The purpose of this invention is to address the shortcomings of the prior art by proposing a gallium oxide 3 device based on a radiation cooling layer and its fabrication method, so as to further improve the heat dissipation performance of the Ga2O3 device, avoid the loss of electrical performance and device failure due to thermal effects, and improve the reliability of the device.

[0008] The technical solutions for achieving the objectives of this invention include the following:

[0009] Technical Solution 1:

[0010] 1. A Ga2O3 metal-oxide-semiconductor field-effect transistor based on a radiation-cooling layer, comprising, from bottom to top: a substrate layer 2, a buffer layer 3, a channel layer 4, and a dielectric layer 5, wherein source, drain, and gate metal electrodes are disposed on the dielectric layer 5, and a passivation layer 6 is surrounding the metal electrodes, characterized in that:

[0011] A silver reflective layer 1 is provided on the lower surface of the substrate layer 2 to effectively conduct heat generated inside the device and improve heat reflection efficiency.

[0012] The passivation layer 6 has a radiation cooling layer 7 composed of multiple composite SiO2 / Si3N4 cylindrical structures between the metal electrodes on its upper surface, in order to enhance the heat dissipation performance of the device.

[0013] Furthermore, the silver reflective layer 1 is made of high metallic silver material with a thermal conductivity of 400~450 W / mK and a thickness of 1~15 µm.

[0014] Furthermore, in the radiation cooling layer 7, each of the SiO2 / Si3N4 cylindrical structures composited on the top and bottom has a thickness of 1~15 μm and a diameter of 4~50 μm, with a spacing of 5~30 μm between adjacent cylindrical structures. The composite cylindrical structure can also be composited with Si3N4 using any one of alumina, hafnium oxide or titanium oxide materials.

[0015] Furthermore, the substrate layer 2 is made of SiC or AlN, with a thickness of 150~600 μm; the buffer layer 3 is made of β-Ga2O3, with a thickness of 0.5~2.5 μm; the channel layer 4 is made of β-Ga2O3, with a thickness of 20~600 nm; and the dielectric layer 5 is made of Al2O3, NiO, Al2O3, or Hf. 0.5 Zr 0.5 O2, any one of the following, with a thickness of 20~260 nm; the passivation layer 6, using SiO2 or Si3N4, with a thickness of 80~250 nm.

[0016] Technical Solution 2:

[0017] A vertical Ga2O3 heterojunction diode based on a radiation-cooling layer, comprising, from bottom to top: a cathode electrode, an n+β-Ga2O3 substrate layer, an n-β-Ga2O3 epitaxial layer, a p-NiO dielectric layer, and an anode electrode, wherein the anode electrode is surrounded by a Si3N4 passivation layer, characterized in that:

[0018] Above the passivation layer, there are multiple SiO2 / Si3N4 cylindrical structures spaced 10-20 μm apart from the anode metal. Each cylindrical structure is composed of a radiation cooling layer and a silver reflective layer stacked on top of each other. The spacing between two adjacent cylindrical structures is 10-40 micrometers to reflect the heat generated inside the device and improve heat dissipation performance.

[0019] Further: Each SiO2 / Si3N4 cylindrical structure has a thickness of 1~15μm and a ring width of 10~50 μm, wherein the thickness of the silver reflective layer is 100~500nm and is located between the Si3N4 passivation layer and the radiation cooling layer.

[0020] Furthermore, the silver reflective layer is made of high metallic silver material with a thermal conductivity of 400~450 W / mK; the composite annular structure can also be made by combining any one of aluminum oxide, hafnium oxide or titanium oxide with Si3N4 in an upper and lower composite manner.

[0021] Furthermore, the n + The β-Ga₂O₃ substrate has a thickness of 400–650 μm, and is doped with either Si or Sn at a concentration of 1 × 10⁻⁶. 18 ~1×10 19 cm -3 The n - The thickness of the β-Ga2O3 epitaxial layer is 6~20 μm, and the doping element is Si or Sn with a doping concentration of 1×10⁻⁶. 15 ~1×10 17 cm -3 The p-NiO dielectric layer has a thickness of 200~600 nm, is doped with boron (B), and has a doping concentration of 1×10⁻⁶. 17 ~5×10 18 cm -3 The thickness of the Si3N4 passivation layer is 100~300 nm.

[0022] Technical Solution 3:

[0023] A method for preparing the above-mentioned Ga2O3 metal oxide semiconductor field-effect transistor, characterized by comprising the following steps:

[0024] S1) High-temperature annealing was used to heterobond the pre-prepared β-Ga2O3 wafer with buffer layer and channel layer to the substrate, and the β-Ga2O3 wafer was thinned by ion cutting.

[0025] S2) The surface of the channel layer is smoothed, and an epitaxial deposited medium layer is deposited on the channel layer;

[0026] S3) First, the pattern of the metal electrode is defined by photolithography on the channel layer and the dielectric layer. Then, the electrode metal is deposited on the channel layer and the dielectric layer by electron beam evaporation E-Beam and ion implantation isolation is performed to deposit a passivation layer.

[0027] S4) The upper surface of the passivation layer with deposited metal electrodes is bonded to an external carrier wafer using a bonding process;

[0028] S5) Thinning and surface polishing are performed on the back side of the substrate;

[0029] S6) An electron beam evaporation E-Beam deposition of a silver reflective layer is performed on the back side of the polished substrate;

[0030] S7) Remove the carrier wafer, define the radiation cooling layer pattern on the passivation layer using photolithography, and then fabricate the radiation cooling layer using plasma-enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD) to complete device fabrication. (Adding photolithography...)

[0031] Technical Solution Four:

[0032] A method for fabricating the above-mentioned vertical Ga2O3 heterojunction diode, characterized by comprising the following steps:

[0033] 1) Set n + The β-Ga2O3 substrate was first subjected to organic ultrasonic cleaning and then dried in an N2 environment;

[0034] 2) In n + n-Ga2O3 substrate was epitaxially deposited via metal-organic chemical vapor deposition (MOCVD) - β-Ga2O3 epitaxial layer;

[0035] 3) In n - A p-NiO dielectric layer is deposited on a β-Ga2O3 epitaxial layer using magnetron sputtering.

[0036] 4) In n + A cathode electrode was deposited on the back side of the β-Ga2O3 substrate by electron beam evaporation of E-beam, followed by rapid annealing to obtain good ohmic contact.

[0037] 5) The anode electrode region is first formed on the p-NiO dielectric layer by photolithography and development process, and then the anode electrode is deposited by electron beam evaporation of E-beam;

[0038] 6) A Si3N4 passivation layer is deposited around the anode electrode by atomic layer deposition (ALD);

[0039] 7) Define the silver reflective layer pattern above the passivation layer by photolithography, and deposit the silver reflective layer by electron beam evaporation (E-Beam) technology;

[0040] 8) On the Si3N4 passivation layer with the silver reflective layer, the radiation cooling layer pattern consistent with the silver reflective layer is defined by photolithography, and the SiO2 / Si3N4 composite layer is prepared by plasma enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD) respectively to complete the device fabrication.

[0041] Compared with the prior art, the present invention has the following advantages:

[0042] 1) In the second technical solution of the present invention, since a radiation cooling layer is prepared on the passivation layer, the heat inside the device can be absorbed. Unlike microchannels, there is no need to add an additional water pump to achieve water circulation, nor is it necessary to contact the conductive channel material. The heat can be radiated to the outside of the device efficiently. Furthermore, the heat generated by the device can be absorbed and reflected by the multilayer radiation material, effectively reflecting the heat generated by the device to the external environment and improving the heat dissipation performance of the device.

[0043] 2) In the first technical solution of the present invention, a silver reflective layer is prepared under the substrate, which can reflect part of the heat to the surface radiation cooling layer, thereby improving the heat reflection efficiency. At the same time, metallic silver has a good thermal conductivity, which can help reflect heat while improving the thermal conductivity of the substrate, thereby further improving the heat dissipation performance of the device.

[0044] 3) In technical solution 2 of the present invention, since a radiation cooling layer is prepared around the anode of the gallium oxide Schottky diode and the silver reflective layer is prepared directly below the radiation cooling layer, the thermal conductivity of the device surface is greatly improved, and the speed at which heat inside the device is radiated to the outside is also increased.

[0045] 3) The radiation cooling layer of the present invention adopts multiple cylindrical structures of upper and lower composite SiO2 / Si3N4, which does not need to be in direct contact with the Ga2O3 epitaxial layer. This not only has no impact on the quality of the epitaxial layer, but also can more effectively reduce the thermal resistance of the device. Furthermore, it can effectively avoid lattice mismatch and damage to the Ga2O3 material caused by high thermal conductivity materials. It can greatly improve the heat dissipation performance of the device while achieving excellent electrical performance.

[0046] 4) By directly integrating the radiative cooling layer on the front side of the device, this invention achieves a shorter heat propagation path, improves the overall heat dissipation efficiency of the device, facilitates device integration, helps reduce the size and weight of the equipment, reduces the process complexity of the device, and improves the reliability, stability and overall electrical performance of the device. Attached Figure Description

[0047] Figure 1 is a structural diagram of an existing GaO LDMOSFET device;

[0048] Figure 2 This is a schematic diagram of the structure of the device in technical solution 1 of the present invention;

[0049] Figure 3 This is a schematic diagram of the structure of the device in technical solution 2 of the present invention;

[0050] Figure 4 This is a schematic diagram of the manufacturing process of the device in technical solution 1 of the present invention;

[0051] Figure 5 This is a schematic diagram of the manufacturing process of the device in technical solution 2 of the present invention. Detailed Implementation

[0052] This invention relates to Ga2O3 metal-oxide-semiconductor devices based on radiation-cooling layers, including Ga2O3 metal-oxide-semiconductor field-effect transistors, vertical Ga2O3 heterojunction diodes, and their respective fabrication methods. The following detailed description of these two device structures and their fabrication methods, in conjunction with the accompanying drawings and embodiments, further illustrates these inventions.

[0053] Reference Figure 2 This invention relates to a Ga2O3 metal-oxide-semiconductor field-effect transistor based on a radiation-cooling layer, comprising a silver reflective layer 1, a substrate layer 2, a buffer layer 3, a channel layer 4, a dielectric layer 5, a passivation layer 6, a radiation-cooling layer 7, and a source electrode (S), a drain electrode (D), and a gate electrode (G). Wherein:

[0054] The substrate layer 2 is made of SiC or AlN and has a thickness of 200~650 μm.

[0055] The buffer layer 3 is made of β-Ga2O3 with a thickness of 0.3~2.5 μm and is located on the substrate layer 2.

[0056] The channel layer 4 is made of β-Ga2O3 with a thickness of 20~600 nm and is located above the buffer layer 3.

[0057] The dielectric layer 5 is made of Al2O3 or NiO or Al2O3 and Hf. 0.5 Zr 0.5 O2, with a thickness of 20~200 nm, is located above channel layer 4.

[0058] The source electrode S and drain electrode D are made of Ti / Au with a thickness of 20~60 / 80~2000 nm, and are located above the channel layer 4;

[0059] The gate G is made of Ni / Au with a thickness of 20~60 / 60~2000 nm, and it is located on the dielectric layer 5 between the source S and the drain D.

[0060] The passivation layer 6 is made of SiO2 or Si3N4 and has a thickness of 80~200 nm. It surrounds the source S, drain D and gate G.

[0061] The silver reflective layer 1 is located below the substrate layer 2, and its thickness is 0.1~15 μm;

[0062] The radiation cooling layer is formed by arranging multiple vertically composited SiO2 / Si3N4 cylindrical structures at a spacing of 5–30 μm to enhance the heat dissipation performance of the device. Each vertically composited SiO2 / Si3N4 cylindrical structure has a thickness of 1–15 μm and a diameter of 4–50 μm. This composite cylindrical structure can also be formed by combining any one of alumina, hafnium oxide, or titanium oxide with Si3N4, and it is located on the upper surface of the passivation layer.

[0063] Reference Figure 3 This invention relates to a vertical Ga2O3 heterojunction diode based on a radiation-cooling layer, comprising cathode electrodes 1 and n. + β-Ga2O3 substrate layer 2,n - 3. β-Ga2O3 epitaxial layer, 4. p-NiO dielectric layer, 5. anode electrode, 6. Si3N4 passivation layer, 7. silver reflective layer, and 8. radiation cooling layer, wherein:

[0064] The n + β-Ga2O3 substrate layer 1, with a thickness of 400~600 μm.

[0065] The cathode electrode 2 is made of Ti / Au with a thickness of 20~60 / 80~300 nm, and it is located at n + Back side of β-Ga2O3 substrate.

[0066] The n - β-Ga2O3 epitaxial layer 3, with a thickness of 6~20 μm, is located at n + On top of the β-Ga2O3 substrate.

[0067] The p-NiO dielectric layer 4 has a thickness of 300~600 nm and is located in the n - Above the β-Ga2O3 epitaxial layer.

[0068] The anode electrode 5 is made of Ni / Au with a thickness of 20~60 / 60~2000 nm, and it is located on the p-NiO dielectric layer.

[0069] The Si3N4 passivation layer has a thickness of 100~300 nm and is wrapped around the anode electrode.

[0070] The silver reflective layer 7 is made of high metallic silver material with a thermal conductivity of 400~450 W / mK. It consists of multiple silver reflective cylinders distributed in a ring on the upper part of the Si3N4 passivation layer. Each silver reflective cylinder has a thickness of 100~500 nm and a diameter of 4~50 μm. The distance between the cylinder and the anode electrode is 10~20 μm, and the distance between adjacent silver reflective cylinders is 20~50 μm.

[0071] The radiation-cooling layer 8 is composed of multiple SiO2 / Si3N4 radiation-cooling cylinders stacked vertically. Each radiation-cooling SiO2 / Si3N4 cylinder has a thickness of 1~20 μm and a diameter the same as the silver reflective cylinder, and is located on top of the silver reflective cylinder. Besides using a composite layer of silicon dioxide and silicon nitride, this radiation-cooling composite cylindrical structure can also use any one of aluminum oxide, hafnium oxide, or titanium oxide materials stacked vertically with Si3N4.

[0072] Reference Figure 4 This invention provides three embodiments for fabricating Ga2O3 metal-oxide-semiconductor field-effect transistors that utilize radiation cooling to improve heat dissipation performance; however, the embodiments of this invention are not limited to these. Unless otherwise specified, the experimental methods described in the following embodiments are conventional methods; and unless otherwise specified, the reagents and materials are commercially available.

[0073] Example 1: A silver reflective layer with a thickness of 10 μm and a thermal conductivity of 426 W / mK is fabricated on a SiC substrate; the radiation cooling layer is a SiO2 / Si3N4 composite layer with a thickness of 1.5 μm; and the dielectric layer is a Ga2O3 metal oxide semiconductor field-effect transistor with a thickness of 20 nm of Al2O3.

[0074] Step 1: The pre-prepared β-Ga2O3 wafer with buffer layer 5 and channel layer 6 is heterobonded to substrate 2 using high-temperature annealing, and the β-Ga2O3 wafer is thinned by ion cutting, as follows: Figure 4 (a).

[0075] 1.1) A series of organic ultrasonic cleaning processes were performed on a 500 µm thick SiC substrate 2. First, acetone was used for cleaning for 10 minutes, followed by isopropanol for 10 minutes, and finally deionized water for 5 minutes. Throughout the cleaning process, the ultrasonic power was maintained at 120 W. After cleaning, the surface of the SiC substrate 2 was dried using nitrogen gas.

[0076] 1.2) Select a pre-prepared β-Ga2O3 wafer, the structure of which includes an unintentionally doped β-Ga2O3 buffer layer with a thickness of 0.8 μm and a 500 μm thick layer with a doping concentration of 2×10⁻⁶. 17 cm -3H ions are implanted on one side of the β-Ga2O3 channel layer 4 to form defects in the β-Ga2O3 wafer at a distance of 1.5 μm from the surface of the buffer layer 3.

[0077] 1.3) The front side of the SiC substrate 2 is subjected to Ar ion bombardment treatment for 1 min to form an amorphous layer. Then, the front side of the SiC substrate 2 and one side of the β-Ga2O3 wafer buffer layer 3 are bonded by high-temperature annealing in a vacuum at a temperature of 800℃ for 45 s.

[0078] 1.4) The annealed wafer is annealed again at a temperature of 800℃ in an N2 environment for 30 min to remove the β-Ga2O3 wafer from the defect and leave a buffer layer 3 with a thickness of 0.8 μm and a channel layer 4 with a thickness of 0.7 μm on the surface of the SiC substrate 2.

[0079] Step 2: Smooth the surface of the channel layer 4, and epitaxially grow the dielectric layer 5 on the channel layer 4, such as... Figure 4 (b).

[0080] 2.1) The surface of the channel layer 4 was ground and polished using chemical mechanical polishing (CMP) technology to reduce the thickness of the channel layer 4 to 0.3 μm;

[0081] 2.2) Using atomic layer deposition (ALD) technology, an Al2O3 dielectric layer 5 with a thickness of 25 nm was deposited on the channel layer 4 under the process conditions of reaction chamber temperature of 325℃ and pressure of 1.5 mbar.

[0082] Step 3: Deposit source (S), drain (D), and gate (G) metals on channel layer 4 and dielectric layer 5 respectively, and perform ion implantation to achieve isolation. Deposit passivation layer 8, as shown below. Figure 4 (c).

[0083] 3.1) Photolithography is performed on the surface of dielectric layer 5. First, a layer of photoresist is spin-coated on the surface of dielectric layer 5, and then alignment, exposure, development, and pattern detection are performed in sequence to form the active region from the source S to the drain D of the device.

[0084] 3.2) The dielectric layer 5 outside the active region is etched using inductively coupled plasma etching (ICP) technology. The etching needs to reach the channel layer 4. Then, the wafer is placed in the photoresist stripping solution to remove the photoresist.

[0085] 3.3) The surface of the channel layer 4 is patterned using photolithography to form the source and drain regions. Ion implantation doping is then performed on the channel layer 4 between the source and drain regions to reduce the resistance of the source and drain regions. The doping element is Si, and the doping concentration is 6 × 10⁻⁶. 18 cm-3 ;

[0086] 3.4) E-Beam is evaporated by electron beam, and the working chamber is evacuated to 2.0 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 9 kV, electron gun beam current of 0.3 A, and evaporation time of 1200 s, Ti / Au with a thickness of 50 / 1500 nm is deposited in the source and drain regions as source (S) and drain (D), and then the wafer with evaporated metal is placed in photoresist stripping solution to remove photoresist.

[0087] 3.5) The wafers with completed source S and drain D metal deposition were subjected to rapid thermal annealing in an N2 environment for 60 s at an annealing temperature of 850℃ to form good ohmic contact at the contact surfaces of the source, drain and channel layer 4.

[0088] 3.6) The gate region is formed again by photolithography on the surface of dielectric layer 5, and E-Beam is evaporated by electron beam evaporation. The vacuum level in the working chamber is then reduced to 2.0 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 9 kV, electron gun beam current of 0.3 A, and evaporation time of 1100 s, Ni / Au with a thickness of 40 / 1200 nm is deposited in the gate region as gate G to form a Schottky contact at the interface between gate G and dielectric layer 5. Then the wafer is placed in photoresist stripping solution to remove the photoresist.

[0089] 3.7) Ion implantation technology was used, with an implantation energy of 320 keV and an ion concentration of 1×10⁻⁶. 15 cm -2 Under the given process conditions, high-energy ion implantation is performed on the surface of the channel layer 4 outside the active region of the wafer to complete device isolation;

[0090] 3.8) Under the conditions of a reaction chamber temperature of 300°C and a pressure of 2.6 mbar, an atomic layer deposition (ALD) technique is used to epitaxially grow a Si3N4 passivation layer 6 with a thickness of 100 nanometers on the channel layer 4 and dielectric layer 5 surrounding the source S, drain D and gate G.

[0091] Step 4: The surface of the passivation layer 6 is bonded to the sapphire wafer 202 via a high-temperature paraffin layer 201, and pressure is applied to perform bonding. Figure 4 (d).

[0092] Step 5: Process the back side of SiC substrate 2, such as... Figure 4 (e).

[0093] 5.1) The SiC substrate 2, on which the device is fabricated with substrate layer 2, buffer layer 3, channel layer 4, dielectric layer 5, passivation layer 6, source S, drain D, and gate G, is thinned to reduce its thickness to 200 μm.

[0094] 5.2) The thinned SiC substrate 2 is back-side polished using polishing technology to improve the smoothness and flatness of the wafer surface.

[0095] Step 6: Fabricate a silver reflective layer on the back side of the substrate. For example... Figure 4 (f).

[0096] E-Beam was evaporated using an electron beam, with the chamber evacuated to a vacuum of 3×10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 9 kV, electron gun beam current of 0.6 A, and evaporation time of 5000 s, a 10 μm thick Ag metal layer was deposited on the back side of Si substrate 2 as a back silver reflective layer 1.

[0097] Step 7: Remove the carrier wafer. Define the radiation cooling layer pattern on the passivation layer 6 between the metal electrodes using photolithography. Protect the metal electrodes by covering them with photoresist 301, and then grow the material for the radiation cooling layer. Figure 4 (g).

[0098] 7.1) Use a dewaxing solution to remove the sapphire substrate 202 bonded to the surface of the passivation layer.

[0099] 7.2) First, spin-coat a layer of photoresist onto the surface of passivation layer 6, then perform alignment, exposure, development and pattern inspection to cover the metal electrode layer with photoresist and define the pattern of radiation layer 7.

[0100] 7.3) Based on the defined radiation layer pattern, using plasma chemical vapor deposition (PECVD) technology, under the conditions of maintaining a temperature of 300°C and a pressure of 1.3 mbar in the reaction chamber, multiple SiO2 layers with a thickness of 0.75 µm and a diameter of 12 µm are epitaxially grown along the passivation layer 6 surrounding the source S, drain D and gate G covered with photoresist, with a spacing of 12 µm.

[0101] 7.4) Using atomic layer deposition (ALD) technology, under the conditions of maintaining a temperature of 300°C and a pressure of 1.3 mbar in the reaction chamber, a Si3N4 layer with a thickness of 0.75 µm and a diameter of 12 μm is epitaxially grown on each passivation layer 6 covered with photoresist source S, drain D and gate G, forming multiple columnar SiO2 / Si3N4 radiation layers, and then transferred to the surface of passivation layer 6.

[0102] Step 8: Remove excess SiO2 / Si3N4 composite layer using a stripping process to form radiation cooling layer 7, such as... Figure 4 (h).

[0103] The wafer with the grown radiation layer 7 is placed in a photoresist stripping solution for stripping to remove excess SiO2 / Si3N4 composite layers, forming a radiation cooling layer 7 consisting of multiple composite columnar radiation layers. This completes the device fabrication.

[0104] Example 2: A silver reflective layer with a thickness of 12 μm and a thermal conductivity of 428 W / mK was fabricated on an AlN substrate; the radiation cooling layer was an HfO2 / Si3N4 composite layer with a thickness of 2 μm; the dielectric layer was 100 nm NiO; and a Ga2O3 metal oxide semiconductor field-effect transistor with a heterojunction was fabricated.

[0105] Step 1: The pre-prepared β-Ga2O3 wafer with buffer layer 3 and channel layer 4 is heterobonded to substrate 2 using high-temperature annealing, and the β-Ga2O3 wafer is thinned by ion cutting, as follows: Figure 4 (a).

[0106] A series of organic ultrasonic cleaning processes were performed on the 500-micrometer-thick AlN substrate 2. First, acetone was used for cleaning for 10 minutes, followed by isopropanol for 10 minutes, and finally deionized water for 5 minutes. Throughout the cleaning process, the ultrasonic power was maintained at 120 W. After cleaning, the surface of the AlN substrate 2 was dried using nitrogen (N2).

[0107] A pre-prepared β-Ga₂O₃ wafer was selected, the structure of which includes an unintentionally doped β-Ga₂O₃ buffer layer with a thickness of 0.8 μm and a 500 μm thick layer with a doping concentration of 2 × 10⁻⁶. 17 cm -3 H ions are implanted on one side of the β-Ga2O3 channel layer 4 to form defects in the β-Ga2O3 wafer at a distance of 1.5 μm from the surface of the buffer layer 3.

[0108] Ar ion bombardment was performed on the front side of AlN substrate 2 for 1 min to form an amorphous layer. Then, the front side of AlN substrate 2 and one side of β-Ga2O3 wafer buffer layer 3 were bonded by high-temperature annealing in vacuum at a temperature of 800℃ for 60 s.

[0109] The annealed wafer was annealed again at a temperature of 500℃ in an N2 environment for 120 min to remove the β-Ga2O3 wafer from the defect and leave a buffer layer 3 with a thickness of 0.6 μm and a channel layer 4 with a thickness of 0.5 μm on the surface of AlN substrate 2.

[0110] Step 2: Smooth the surface of the channel layer 4, and epitaxially grow the dielectric layer 5 on the channel layer 4, such as... Figure 4 (b).

[0111] The vacuum level in the deposition chamber is set to 5.6 × 10⁻⁶. -4 Under the process conditions of 1.5 Pa growth pressure and 26 W sputtering power, a 100 nm thick p-type NiO dielectric layer 5 with a doping concentration of 1 × 10⁻⁶ W was deposited on the channel layer 4 using magnetron sputtering technology. 18 cm -3 .

[0112] Chemical mechanical polishing (CMP) technology was used to grind and polish the surface of the channel layer 4 to reduce the thickness of the channel layer 4 to 0.2 μm.

[0113] Step 3: Deposit source (S), drain (D), and gate (G) metals on channel layer 4 and dielectric layer 5 respectively, perform ion implantation isolation, and deposit passivation layer 6, as shown below. Figure 4 (c).

[0114] Photolithography is performed on the surface of dielectric layer 5. First, a layer of photoresist is spin-coated on dielectric layer 5, and then alignment, exposure, development, and pattern detection are performed in sequence to form the active region from the source S to the drain D of the device.

[0115] The dielectric layer 5 outside the active region is etched using inductively coupled plasma etching (ICP) technology until the channel layer 4 is exposed. After etching, the photoresist stripping solution is used for photoresist removal.

[0116] Photolithography was performed on the surface of channel layer 4 to form source and drain regions. Subsequently, these source and drain regions were ion-implanted for doping to reduce their resistance. The element used in the doping process was Si, with a doping concentration of 5 × 10⁻⁶. 18 cm -3 ;

[0117] Set the vacuum level of the working chamber to 2.0 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 8 kV, electron gun beam current of 0.6 A, and evaporation time of 1500 s, Ti / Au with a thickness of 40 / 1500 nm was deposited in the source and drain regions as source (S) and drain (D) by electron beam evaporation of E-Beam. After the metal deposition was completed, excess photoresist and metal were removed using photoresist stripping solution.

[0118] The wafer with completed source (S) and drain (D) metal deposition was placed in an annealing furnace and rapidly annealed for 60 seconds in an N2 environment at a temperature of 800°C to form good ohmic contact at the contact surfaces of the source, drain, and channel layer 4.

[0119] The gate region was formed by secondary photolithography on the surface of dielectric layer 5, with the vacuum level of the working chamber set to 2.0 × 10⁻⁶. -4 Under the process conditions of 9 kV electron gun accelerating voltage, 0.6 A electron gun beam current, and 1200 s evaporation time, Ni / Au with a thickness of 50 / 1500 nm was deposited as the gate G in the gate region by electron beam evaporation of E-Beam, so as to form a good Schottky contact at the interface between the gate G and the dielectric layer 5. After the metal deposition was completed, the photoresist was removed using a photoresist stripping solution.

[0120] A second photolithography step is performed on the surface of dielectric layer 5 to form the gate region; then the vacuum level of the working chamber is set to 2.0 × 10⁻⁶. -4 Under the process conditions of 9 kV electron gun accelerating voltage, 0.6 A electron gun beam current, and 1200 seconds evaporation time, a 50 / 1500 nm Ni / Au metal layer was deposited in the gate region using electron beam evaporation (E-Beam) technology as the gate G, thereby forming a good Schottky contact at the interface between the gate G and the dielectric layer 5. After metal deposition, a photoresist stripping solution was used to remove residual photoresist.

[0121] The injection energy was set at 320 keV and the ion concentration at 1×10⁻⁶. 15 cm -2 Under the specified process conditions, ion implantation technology is used to perform high-energy ion implantation on the surface of the channel layer 4 outside the active region of the wafer to complete device isolation;

[0122] With the reaction chamber temperature set at 400℃ and the pressure at 3 mbar, an atomic layer deposition (ALD) technique was used to epitaxially grow a 140 nm thick SiO2 passivation layer 6 on the channel layer 4 and dielectric layer 5 surrounding the source S, drain D, and gate G.

[0123] Step 4: The surface of the passivation layer 6 is bonded to the sapphire wafer 202 via a high-temperature paraffin layer 201, and pressure is applied to perform bonding. Figure 4 (d).

[0124] Step 5: Process the back side of AlN substrate 2, such as... Figure 4 (e).

[0125] The back side of the AlN substrate 2 containing the substrate layer 2, buffer layer 3, channel layer 4, dielectric layer 5, passivation layer 6, source S, drain D and gate G is thinned by grinding to reduce its thickness to 300 μm.

[0126] Polishing technology was used to polish the back side of the thinned AlN substrate 2 to improve the surface smoothness and flatness of the wafer.

[0127] Step 6: Deposit silver reflective layer 1 on the back side of substrate 2, as follows Figure 4 (f).

[0128] Vacuum the studio to 3×10 -4 Under the process conditions of setting the electron gun acceleration voltage to 9 kV, the electron gun beam current to 0.6 A, and the evaporation time to 6000 s, a 12 μm thick Ag metal layer was deposited on the back side of the Si substrate 2 as a back silver reflective layer 1 by evaporating E-Beam with an electron beam.

[0129] Step 7: Remove the carrier wafer. Define the radiation cooling layer pattern on the passivation layer 6 between the metal electrodes using photolithography. Protect the metal electrodes by covering them with photoresist 301, and then grow the material for the radiation cooling layer. Figure 4 (g).

[0130] The sapphire substrate 202 bonded to the surface of the passivation layer was removed using a dewaxing solution.

[0131] First, a layer of photoresist is spin-coated onto the surface of passivation layer 6. Then, alignment, exposure, development, and pattern inspection are performed to cover the metal electrode layer with photoresist and define the pattern of radiation layer 7.

[0132] With the reaction chamber temperature set at 300℃ and the pressure at 1.3 mbar, multiple HfO2 layers with a thickness of 1 µm and a diameter of 20 μm were epitaxially grown along the passivation layer 6 surrounding the source S, drain D and gate G covered with photoresist at a spacing of 15 μm.

[0133] With the reaction chamber temperature set at 300℃ and the pressure at 1.3 mbar, atomic layer deposition (ALD) technology was used to epitaxially grow a Si3N4 layer with a thickness of 1 µm and a diameter of 20 μm on each HfO2 layer along the passivation layer 6 covering the photoresist source S, drain D and gate G, forming multiple HfO2 / Si3N4 composite pillar material layers.

[0134] Step 8: Remove excess SiO2 / Si3N4 composite layer using a stripping process to form radiation cooling layer 8, such as... Figure 4 (h).

[0135] The wafer with the radiation layer 7 is placed in the photoresist stripping solution to remove excess SiO2 / Si3N4 composite layer, and a radiation layer cooling 7 is formed on the surface of the passivation layer 6, thus completing the device fabrication.

[0136] In Example 3, a silver reflective layer with a thickness of 2 μm and a thermal conductivity of 429 W / mK was fabricated on a SiC substrate; the radiation cooling layer was a SiO2 / Si3N4 composite layer with a thickness of 1.2 μm; and the dielectric layers were Al2O3 with thicknesses of 10 nm and Hf, respectively. 0.5 Zr 0.5 A Ga2O3 metal oxide semiconductor field-effect transistor with an O2 thickness of 20 nm.

[0137] Step A: The β-Ga2O3 wafer with the prepared buffer layer 3 and channel layer 4 is heterobonded to the substrate 2 using high-temperature annealing, and the β-Ga2O3 wafer is thinned by ion cutting, as follows: Figure 4 (a).

[0138] A1) A series of organic ultrasonic cleaning processes were performed on a 500 μm thick SiC substrate 2. First, acetone was used for cleaning for 10 minutes, followed by isopropanol for 10 minutes, and finally deionized water for 5 minutes. Throughout the cleaning process, the ultrasonic power was maintained at 120 W. After cleaning, the surface of the SiC substrate 2 was dried using nitrogen gas.

[0139] A2) Select a pre-prepared β-Ga2O3 wafer, the structure of which includes an unintentionally doped β-Ga2O3 buffer layer with a thickness of 0.8 μm and a 500 μm thick layer with a doping concentration of 2 × 10⁻⁶. 17 cm -3 H ions are implanted on one side of the β-Ga2O3 channel layer 4 to form defects in the β-Ga2O3 wafer at a distance of 1.5 μm from the surface of the buffer layer 3.

[0140] A3) The front side of the SiC substrate 2 is subjected to Ar ion bombardment treatment for 1 min to form an amorphous layer. Then, the front side of the SiC substrate 2 and one side of the β-Ga2O3 wafer buffer layer 3 are bonded by high-temperature annealing in a vacuum at a temperature of 800℃ for 45 s.

[0141] A4) The annealed wafer is annealed again at a temperature of 800℃ in an N2 environment for 30 min to remove the β-Ga2O3 wafer from the defect and leave a buffer layer 3 with a thickness of 0.8 μm and a channel layer 4 with a thickness of 0.7 μm on the surface of the SiC substrate 2.

[0142] Step B: Smooth the surface of the channel layer 4, and epitaxially grow the dielectric layer 5 on the channel layer 4, such as... Figure 4 (b).

[0143] B1) The surface of the channel layer 4 was ground and polished using chemical mechanical polishing (CMP) technology, reducing the thickness of the channel layer 4 from 0.7 μm to 0.35 μm;

[0144] B2) Using atomic layer deposition (ALD) technology, a 10 nm thick layer of Al2O3 and a 20 nm thick layer of Hf were sequentially deposited on channel layer 4. 0.5 Zr 0.5 O2 is used as the dielectric layer 5, and the process conditions for atomic layer deposition (ALD) are as follows:

[0145] The process conditions for atomic layer deposition (ALD) of Al2O3 were: reaction chamber temperature of 360℃ and reaction chamber pressure of 1.7 mbar.

[0146] Deposition of Hf 0.5 Zr 0.5 The process conditions for atomic layer deposition (ALD) of O2 were: reaction chamber temperature of 260℃ and reaction chamber pressure of 2.7 mbar.

[0147] Step C: Deposit source (S), drain (D), and gate (G) metals on channel layer 4 and dielectric layer 5 respectively for ion implantation isolation, and deposit passivation layer 6, as follows. Figure 4 (c).

[0148] C1) Photolithography is performed on the surface of dielectric layer 5, that is, firstly, a layer of photoresist is spin-coated on dielectric layer 5, and then alignment, exposure, development, and pattern detection are performed in sequence to form the active region from the source S to the drain D of the device.

[0149] C2) The dielectric layer 5 outside the active region is etched using inductively coupled plasma etching (ICP) technology. The etching depth is required to reach the channel layer 4. After etching, photoresist stripping solution is used for photoresist removal.

[0150] C3) Photolithography is performed on the surface of channel layer 4 to form source and drain regions. Ion implantation doping is then performed on the channel layer 4 in the source and drain regions to reduce the resistance of the source and drain regions. The doping element is Si, and the doping concentration is 4 × 10⁻⁶. 18 cm -3 ;

[0151] C4) Electron beam evaporation of E-Beam is used to deposit Ti / Au with a thickness of 50 / 1500 nm as the source (S) and drain (D) regions. After metal deposition, the wafer is placed in a photoresist stripping solution to remove excess photoresist. The process conditions for electron beam evaporation of E-Beam are as follows:

[0152] The vacuum level of the work chamber is 2.0 × 10⁻⁶. -4 Pa,

[0153] The electron gun accelerating voltage is 9 kV.

[0154] The electron gun beam current is 0.7 A.

[0155] The evaporation time is 1000 s;

[0156] C5) Place the wafer with completed source and drain metal deposition into a rapid thermal annealing furnace and anneal it rapidly for 60 seconds in an N2 environment at a temperature of 750°C to form good ohmic contact at the contact surface of the source, drain and channel layer 4.

[0157] C6) The surface of dielectric layer 5 is photolithographically etched again to form the gate region. E-Beam is evaporated by electron beam to deposit a Ni / Au layer with a thickness of 40 / 1500 nm as the gate G in the gate region, so as to form a Schottky contact at the interface between the gate G and dielectric layer 5. The wafer is then placed in photoresist stripping solution to remove the photoresist. The process conditions for electron beam evaporation of E-Beam are as follows:

[0158] The vacuum level of the work chamber is 2.0 × 10⁻⁶. -4 Pa,

[0159] The electron gun accelerating voltage is 8 kV.

[0160] The electron gun beam current is 0.7 A.

[0161] The evaporation time is 1000 s;

[0162] C7) Ion implantation technology is used to perform high-energy ion implantation on the surface of the channel layer 4 outside the active region of the wafer to complete device isolation. The ion implantation process conditions are as follows:

[0163] The injected energy was 330 keV.

[0164] The ion concentration is 1×10 15 cm -2 ;

[0165] C8) Using atomic layer deposition (ALD) technology, a SiO2 passivation layer 6 with a thickness of 180 nm is epitaxially grown on the channel layer 4 and dielectric layer 5 surrounding the source (S), drain (D), and gate (G). The ALD process conditions are as follows:

[0166] The temperature of the reaction chamber is 360℃.

[0167] The pressure in the reaction chamber is 3.5 mbar.

[0168] Step D: The surface of the passivation layer 6 is bonded to the sapphire wafer 202 via a high-temperature paraffin layer 201, and pressure is applied to perform bonding. Figure 4 (d).

[0169] Step E: Process the back side of SiC substrate 2, such as... Figure 4 (e).

[0170] E1) The back side of the SiC substrate 2, on which the device is fabricated with substrate layer 2, buffer layer 3, channel layer 4, dielectric layer 5, passivation layer 6, source S, drain D, and gate G, is thinned by grinding to reduce its thickness to 260 μm.

[0171] E2) Polishing technology is used to polish the back side of the thinned SiC substrate 2 to improve the smoothness and flatness of the wafer surface.

[0172] Step F: Fabricate a silver reflective layer on the back side of the substrate. For example... Figure 4 (f).

[0173] A 2 μm thick metallic Ag layer was deposited on the back side of Si substrate 2 as a back silver reflective layer 1 by electron beam evaporation of E-Beam. The process conditions for electron beam evaporation of E-Beam are as follows.

[0174] The vacuum level of the work chamber is 2.0 × 10⁻⁶. -4 Pa,

[0175] The electron gun accelerating voltage is 8 kV.

[0176] The electron gun beam current is 0.7 A.

[0177] The evaporation time is 1000 s.

[0178] Step G: Remove the carrier wafer, and use photolithography to define the radiation cooling layer pattern on the passivation layer 6 between the metal electrodes. Protect the metal electrodes by covering them with photoresist 301, and then grow the material for the radiation cooling layer, such as... Figure 4 (g).

[0179] G1) Use a dewaxing solution to remove the sapphire substrate 202 bonded to the surface of the passivation layer;

[0180] G2) First, spin-coat a layer of photoresist onto the surface of passivation layer 6, then perform alignment, exposure, development and pattern inspection, cover the metal electrode layer with photoresist, and define the pattern of radiation layer 7.

[0181] G3) Using plasma-enhanced chemical vapor deposition (PECVD) technology, multiple SiO2 layers with a thickness of 0.6 µm and a diameter of 45 μm are epitaxially grown along the passivation layer 6 surrounding the source (S), drain (D), and gate (G) covered with photoresist, with a spacing of 5 μm. The process parameters of the plasma-enhanced chemical vapor deposition (PECVD) technology are as follows:

[0182] SiH4 and N2O are the precursor gases;

[0183] The flow velocities were 80 cm. 3 / min, 160 cm 3 / min;

[0184] The reaction chamber is maintained at 300°C.

[0185] The pressure in the reaction chamber is 1.3 mbar;

[0186] The radio frequency power is 100 W;

[0187] Deposition time: 750 s;

[0188] G4) Using atomic layer deposition (ALD) technology, multiple Si3N4 layers with a thickness of 0.6 µm and a diameter of 45 μm are epitaxially grown along the passivation layer 6 covering the photoresist source (S), drain (D), and gate (G) at 5 μm intervals. The process parameters for ALD technology are as follows:

[0189] The temperature of the reaction chamber is 360℃;

[0190] The reaction chamber pressure is 3.5 mbar;

[0191] The deposition time was 750 s.

[0192] Step H: Remove excess SiO2 / Si3N4 composite layer using a stripping process to form radiation cooling layer 7, such as... Figure 4 (h).

[0193] The wafer with the radiation layer 7 is placed in a photoresist stripping solution to remove excess SiO2 / Si3N4 composite layer, forming a radiation cooling layer and completing the device fabrication.

[0194] Reference Figure 5 This invention provides three embodiments for fabricating vertical Ga2O3 heterojunction diodes based on radiation-cooling layers, but the implementation of this invention is not limited to these. Unless otherwise specified, the experimental methods described in the following embodiments are conventional methods; the reagents and materials described are commercially available unless otherwise specified.

[0195] Example 4: A vertical Ga2O3 heterojunction diode with a silver reflective layer thickness of 100 nm and a thermal conductivity of 425 W / mK was fabricated; the radiation cooling layer was a SiO2 / Si3N4 composite layer with a thickness of 1.5 μm.

[0196] Step 1: Clean the substrate, such as Figure 5 (a).

[0197] A thickness of 500 μm was selected. The Si doping concentration is 5×10⁻⁶. 18 cm -3 n + The β-Ga2O3 substrate was first ultrasonically cleaned with acetone solution for 10 minutes, then transferred to isopropanol solution for ultrasonic cleaning for 10 minutes, and finally ultrasonically cleaned with deionized water for 10 minutes. The ultrasonic power was 100 W. After cleaning, the substrate surface was dried with N2.

[0198] Step 2: Deposit the epitaxial layer, such as Figure 5 (b).

[0199] Metal-organic chemical vapor deposition (MOCVD) technology was employed under the following process conditions: an O2 to TMGa flow rate ratio of 20, a temperature of 610℃, and a growth pressure of 56 mbar. + A 10 μm thick Si doping layer was deposited on a β-Ga2O3 substrate with a Si doping concentration of 1×10⁻⁶. 16 cm -3 n - β-Ga2O3 epitaxial layer.

[0200] Step 3: Deposition of the medium layer, such as Figure 5 (c).

[0201] Using magnetron sputtering technology, the reaction chamber was first evacuated to a vacuum of 5.6 × 10⁻⁶. -4 Under process conditions of Pa, growth pressure of 1.6 Pa, and sputtering power of 30 W, and then at n - The β-Ga2O3 epitaxial layer has a deposition thickness of 300 nm and a doping concentration of 1×10⁻⁶. 18 cm -3 p-NiO dielectric layer.

[0202] Step 4: Fabricate the cathode electrode, such as Figure 5 (d).

[0203] (4.1) E-beam was evaporated by electron beam, and the working chamber was evacuated to 2.0 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 9 kV, electron gun beam current of 0.3 A, and evaporation time of 250 s, first in n + A Ti / Au cathode electrode with a thickness of 50 / 200 nm was deposited on the back side of a β-Ga2O3 substrate;

[0204] (4.2) The wafer with the cathode electrode deposited is placed in an annealing furnace and rapidly annealed in a N2 environment at a furnace temperature of 475 ℃ for 60 s, so as to deposit the cathode electrode and the N2 atmosphere. + The β-Ga2O3 substrate forms a good ohmic contact at the interface.

[0205] Step 5: Fabricate the anode electrode, such as... Figure 5 (e).

[0206] (5.1) Photolithography is performed on the surface of the p-NiO dielectric layer. First, a layer of photoresist is spin-coated on the p-NiO dielectric layer, and then alignment, exposure, development, and pattern detection are performed in sequence to form the anode region of the device.

[0207] (5.2) E-Beam was evaporated by electron beam, and the evacuation chamber was evacuated to a vacuum of 2.5 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 9 kV, electron gun beam current of 0.4 A, and evaporation time of 1200 s, a Ni / Au anode electrode with a thickness of 50 / 1200 nm was deposited in the anode region to form a Schottky contact at the interface between the anode electrode and the p-NiO dielectric layer. After the metal deposition was completed, the wafer was stripped with a photoresist stripping solution to remove excess photoresist and metal.

[0208] Step 6: Using atomic layer deposition (ALD) technology, under process conditions of 300℃ and 1.5 mbar in the reaction chamber, a 150 nm thick Si3N4 passivation layer is deposited around the anode electrode. Figure 5 (f).

[0209] Step 7: Create a silver reflective layer, such as... Figure 5 (g).

[0210] (7.1) Photolithography is performed on the dielectric layer on which the anode metal has been grown. First, photoresist is spin-coated on the surface of the dielectric layer, and then alignment, exposure, development, and pattern detection are performed in sequence to form a circular silver reflective layer pattern, which is located between the anode metal and does not contact the metal.

[0211] (7.2) E-beam was evaporated by electron beam, and the working chamber was evacuated to 2.6 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 9 kV, electron gun beam current of 0.3 A, and evaporation time of 100 s, a 100 nm thick layer of metallic silver was deposited on the dielectric layer. After the metal deposition was completed, the wafer was stripped with photoresist stripping solution to remove excess photoresist and metal, forming a silver reflective layer with a thickness of 100 nm, a diameter of 10 μm, and a spacing of 40 μm between adjacent silver pillars.

[0212] Step 8: Deposit a radiation-cooling layer, such as Figure 5 (h).

[0213] (8.1) Photolithography is performed on the dielectric layer on which the anode metal and silver reflective layer have been grown. First, photoresist is spin-coated on the surface of the dielectric layer, and then alignment, exposure, development, and pattern detection are performed in sequence to form a radiation cooling layer pattern that coincides with the pattern of the silver reflective layer.

[0214] (8.2) Using plasma chemical vapor deposition (PECVD) technology, under the conditions of maintaining a temperature of 300℃ and a pressure of 1.3 mbar in the reaction chamber, a SiO2 layer with a thickness of 0.75 µm, a diameter of 10 μm and a spacing of 40 μm is epitaxially grown along the dielectric layer surrounding the anode metal covered with photoresist.

[0215] (8.3) Using atomic layer deposition (ALD) technology, under the conditions of maintaining a temperature of 300℃ and a pressure of 1.3 mbar in the reaction chamber, a Si3N4 layer with a thickness of 0.75 µm, a diameter of 10 μm and a spacing of 40 μm is epitaxially grown along the dielectric layer covering the periphery of the photoresist anode metal.

[0216] (8.4) The wafer with the radiation cooling layer is placed in the photoresist stripping solution for photoresist removal to remove excess photoresist and SiO2 / Si3N4 composite layer, thereby realizing the fabrication of the radiation cooling layer on the silver reflective layer on the surface of the dielectric layer and completing the device fabrication.

[0217] Example 5: A vertical Ga2O3 heterojunction diode with a silver reflective layer thickness of 300 nm and a thermal conductivity of 429 W / mK was fabricated; the radiation cooling layer was an HfO2 / Si3N4 composite with a thickness of 2 μm was fabricated.

[0218] 1: Clean the substrate, such as Figure 5 (a).

[0219] A thickness of 650 μm was selected. Sn doping concentration is 5×10 18 cm -3 n + The β-Ga2O3 substrate was first ultrasonically cleaned with acetone solution for 10 minutes, then transferred to isopropanol solution for ultrasonic cleaning for 10 minutes, and finally ultrasonically cleaned with deionized water for 10 minutes. The ultrasonic power was 100 W. After cleaning, the substrate surface was dried with N2.

[0220] 2: Deposited epitaxial layer, such as Figure 5 (b).

[0221] Metal-organic chemical vapor deposition (MOCVD) was employed, with process conditions set as follows: O2 to TMGa flow rate ratio of 30, temperature of 680℃, and growth pressure of 65 mbar.+ A 15 μm thick Sn doping layer was grown on a β-Ga2O3 substrate with a Sn doping concentration of 2 × 10⁻⁶. 16 cm -3 n - β-Ga2O3 epitaxial layer.

[0222] 3: Depositional medium layer, such as Figure 5 (c).

[0223] Magnetron sputtering technology was used, and the vacuum level of the reaction chamber was set to 6×10⁻⁶. -4 Under process conditions of Pa, growth pressure of 2.5 Pa, and sputtering power of 35 W, at n - The β-Ga2O3 epitaxial layer has a surface growth thickness of 350 nm and a doping concentration of 6 × 10⁻⁶. 18 cm -3 p-NiO dielectric layer.

[0224] 4: Fabricate the cathode electrode, such as Figure 5 (d).

[0225] E-beam was evaporated using an electron beam, with the working chamber vacuum level set to 2.0 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 7 kV, electron gun beam current of 0.6 A, and evaporation time of 1500 s, at n + A Ti / Au cathode electrode with a thickness of 50 / 1500 nm was deposited on the back side of the β-Ga2O3 substrate; the wafer was then placed in a rapid thermal annealing furnace, and the furnace temperature was set to 475℃ and rapidly annealed in an N2 environment for 60 s to form a good ohmic contact on the back side of the gallium oxide substrate.

[0226] 5: Fabricate the anode electrode, such as Figure 5 (e).

[0227] To perform photolithography on the surface of the p-NiO dielectric layer, first spin-coat a layer of photoresist onto the p-NiO dielectric layer, and then perform alignment, exposure, development, and pattern detection to form the anode region of the device.

[0228] Set the evaporation chamber to a vacuum level of 2.5 × 10⁻⁶. -4 The process conditions are as follows: Pa, electron gun accelerating voltage of 7 kV, electron gun beam current of 0.4 A, and evaporation time of 1500 s. Then, electron beam evaporation is used to deposit a Ni / Au anode electrode with a thickness of 50 / 1500 nm in the anode region to form a Schottky contact at the interface between the anode electrode and the p-NiO dielectric layer. After the metal deposition is completed, the wafer is stripped with photoresist stripping solution to remove excess photoresist and metal.

[0229] 6. Using atomic layer deposition (ALD) technology, with process conditions set at a reaction chamber temperature of 350℃ and a pressure of 5 mbar, a 200 nm thick Si3N4 passivation layer was deposited around the anode electrode. Figure 5 (f).

[0230] 7: Create a silver reflective layer, such as Figure 5 (g).

[0231] Photolithography is performed on the dielectric layer on which the anode metal has already grown. First, photoresist is spin-coated onto the surface of the dielectric layer, and then alignment, exposure, development, and pattern detection are performed in sequence to form a circular silver reflective layer pattern, which is located between the anode metal and does not contact the metal.

[0232] Set the working chamber to a vacuum level of 2.6 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 9 kV, electron gun beam current of 0.3 A, and evaporation time of 300 s, a 300 nm thick layer of metallic silver was deposited on the dielectric layer by electron beam evaporation of E-beam.

[0233] After metal deposition, the wafer is stripped using a photoresist stripping solution to remove excess photoresist and metal, forming a silver reflective layer with a thickness of 300 nm, a diameter of 20 μm, and a spacing of 30 μm between adjacent silver pillars.

[0234] 8: Deposited radiation cooling layer, such as Figure 5 (h).

[0235] Photolithography is performed on the dielectric layer on which the anode metal and silver reflective layer have already grown. First, photoresist is spin-coated on the surface of the dielectric layer, and then alignment, exposure, development, and pattern detection are performed in sequence to form a radiation-cooled layer pattern that coincides with the pattern of the silver reflective layer.

[0236] With process conditions of 300℃ and 1.3 mbar in the reaction chamber, a 1 µm thick HfO2 layer was epitaxially grown along the dielectric layer surrounding the anode metal covered with photoresist using plasma chemical vapor deposition (PECVD).

[0237] The process conditions of maintaining the reaction chamber temperature at 300℃ and the pressure at 1.3 mbar are maintained. Then, using atomic layer deposition (ALD) technology, a Si3N4 layer with a thickness of 1 µm is epitaxially grown along the dielectric layer covering the photoresist anode metal periphery.

[0238] The wafer with the radiation-cooling layer is placed in a photoresist stripping solution to remove excess photoresist and the HfO2 / Si3N4 composite layer, thus fabricating the radiation-cooling layer on the silver reflective layer on the surface of the dielectric layer. Each radiation cooler is located above a cylindrical silver reflective layer, with the pattern consistent with the silver reflective layer and a diameter of 20 μm. The spacing between adjacent radiation-cooling layers is 30 μm, completing the device fabrication.

[0239] Example 6: A vertical Ga2O3 heterojunction diode with a silver reflective layer thickness of 500 nm and a radiation cooling layer of TiO2 / Si3N4 composite layer thickness of 1.2 μm was fabricated.

[0240] Step 1: Clean the substrate, such as... Figure 5 (a).

[0241] A thickness of 600 μm and a Si doping concentration of 3 × 10⁻⁶ were selected. 18 cm -3 n + The β-Ga2O3 substrate was first ultrasonically cleaned with acetone solution for 10 minutes, then transferred to isopropanol solution for ultrasonic cleaning for 10 minutes, and finally ultrasonically cleaned with deionized water for 10 minutes. The ultrasonic power was 100 W. After cleaning, the substrate surface was dried with N2.

[0242] Step 2: Ga2O3 epitaxial layer deposition, such as Figure 5 (b).

[0243] Using metal-organic chemical vapor deposition (MOCVD) technology, in n + A 7.5 μm thick Sn doping layer was deposited on a β-Ga2O3 substrate with a Sn doping concentration of 2 × 10⁻⁶. 16 cm -3 n - The β-Ga2O3 epitaxial layer, wherein the process conditions used for metal-organic chemical vapor deposition (MOCVD) are as follows:

[0244] The growth pressure is 60 mbar.

[0245] The flow rate ratio of O2 to TMGa is 10.

[0246] The temperature is 640℃.

[0247] Step 3: Deposit a p-NiO dielectric layer, such as Figure 5 (c).

[0248] Using magnetron sputtering technology, in n - The β-Ga2O3 epitaxial layer has a surface growth thickness of 500 nm and a doping concentration of 1×10⁻⁶. 18 cm -3The p-NiO dielectric layer, wherein the magnetron sputtering process conditions are as follows:

[0249] The vacuum level of the magnetron sputtering chamber is 5.6 × 10⁻⁶. -4 Pa,

[0250] The growth pressure is 1 Pa.

[0251] The sputtering power is 28 W.

[0252] Step 4: Fabricate the cathode electrode, such as... Figure 5 (d).

[0253] (4-1) Electron beam evaporation of E-beam is used in n + A Ti / Au cathode electrode with a thickness of 60 / 1000 nm was deposited on the back side of a β-Ga2O3 substrate, wherein the electron beam evaporation process conditions for the E-beam were as follows:

[0254] The vacuum level of the work chamber is 2.0 × 10⁻⁶. -4 Pa,

[0255] The electron gun accelerating voltage is 8 kV.

[0256] The electron gun beam current is 0.4 A.

[0257] The evaporation time is 1000 s;

[0258] (4-2) After the cathode metal deposition is completed, the wafer is placed in a rapid thermal annealing furnace for annealing. In an N2 environment, the furnace temperature is set to 470℃ and annealing is performed for 60 s to form the cathode electrode and n + Good ohmic contact between β-Ga2O3 substrates.

[0259] Step 5: Fabricate the anode electrode, such as... Figure 5 (e).

[0260] (5-1) First, a layer of photoresist is spin-coated on the p-NiO dielectric layer, and then alignment, exposure, development and pattern detection are performed in sequence to photolithographically form the anode region of the device on the surface of the p-NiO dielectric layer.

[0261] (5-2) A Ni / Au layer with a thickness of 50 / 1000 nm was deposited in the anode region by electron beam evaporation of E-Beam to form a Schottky contact between the anode electrode and the gallium oxide epitaxial layer. The process conditions used for electron beam evaporation of E-Beam are as follows:

[0262] The vacuum level of the work chamber is 2.0 × 10⁻⁶. -4 Pa,

[0263] The electron gun accelerating voltage is 8 kV.

[0264] The electron gun beam current is 0.4 A.

[0265] The evaporation time is 1000 s;

[0266] (5-3) Place the wafer with the deposited anode electrode into the photoresist stripping solution to remove the photoresist.

[0267] Step 6: Using atomic layer deposition (ALD) technology, a 180 nm thick Si3N4 passivation layer is deposited around the anode electrode, such as... Figure 5 (f), where the process conditions for atomic layer deposition (ALD) are:

[0268] The temperature of the reaction chamber is 350℃.

[0269] The pressure is 2.5 mbar.

[0270] Step 7: Create a silver reflective layer, such as... Figure 5 (g).

[0271] (7-1) Photolithography is performed on the dielectric layer on which the anode metal has been grown. That is, photoresist is first spin-coated on the surface of the dielectric layer, and then alignment, exposure, development and pattern detection are performed in sequence to form a circular silver reflective layer pattern, which is located between the anode metal and does not contact the metal.

[0272] (7-2) Electron beam evaporation was used to deposit a 500 nm thick layer of metallic silver on the dielectric layer. After the metal deposition was completed, the wafer was stripped using a photoresist stripping solution to remove excess photoresist and metal, forming a cylindrical silver reflective layer with a diameter of 25 μm and a spacing of 25 μm between adjacent silver pillars. The electron beam evaporation process conditions were as follows:

[0273] The vacuum level of the work chamber is 2.0 × 10⁻⁶. -4 Pa,

[0274] The electron gun accelerating voltage is 8 kV.

[0275] The electron gun beam current is 0.4 A.

[0276] The evaporation time is 500 s.

[0277] Step 8: Deposit a radiation-cooling layer, such as Figure 5 (h).

[0278] (8-1) Photolithography is performed on the dielectric layer on which the anode metal and silver reflective layer have been grown. That is, photoresist is first spin-coated on the surface of the dielectric layer, and then alignment, exposure, development and pattern detection are performed in sequence to form a radiation cooling layer pattern that coincides with the pattern of the silver reflective layer.

[0279] (8-2) Using atomic layer deposition (ALD) technology, a TiO2 layer with a thickness of 0.6 µm is first epitaxially grown along the dielectric layer covering the photoresist anode metal periphery, and then a Si3N4 layer with a thickness of 0.6 µm is epitaxially grown along the dielectric layer covering the photoresist anode metal periphery. The process conditions for atomic layer deposition (ALD) are as follows:

[0280] The reaction chamber temperature is 300℃;

[0281] The reaction chamber pressure is 1.3 mbar.

[0282] Deposition time: 600 s;

[0283] (8-3) The wafer with the radiation cooling layer is placed in the photoresist stripping solution for photoresist removal to remove excess photoresist and TiO2 / Si3N4 composite layer, thereby realizing the fabrication of the radiation cooling layer on the silver reflective layer on the surface of the dielectric layer. Each radiation cooler is located above the cylindrical silver reflective layer, with the pattern consistent with the silver reflective layer and a diameter of 25 μm. The spacing between adjacent radiation cooling layers is 25 μm, thus completing the device fabrication.

[0284] The above descriptions are merely six specific examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and detail without departing from the principles and results of the present invention. For example, in addition to using SiO2 / Si3N4 composite layers and HfO2 / Si3N4 composite layers, TiO2 / Si3N4 composite layers and Al2O3 / Si3N4 composite layers can also be used for the radiation cooling layer. Furthermore, the present invention can employ multiple composite layers to form a radiation cooling layer, such as a SiO2 / Si3N4 / SiO2 / Si3N4 multilayer composite layer. However, these modifications and changes based on the concept of the present invention are still within the protection scope of the present invention.

Claims

1. A Ga2O3 metal-oxide-semiconductor field-effect transistor based on a radiation cooling layer, comprising, from bottom to top: a substrate layer (2), a buffer layer (3), a channel layer (4), and a dielectric layer (5), wherein source, drain, and gate metal electrodes are disposed on the dielectric layer (5), and a passivation layer (6) is wrapped around the metal electrodes, characterized in that: A silver reflective layer (1) is provided on the lower surface of the substrate layer (2) to effectively conduct the heat generated inside the device and improve the heat reflection efficiency; The passivation layer (6) has a radiation cooling layer (7) composed of multiple vertically composite SiO2 / Si3N4 cylindrical structures between the metal electrodes on its upper surface to enhance the heat dissipation performance of the device. The radiation cooling layer (7) has a thickness of 1~15 μm and a diameter of 4~50 μm for each of its upper and lower composite SiO2 / Si3N4 cylindrical structures, and the spacing between adjacent cylindrical structures is 5~30 μm. The cylindrical structure can also be composited with Si3N4 using any one of alumina, hafnium oxide or titanium oxide materials.

2. The Ga2O3 metal-oxide-semiconductor field-effect transistor based on a radiation-cooling layer according to claim 1, characterized in that: The silver reflective layer (1) is made of high metallic silver material with a thermal conductivity of 400~450 W / mK and a thickness of 1~15 µm.

3. The Ga2O3 metal-oxide-semiconductor field-effect transistor based on a radiation-cooling layer according to claim 1, characterized in that: The substrate layer (2) is made of SiC or AlN and has a thickness of 150~600 μm; The buffer layer (3) is made of β-Ga2O3 and has a thickness of 0.5~2.5 μm; The channel layer (4) is made of β-Ga2O3 and has a thickness of 20~600 nm. The medium layer (5) is made of any one of Al2O3, NiO, Hf 0.5 Zr 0.5 O2, with a thickness of 20-260 nm; The passivation layer (6) is made of SiO2 or Si3N4 and has a thickness of 80~250 nm.

4. A vertical Ga2O3 heterojunction diode based on a radiation cooling layer, comprising, from bottom to top: a cathode electrode (1), an n+β-Ga2O3 substrate layer (2), an n-β-Ga2O3 epitaxial layer (3), a p-NiO dielectric layer (4), and an anode electrode (5), wherein the anode electrode (5) is surrounded by a Si3N4 passivation layer (6), characterized in that: Above the passivation layer, there are multiple SiO2 / Si3N4 cylindrical structures spaced 10~20μm apart from the anode metal. Each cylindrical structure is composed of a radiation cooling layer (8) and a silver reflective layer (7) stacked on top of each other. The spacing between two adjacent cylindrical structures is 10~40μm to reflect the heat generated inside the device and improve heat dissipation performance.

5. The vertical Ga2O3 heterojunction diode based on a radiation-cooling layer according to claim 4, characterized in that: Each SiO2 / Si3N4 cylindrical structure has a thickness of 1~15μm and a ring width of 10~50μm, wherein the silver reflective layer (7) has a thickness of 100~500nm and is located between the Si3N4 passivation layer (6) and the radiation cooling layer (8).

6. The vertical Ga2O3 heterojunction diode based on a radiation-cooling layer according to claim 4, characterized in that: The silver reflective layer (7) is made of high metallic silver material with a thermal conductivity of 400~450 W / mK. The cylindrical structure can also be formed by combining Si3N4 with any one of aluminum oxide, hafnium oxide, or titanium oxide materials.

7. The vertical Ga2O3 heterojunction diode based on a radiation-cooling layer according to claim 4, characterized in that: The n + The thickness of the β-Ga2O3substrate layer (2) is 400 to 650 μm, the doping element is Si or Sn, and the doping concentration is 1 x 10 18 ~1 x 10 19 cm -3 ; The n - The thickness of the β-Ga2O3 epitaxial layer (3) is 6~20 μm, and the doping element is Si or Sn with a doping concentration of 1×10⁻⁶. 15 ~1×10 17 cm -3 ; The p-NiO dielectric layer has a thickness of 200~600 nm, and the doping element is bo, with a doping concentration of 1×10⁻⁶. 17 ~5×10 18 cm -3 ; The thickness of the Si3N4 passivation layer (6) is 100~300 nm.

8. A method for preparing the Ga2O3 metal oxide semiconductor field-effect transistor of claim 1, characterized in that, Includes the following steps: S1) High-temperature annealing was used to heterobond the pre-prepared β-Ga2O3 wafer with buffer layer and channel layer to the substrate, and the β-Ga2O3 wafer was thinned by ion cutting. S2) The surface of the channel layer is smoothed, and an epitaxial deposited medium layer is deposited on the channel layer; S3) First, the pattern of the metal electrode is defined by photolithography on the channel layer and the dielectric layer. Then, the electrode metal is deposited by electron beam evaporation E-Beam and ion implantation isolation is performed to deposit a passivation layer. S4) The upper surface of the passivation layer with deposited metal electrodes is bonded to an external carrier wafer using a bonding process; S5) Thinning and surface polishing are performed on the back side of the substrate; S6) An electron beam evaporation E-Beam deposition of a silver reflective layer is performed on the back side of the polished substrate; S7) Remove the carrier wafer, define the radiation cooling layer pattern on the passivation layer by photolithography, and then prepare the radiation cooling layer by plasma-enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD) to complete the device fabrication.

9. The method according to claim 8, characterized in that: The electron beam evaporation of E-Beam in step S3) is performed under the following conditions: the working chamber is evacuated to 2.0 × 10⁻⁶. -4 Pa, electron gun accelerating voltage is 8~10 kV, electron gun beam current is 0.2~0.8 A, and evaporation time is 200~2000 s; The electron beam evaporation of E-Beam in step S6) is performed under the following conditions: the working chamber is evacuated to 2.5 × 10⁻⁶. -4 Pa, electron gun accelerating voltage is 6~10 kV, electron gun beam current is 0.3~1 A, and evaporation time is 500~6000 s; In step S7), the plasma-enhanced chemical vapor deposition (PECVD) process conditions are as follows: SiH4 and N2O are used as precursor gases, and the flow rates are maintained at 40-80 cm⁻¹, respectively. 3 / min, 160~220 cm 3 The growth rate was maintained at 260~300℃, the growth pressure at 75~100 Pa, and the RF power at 60~100 W.

10. A method for manufacturing the vertical Ga2O3 heterojunction diode as described in claim 5, characterized in that, Includes the following steps: 1) Set n + The β-Ga2O3 substrate was first subjected to organic ultrasonic cleaning and then dried in an N2 environment; 2) In n + n-Ga2O3 substrate was epitaxially deposited via metal-organic chemical vapor deposition (MOCVD) - β-Ga2O3 epitaxial layer; 3) In n - A p-NiO dielectric layer is deposited on a β-Ga2O3 epitaxial layer using magnetron sputtering. 4) In n + A cathode electrode was deposited on the back side of the β-Ga2O3 substrate by electron beam evaporation of E-beam, followed by rapid annealing to obtain good ohmic contact. 5) The anode electrode region is first formed on the p-NiO dielectric layer by photolithography and development process, and then the anode electrode is deposited by electron beam evaporation of E-beam; 6) A Si3N4 passivation layer is deposited around the anode electrode by atomic layer deposition (ALD); 7) Define the silver reflective layer pattern above the passivation layer by photolithography, and deposit the silver reflective layer by electron beam evaporation (E-Beam) technology; 8) On the Si3N4 passivation layer with the silver reflective layer, the radiation cooling layer pattern consistent with the silver reflective layer is defined by photolithography, and the SiO2 / Si3N4 composite layer is prepared by plasma enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD) respectively to complete the device fabrication.

11. The method according to claim 10, characterized in that: The metal-organic chemical vapor deposition (MOCVD) process in step 2) is as follows: TMGa is used as the precursor of Ga, O2 is used as the oxygen source, N2 is used as the carrier gas, the flow rate ratio of O2 to TMGa is 10~40, the temperature is maintained at 500~700℃, and the growth pressure is maintained at 55~75 mbar. The magnetron sputtering process in step 3) has the following conditions: the deposition chamber is evacuated to 5~6×10⁻⁶ ppm. -4 Pa, growth pressure maintained at 1~2.5 Pa, sputtering power set at 20~35 W; The electron beam evaporation of E-beam in steps 4) and 5) is performed under the following conditions: the working chamber is evacuated to 2.0 × 10⁻⁶. -4 Pa, electron gun accelerating voltage is 6~10 kV, electron gun beam current is 0.2~0.75 A, and evaporation time is 100~2000 s; The electron beam evaporation of E-beam in step 7) is performed under the following conditions: the working chamber is evacuated to a vacuum of 2.6 × 10⁻⁶. -4 Pa, electron gun accelerating voltage is 6~10 kV, electron gun beam current is 0.25~1 A, and evaporation time is 200~2500 s.

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