An ultrawideband multilayer vertical interconnect structure based on glass-based SiP packaging

Abstract

This invention relates to the field of radio frequency front-end technology, specifically disclosing an ultra-wideband multilayer vertical interconnect structure based on glass-based SiP packaging. The structure includes a first dielectric layer with a signal line 1, a second dielectric layer with a signal line 2, dielectric layer units disposed between the first and second dielectric layers, signal vias for signal lines 1 and 2, and grounding shielding structures disposed on the outer sides of both signal lines 1 and 2. The first dielectric layer, dielectric layer units, and second dielectric layer are stacked. The projections of signal lines 1 and 2 onto the second dielectric layer are perpendicular to each other. Pad structures are disposed on the outer side of each dielectric layer through the signal vias. An air cavity corresponding to the pad structure position is disposed on the second dielectric layer. This invention reduces signal transmission loss across multiple layers and improves signal transmission performance in the link by adding a cavity below the vertical interconnect structure and using a high-low impedance structure.

Description

Technical Field

[0001] This invention relates to the field of radio frequency front-end technology, and more specifically, to an ultra-wideband multilayer vertical interconnect structure based on glass-based SiP packaging. Background Technology

[0002] With the rapid development of communication technology, the design of radio frequency (RF) circuits not only requires smaller size but also higher signal speed, power capacity, and integration density. SiP (System-in-Package) technology integrates bare chips with different functions onto a substrate in 2D and 3D methods to achieve chip-based system integration. Three-dimensional interconnects manufactured using glass vias have unique advantages in the field of RF chip integration due to their low loss, low cost, and high density, making them a hot topic in high-frequency chip 3D packaging. For SiP packaging, multiple chips are stacked together in a three-dimensional manner. This requires creating vias and copper interconnects between different chip layers to enable communication between chips. Because the physical dimensions of these copper vias differ from those of the signal lines, their characteristic impedance differs, resulting in impedance discontinuities, increased insertion loss, and reduced return loss, thus affecting the transmission of RF signals.

[0003] Traditional vertical interconnect structures based on low-temperature co-fired ceramic (LTCC) technology suffer from high insertion loss and low return loss, with the return loss deteriorating rapidly at high frequencies, making it difficult to meet the broadband and high-frequency requirements of RF integrated circuits. Although through-silicon via (TSV) technology offers superior performance compared to LTCC, it requires an insulating layer between the upper and lower surfaces of the silicon wafer and the copper wiring for isolation. Furthermore, copper atoms may penetrate the silicon dioxide insulating layer during the TSV manufacturing process, leading to a decrease in the performance of the packaged device or even its failure. The process is complex and has a low yield. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an ultra-wideband multilayer vertical interconnect structure based on glass-based SiP packaging. By adding a cavity below the vertical interconnect structure and using a high-low impedance structure, the loss of signal lines transmitted across multiple layers is reduced, and the signal transmission performance in the link is improved.

[0005] The solution adopted by this invention to solve the technical problem is:

[0006] An ultra-wideband multilayer vertical interconnect structure based on glass-based SiP packaging includes a first dielectric layer with a signal line one, a second dielectric layer with a signal line two, a dielectric layer unit disposed between the first dielectric layer and the second dielectric layer, signal vias for the signal line one and the signal line two, and grounding shielding structures disposed on the outside of both the signal line one and the signal line two; the first dielectric layer, the dielectric layer unit, and the second dielectric layer are stacked.

[0007] The projections of signal line one and signal line two on the second dielectric layer are perpendicular to each other; a pad structure is provided on the outer side of each dielectric layer; an air cavity corresponding to the position of the pad structure is provided on the second dielectric layer.

[0008] In some possible implementations, it also includes metal ground planes disposed on the upper and lower sides of the first dielectric layer, the second dielectric layer, and the dielectric layer unit; wiring is respectively laid on the metal ground plane on the top surface of the first dielectric layer and on the metal ground plane on the top surface of the second dielectric layer.

[0009] In some possible implementations, there is no grounding metal on the metal ground layer of the second dielectric layer at the location corresponding to the air cavity.

[0010] In some possible implementations, the pad structure includes a pad and an anti-pad located between the pad and the metal ground layer; multiple sets of pad structures are coaxially arranged; signal line one is connected to a pad on the first dielectric layer; signal line two is connected to a pad on the second dielectric layer.

[0011] In some possible implementations, the grounding shielding structure includes a shielding hole one disposed outside the anti-pad, a shielding hole two disposed outside the signal line one and symmetrically disposed along its axis, and a shielding hole three disposed outside the signal line two and symmetrically disposed along its axis.

[0012] In some possible implementations, the shielding via includes multiple sets of first shielding vias A disposed outside the anti-pad corresponding to signal line 1 and penetrating the first dielectric layer to the dielectric layer unit; multiple sets of first shielding vias C disposed on the second dielectric layer and located outside the anti-pad corresponding to signal line 2; and multiple sets of first shielding vias B disposed on the dielectric layer unit; the first shielding vias A and C, and the first shielding vias A and B respectively form a quasi-coaxial interconnect structure.

[0013] The axis of the first shielding hole A, the axis of the first shielding hole B, the axis of the first shielding hole C, and the axis of the signal line are on the bisectors of the signal through hole.

[0014] In some possible implementations, the dielectric layer unit includes a second dielectric layer and a third dielectric layer disposed sequentially below the first dielectric layer, with the third dielectric layer disposed between the second and second dielectric layers; and metal grounding layers are respectively disposed on the upper and lower sides of the second and third dielectric layers.

[0015] In some possible implementations, the first shielding hole B includes a hole one that penetrates the second and third dielectric layers and forms a near-coaxial interconnection structure with the first shielding hole A, and a set of holes two whose axes are on the same vertical plane as the axis of the signal line one; the axes of the holes one, two, and the signal line one are on the bisectors of the signal through hole.

[0016] In some possible implementations, the second shielding hole penetrates the first dielectric layer; the third shielding hole penetrates the second dielectric layer.

[0017] In some possible implementations, signal line one and signal line two are grounded coplanar waveguide transmission lines; the signal lines are high and low impedance lines.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0019] This invention reduces signal loss across multiple layers and improves signal transmission performance by using glass as a dielectric layer instead of silicon, adding a cavity below the vertical interconnect structure, and using a high-low impedance structure to improve the distribution and size of the ground shield hole and signal hole.

[0020] This invention is based on TGV technology. By incorporating a cavity structure, a high- and low-impedance line structure, and a coaxial-like structure, it adjusts the internal impedance matching, thereby reducing insertion loss and improving return loss.

[0021] This invention features an insertion loss greater than 0.16dB and a return loss greater than 30dB across the entire frequency band from 0.1GHz to 30GHz, with a return loss of approximately 40dB from 2GHz to 24GHz. Simultaneously, the impedance seen from both ports is 50 ohms, allowing for good matching with various RF devices. Attached Figure Description

[0022] Figure 1 This is a front view of the present invention;

[0023] Figure 2 This is a three-dimensional structural diagram of the present invention;

[0024] Figure 3 This is a schematic diagram of the structure of the upper surface of the first dielectric layer of the present invention;

[0025] Figure 4 This is a schematic diagram of the structure of the upper surface of the second dielectric layer in this invention;

[0026] Figure 5 This is a schematic diagram of the vertical structure insertion loss of the present invention;

[0027] Figure 6 This is a schematic diagram of the return loss of the present invention;

[0028] Wherein: 1-First dielectric layer, 11-Signal line one, 2-Dielectric layer two, 3-Dielectric layer three, 4-Second dielectric layer, 41-Signal line two, 5-Third dielectric layer, 6-Fourth dielectric layer, 7-Shielding hole one, 71-First shielding hole A, 72-First shielding hole B, 8-Shielding hole two, 9-Shielding hole three, 10-Air cavity, 20-Signal through hole. Detailed Implementation

[0029] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," etc., do not indicate a quantity limitation, but rather indicate the existence of at least one. In the implementation of this application, "and / or" describes the association relationship of related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more. For example, multiple positioning posts refer to two or more positioning posts. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0030] The present invention will now be described in detail.

[0031] Combined with appendix Figures 1-2 As shown, the present invention provides an ultra-wideband multilayer vertical interconnect structure based on glass-based SiP packaging, wherein the signal lines of the ultra-wideband multilayer vertical interconnect structure adopt the ground coplanar waveguide-signal via 20-ground coplanar waveguide type;

[0032] The dielectric layer structure includes a first dielectric layer 1, a second dielectric layer 2, a third dielectric layer 3, a second dielectric layer 4, a third dielectric layer 5, and a fourth dielectric layer 6 stacked sequentially. Metal grounding layers are provided on the upper and lower sides of each dielectric layer (first dielectric layer 1, second dielectric layer 2, third dielectric layer 3, second dielectric layer 4, third dielectric layer 5, and fourth dielectric layer 6). Signal line 11, which uses a grounded coplanar waveguide, is provided on the upper surface of the first dielectric layer 1, and signal line 41, which uses high and low impedance lines, is provided on the upper surface of the second dielectric layer 4.

[0033] Among them, the metal ground layer above the second dielectric layer 2 is continuous at the position corresponding to the first signal line 11, and the metal ground layer on the second dielectric layer 4 is continuous at the position corresponding to the second signal line 41.

[0034] When viewed from above, signal line 11 and signal line 41 are perpendicular to each other on the plane of the second dielectric layer 4, forming a 90° angle; signal wiring is carried out on the upper surface of the first dielectric layer 1 and the upper surface of the second dielectric layer 4, respectively.

[0035] The signal via 20 is used to connect signal line 11 and signal line 41. Each dielectric layer (dielectric layer 1, dielectric layer 2, dielectric layer 3, dielectric layer 4, dielectric layer 5, and dielectric layer 6) has a pad. The pads are isolated from the corresponding metal ground planes by anti-pads.

[0036] A shielding hole 7 is provided on the outside of the anti-pad. The shielding hole 7 includes multiple sets of first shielding holes A71 that penetrate the first dielectric layer 1 to the dielectric layer unit, multiple sets of first shielding holes B72 that penetrate the second dielectric layer 2 and the third dielectric layer 3 and form a quasi-coaxial interconnection structure with the first shielding holes A71, and multiple sets of first shielding holes C73 that are provided in the second dielectric layer 4 and form a quasi-coaxial interconnection structure with the first shielding holes A71.

[0037] Multiple sets of first shielding holes A71 are disposed outside the anti-pad corresponding to signal line 11 and penetrate the first dielectric layer 1 to the dielectric layer unit; multiple sets of first shielding holes B72 are disposed on the dielectric layer unit; and multiple sets of first shielding holes C73 are disposed on the second dielectric layer 4 and penetrate the second dielectric layer 4. The first shielding holes A71 and C73, and the first shielding holes A71 and B72 respectively form a quasi-coaxial interconnect structure.

[0038] The first shielding hole B72 includes a hole one that penetrates the second dielectric layer 2 and the third dielectric layer 3 and forms a near-coaxial interconnection structure with the first shielding hole A71, and a set of holes two whose axes are on the same vertical plane as the axis of the signal line 11; the axes of the holes one, the holes two, and the signal line 11 are on the bisectors of the signal through hole;

[0039] Among them, the number of the first shielding hole A71 is eleven, which penetrates from the first dielectric layer 1 to the dielectric layer unit. When the first hole has eleven groups penetrating the second dielectric layer 2, the number of holes one and two penetrating the second dielectric layer 2 is 12. The first hole and the first shielding hole A71 are correspondingly arranged to form a quasi-coaxial interconnection structure, ensuring that the metal ground layer on the first dielectric layer 1, the metal ground layer on the second dielectric layer 2, and the metal ground layer on the third dielectric layer 3 are connected.

[0040] To avoid overlapping and interference with signal line 41, only 7 sets of vias 1 penetrate dielectric layer 3, and these 7 sets will be located on the side of the anti-pad away from signal line 41; there is 1 set of vias 2, which penetrates from dielectric layer 2 to dielectric layer 3, and the axis of vias 2 and the axis of signal line 11 are on the same vertical plane; this ensures that the metal ground plane on dielectric layer 3 is connected to the metal ground plane on the second dielectric layer 4.

[0041] The first shielding hole C73 penetrates the second dielectric layer 4 in five groups, forming a near-coaxial structure with the five groups corresponding to the seven groups of holes in the third dielectric layer 3, ensuring the conductivity between the metal ground layer on the second dielectric layer 4 and the metal ground layer on the third dielectric layer 5.

[0042] Connect the center of the circle containing the first shielding hole A71 and the second hole in the eleventh group with the center of the circle containing the signal through hole 20, and divide the circle formed by the signal through hole 20 into twelve equal parts.

[0043] An air cavity 10 is provided on the second dielectric layer 4, specifically below the position corresponding to the anti-pad.

[0044] Specifically, in this embodiment, the dielectric layer is a glass dielectric, specifically an alkali-free glass dielectric AF32, with a relative permittivity of 5.1, a loss factor of 0.0035, and a thickness of 300 μm for each glass substrate layer.

[0045] Specifically, the pad radius is r p =180um, the radius of the anti-pad is r p0 =325um, the distance between the first shielding hole A71 and the signal via 20 on the first dielectric layer 1 is d. x =430um; the distance d between the first shielding hole B72 penetrating the dielectric layer 3 and the axis of the signal via 20 is 430um. x1 =420μm;

[0046] Based on a first dielectric layer thickness of 300 μm, and assuming a linewidth of 180 μm for signal line 11, the distance between signal line 11 and the same layer of metallic ground plane is 35 μm. (See attached image) Figure 3 As shown.

[0047] Furthermore, the pad radius of the intermediate transition dielectric layer (dielectric layer 2, dielectric layer 3) is consistent with the spacing of the corresponding ground metal layer and the line width and spacing in the first dielectric layer 1.

[0048] It is also provided with shielding hole 2 8 and shielding hole 3 9. Shielding hole 2 8 consists of multiple sets that penetrate from the first dielectric layer 1 to the second dielectric layer 2 and are located on both sides of the axis of signal line 11. Shielding hole 2 8 located on the same side of signal line 11 consists of multiple sets that are equally spaced. Shielding hole 3 9 is set in the same way as shielding hole 2 8.

[0049] The number of shielding holes 2 8 is determined according to the length of the signal line and is distributed on both sides of the signal line 1 11. Due to the limitations of the TGV process, the distance between shielding holes 2 8 and the edge of the corresponding ground metal layer is 30μm, and the hole spacing is 150μm. Shielding holes 3 9 are set in the same way as shielding holes 2 8.

[0050] Furthermore, signal line 212 is a high-impedance and low-impedance line, and the width of the two line segments is calculated based on the dielectric layer height; where the line width d w_btw =280μm, the horizontal distance d between the two locations w_btw_gap =630um.

[0051] The air cavity 10 in the second dielectric layer 4 is specifically located below the anti-pad, and its specific size is r. hole =300μm, the height is the thickness of the second dielectric layer 4 is 300μm.

[0052] This invention can be used in DC 30GHz system-in-package (SiP) applications.

[0053] This invention is based on TGV technology. By incorporating a cavity structure, a high- and low-impedance line structure, and a coaxial-like structure, the internal impedance matching is adjusted, thereby reducing insertion loss and improving return loss.

[0054] From simulation results Figure 5 , Figure 6 As can be seen, the insertion loss is greater than 0.16dB across the entire frequency band from 0.1GHz to 30GHz, and the return loss is greater than 30dB. The return loss is around 40dB from 2GHz to 24GHz. Meanwhile, the impedance seen from both ports is 50 ohms, allowing for good matching with various RF devices.

[0055] This invention is not limited to the specific embodiments described above. The invention extends to any new feature or combination disclosed in this specification, as well as any new method or process step or combination disclosed herein.

Claims

1. An ultra-wideband multilayer vertical interconnect structure based on glass-based SiP packaging, characterized in that, The device includes a first dielectric layer (1) on which signal line one (11) is provided, a second dielectric layer (4) on which signal line two (41) is provided, a dielectric layer unit disposed between the first dielectric layer (1) and the second dielectric layer (4), a signal via (20) for signal line one (11) and signal line two (41), and a grounding shield structure disposed on the outside of both signal line one (11) and signal line two (41); the first dielectric layer (1), the dielectric layer unit, and the second dielectric layer (4) are stacked. The projections of signal line one (11) and signal line two (41) on the second dielectric layer (4) are perpendicular to each other; a pad structure is provided on the outer side of each signal via (20); an air cavity (10) corresponding to the position of the pad structure is provided on the second dielectric layer (4).

2. The ultra-wideband multilayer vertical interconnect structure based on glass-based SiP packaging according to claim 1, characterized in that, It also includes metal grounding layers disposed on the upper and lower sides of the first dielectric layer (1), the second dielectric layer (4), and the dielectric layer unit; wiring is respectively laid on the metal grounding layer on the top surface of the first dielectric layer (1) and the metal grounding layer on the top surface of the second dielectric layer (4).

3. The ultra-wideband multilayer vertical interconnect structure based on glass-based SiP packaging according to claim 2, characterized in that, There is no grounding metal on the metal ground layer of the second dielectric layer (4) at the position corresponding to the air cavity (10).

4. The ultra-wideband multilayer vertical interconnect structure based on glass-based SiP packaging according to claim 2, characterized in that, The pad structure includes a pad and an anti-pad located between the pad and the metal ground layer; multiple sets of pad structures are coaxially arranged; the first signal line (11) is connected to the pad on the first dielectric layer (1); the second signal line (41) is connected to the pad on the second dielectric layer (4).

5. The ultra-wideband multilayer vertical interconnect structure based on glass-based SiP packaging according to claim 4, characterized in that, The grounding shielding structure includes a shielding hole one (7) located outside the anti-solder pad, a shielding hole two (8) located outside the signal line one (11) and symmetrically arranged along its axis, and a shielding hole three (9) located outside the signal line two (41) and symmetrically arranged along its axis.

6. The ultra-wideband multilayer vertical interconnect structure based on glass-based SiP packaging according to claim 5, characterized in that, The shielding hole 1 (7) includes multiple sets of first shielding holes A (71) disposed outside the anti-pad corresponding to signal line 1 (11) and penetrating through the first dielectric layer (1) to the dielectric layer unit, multiple sets of first shielding holes B (72) disposed on the dielectric layer unit, and multiple sets of first shielding holes C (73) disposed on the second dielectric layer (4) and located outside the anti-pad corresponding to signal line 2 (41); the first shielding hole A (71) and the first shielding hole C (73), and the first shielding hole A (71) and the second shielding hole B (72) respectively form a quasi-coaxial interconnect structure; The axis of the first shielding hole A (71), the axis of the first shielding hole B (72), the axis of the first shielding hole C (73), and the axis of the signal line 1 (11) are on the bisector of the signal through hole (20).

7. The ultra-wideband multilayer vertical interconnect structure based on glass-based SiP packaging according to claim 6, characterized in that, The dielectric layer unit includes a second dielectric layer (2) and a third dielectric layer (3) arranged sequentially below the first dielectric layer (1). The third dielectric layer (3) is arranged between the second dielectric layer (2) and the second dielectric layer (4). Metal flooring layers are respectively arranged on the upper and lower sides of the second dielectric layer (2) and the third dielectric layer (3).

8. The ultra-wideband multilayer vertical interconnect structure based on glass-based SiP packaging according to claim 6, characterized in that, The first shielding hole B (72) includes a hole one that penetrates the second dielectric layer (2) and the third dielectric layer (3) and forms a coaxial interconnection structure with the first shielding hole A (71), and a set of holes two whose axes are on the same vertical plane as the axis of the first signal line (11); the axes of the first hole, the second hole, and the first signal line (11) are on the bisectors of the signal through hole (20).

9. The ultra-wideband multilayer vertical interconnect structure based on glass-based SiP packaging according to claim 5, characterized in that, The second shielding hole (8) penetrates the first dielectric layer (1); the third shielding hole (9) penetrates the second dielectric layer (4).

10. An ultra-wideband multilayer vertical interconnect structure based on glass-based SiP packaging according to any one of claims 1-9, characterized in that, Signal line one (11) and signal line two (41) are grounded coplanar waveguide transmission lines; the signal lines are high and low impedance lines.

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