Semiconductor devices and their fabrication methods

Abstract

This invention provides a semiconductor device and a method for fabricating the same. The semiconductor device includes: a substrate; a gate structure disposed on the substrate; source / drain structures disposed on both sides of the gate structure, the source / drain structures protruding from the surface of the substrate; a first sidewall covering a portion of the sidewall of the gate structure, a gap being provided between the first sidewall and the source / drain structures; a first dielectric layer partially filling the gap and covering the source / drain structures, the first sidewall, and the gate structure, the first dielectric layer having a first recess extending toward the gap; and a second dielectric layer covering the first dielectric layer, including a protrusion filling the first recess. This invention improves the performance of the semiconductor device by optimizing parasitic effects and RC delay.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] Semiconductor transistors (such as metal-oxide-semiconductor transistors, or MOS transistors) have been used in various applications, including power supplies, power converters, and switches. MOS transistors typically employ a planar structure. As semiconductor integrated circuit technology has advanced, the size of these planar transistors has also shrunk. The industry commonly uses stress engineering to ensure carrier mobility in the channel. This involves forming raised epitaxial materials in the source and drain regions on both sides of the gate structure to apply specific types of stress to the channel region, thereby improving carrier mobility in the channel.

[0003] However, as transistor size continues to shrink, the parasitic effects and RC delay between the source / drain structure and the gate structure of the aforementioned transistor, as well as between the plugs leading out the two, become increasingly apparent, which in turn affects the performance of the device. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its fabrication method, which improves the performance of the semiconductor device by optimizing parasitic effects and RC delay.

[0005] To solve the above-mentioned technical problems, the present invention provides a semiconductor device comprising:

[0006] Substrate;

[0007] A gate structure disposed on the substrate;

[0008] Source and drain structures are disposed on both sides of the gate structure, and the source and drain structures protrude from the surface of the substrate;

[0009] A first sidewall covers a portion of the sidewall of the gate structure, and a gap is provided between the first sidewall and the source / drain structure;

[0010] A first dielectric layer partially fills the gap and covers the source / drain structure, the first sidewall, and the gate structure, wherein the first dielectric layer has a first recess extending toward the gap;

[0011] The second dielectric layer covers the first dielectric layer and includes a protrusion that fills the first recess.

[0012] Optionally, a second sidewall is provided at the bottom of the gap, and the top surface of the second sidewall is lower than the top surface of the first sidewall in the vertical direction.

[0013] Optionally, the first dielectric layer covers the top surface of the second sidewall.

[0014] Optionally, the top surface of the second sidewall is lower than the top surface of the source / drain structure in the vertical direction.

[0015] Optionally, the bottom surface of the second dielectric layer over the gap is lower than the top surface of the first sidewall.

[0016] Optionally, the protrusions of the second dielectric layer include voids.

[0017] Optionally, a metal contact layer is also provided, located on top of the gate structure and the source / drain structure and covered by the first dielectric layer, wherein the width of the metal contact layer on the gate structure is smaller than the width of the gate structure.

[0018] According to another aspect of the present invention, a semiconductor device is also provided, comprising:

[0019] Substrate;

[0020] A gate structure disposed on the substrate;

[0021] Source and drain structures are disposed on both sides of the gate structure, and the source and drain structures protrude from the surface of the substrate;

[0022] A first sidewall covers a portion of the sidewall of the gate structure, and a gap is provided between the first sidewall and the source / drain structure;

[0023] The first dielectric layer fills the gap and conformally covers the source / drain structure, the first sidewall, and the gate structure;

[0024] The second dielectric layer covers the first dielectric layer;

[0025] The first sidewall has an L-shaped profile.

[0026] According to another aspect of the present invention, a method for fabricating a semiconductor device is also provided, comprising:

[0027] A substrate is provided on which a gate structure and a first sidewall located on the sidewall of the gate structure are disposed;

[0028] A sacrificial sidewall is formed to cover the sidewall of the first sidewall;

[0029] Source and drain structures protruding from the substrate surface are formed in the substrates on both sides of the gate structure;

[0030] At least a portion of the sacrificial sidewall is removed to expose the sidewall of a portion of the gate structure and to form a gap between the source / drain structure and the first sidewall;

[0031] A first dielectric layer is formed to conformally cover the source / drain structure, the first sidewall, and the gate structure, and to partially fill the gap, and the first dielectric layer has a first recess extending toward the gap;

[0032] A second dielectric layer is formed to conformally cover the first dielectric layer, and the second dielectric layer includes protrusions that fill the first depression.

[0033] Optionally, the first sidewall includes a first sub-layer covering the sidewall of the gate structure and a second sub-layer covering the first sub-layer, the first sub-layer further extending to cover the substrate surface between the gate structure and the source / drain structure, so that the first sidewall is L-shaped.

[0034] Optionally, when removing at least a portion of the sacrificial sidewall, the first sidewall and the gate structure are also etched simultaneously, such that the height of the first sidewall is lower than the height of the gate structure, and / or that the top width of the gate structure is smaller than the bottom width.

[0035] Optionally, when the sacrificial sidewall is etched, a portion of the sacrificial sidewall remains and serves as a second sidewall, the top surface of which is lower in the vertical direction than the top surface of the source / drain structure and the top surface of the first sidewall.

[0036] Optionally, the step of forming the first dielectric layer includes:

[0037] A second oxide layer is formed to cover the source / drain structure, the first sidewall, the gate structure, and partially fill the gap;

[0038] A patterning process is performed on the second oxide layer to expose the top of the source / drain structure and the gate structure;

[0039] A metal contact layer is formed on top of the source / drain structure and the gate structure;

[0040] A third oxide layer is formed to conformally cover the second oxide layer and the metal contact layer, the third oxide layer having a first recess extending toward the gap, and the second oxide layer and the third oxide layer serving as the first dielectric layer.

[0041] Optionally, the second dielectric layer includes a second nitride layer, which, when filling the first recess to form a protrusion, also forms a void within the first recess.

[0042] In summary, the semiconductor device of the present invention includes a substrate; a gate structure disposed on the substrate; source / drain structures disposed on both sides of the gate structure, the source / drain structures protruding from the surface of the substrate; a first sidewall covering a portion of the sidewall of the gate structure, a gap being provided between the first sidewall and the source / drain structures; a first dielectric layer partially filling the gap and covering the source / drain structures, the first sidewall, and the gate structure, the first dielectric layer having a first recess extending toward the gap; and a second dielectric layer covering the first dielectric layer, including a protrusion filling the first recess. Compared to the multilayer sidewall structure in related technologies that is located between the gate structure and the source / drain structure and covers the entire sidewall of the gate structure, in this invention, the first sidewall only occupies part of the space between the source / drain structure and the gate structure, while the remaining space (gap) between the source / drain structure and the gate structure is filled by a first dielectric layer with a smaller dielectric constant. Moreover, the first sidewall only covers the sidewall of a portion of the gate structure's height (bottom), and the sidewall of the remaining height of the gate structure (top) is also covered by the first dielectric layer. Thus, by using more first dielectric layers between the source / drain structure and the gate structure in this invention, the dielectric value between the source / drain structure and the gate structure is reduced, thereby improving the performance of the semiconductor device through optimized parasitic effects and RC delay between the two. Attached Figure Description

[0043] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0044] Figure 1a This is a schematic diagram of the semiconductor device provided in Embodiment 1;

[0045] Figure 1b This is a magnified view of a portion of the protrusion provided in Embodiment 1;

[0046] Figure 2 This is a schematic diagram of the semiconductor device provided in Embodiment 2;

[0047] Figure 3a This is a flowchart of the semiconductor device fabrication method provided in Example 3;

[0048] Figures 4a to 4k This is a schematic diagram of the structure corresponding to the steps of the semiconductor device fabrication method provided in Example 3;

[0049] Figure 3b This is a flowchart of the semiconductor device fabrication method provided in Example 4;

[0050] Figures 5a to 5j This is a schematic diagram of the corresponding steps in the fabrication method of the semiconductor device provided in Example 4.

[0051] In the attached figures: 10-substrate; 11-gate structure; 21-first sidewall; 21a-first sublayer; 21b-second sublayer; 22a-sacrificial sidewall; 22b-second sidewall; 23-source / drain structure; 24-gap; 25-first dielectric layer; 25a-second oxide layer; 25b-third oxide layer; 26-metal contact layer; 27-first recess; 28-second dielectric layer; 28a-protrusion; 28b-void; 29-plug. Detailed Implementation

[0052] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0053] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0054] Example 1

[0055] Example 1 provides a semiconductor device.

[0056] Figure 1a This is a schematic diagram of the semiconductor device provided in Embodiment 1.

[0057] like Figure 1aAs shown, the semiconductor device provided in this embodiment includes a substrate 10, a gate structure 11, a source / drain structure 23, a first sidewall 21, a first dielectric layer 25, and a second dielectric layer 28. The gate structure 11 is disposed on the substrate 10. The source / drain structure 23 is disposed on both sides of the gate structure 11 and protrudes from the surface of the substrate 10. The first sidewall 21 covers a portion of the sidewall of the gate structure 11, and a gap 24 is provided between the first sidewall 21 and the source / drain structure 23. The first dielectric layer 25 partially fills the gap 24 and covers the source / drain structure 23, the first sidewall 21, and the gate structure 11. The first dielectric layer 25 has a first recess 27 extending toward the gap 24. The second dielectric layer 28 covers the first dielectric layer 25 and includes a protrusion 28a filling the first recess 27.

[0058] The substrate 10 can be made of any suitable semiconductor substrate, such as silicon, germanium, germanium-silicon, or silicon-on-insulator. The substrate 10 has isolation structures to define several active regions. The semiconductor device in this embodiment is a transistor structure disposed on the active regions. In one example, the transistor structure is P-type, the conductivity type of the active regions can be N-type, the source / drain structure 23 can be P-type, and it can be a germanium-silicon epitaxial structure. In another example, the transistor structure is N-type, the conductivity type of the active regions can be P-type, the source / drain structure 23 can be N-type, and it can be a silicon epitaxial structure or a silicon-carbon epitaxial structure. This embodiment does not limit the type of transistor structure.

[0059] Please continue to refer to Figure 1a The gate structure 11 is partially embedded in the active region between the two source / drain structures 23, and its height relative to the surface of the substrate 10 (the height exceeding the surface of the substrate 10) is greater than the height of the source / drain structures 23 on the substrate 10. In such a case... Figure 1a In the example shown, the top of the gate structure 11 can be trapezoidal or approximately trapezoidal, meaning the top width of the gate structure 11 is smaller than its bottom width (the overall width of the gate structure 11). This also means the width of the metal contact layer 26 on the gate structure 11 (which is close to the top width of the gate structure 11) is smaller than the width of the gate structure 11. This, to some extent, widens (partially increases) the distance between the plug 29 on the source / drain structure 23 and the gate structure 11, which helps to reduce the RC value between them. Figure 2 In the example shown (considering only the gate structure 11 and the metal contact layer 26), the gate structure 11 can be rectangular or approximately rectangular, meaning that the top width of the gate structure 11 is basically the same as its bottom width, which also means that the width of the metal contact layer 26 on the gate structure 11 is basically the same as the width of the gate structure 11.

[0060] Please continue to refer to Figure 1aA first sidewall 21 is disposed between the gate structure 11 and the source / drain structure 23, covering a portion of the sidewall of the gate structure 11, specifically the lower portion of the sidewall of the gate structure 11. In other words, the height of the first sidewall 21 on the substrate 10 (active region) is less than the height of the gate structure 11. The first sidewall 21 may include a first sub-layer 21a covering the sidewall of the gate structure 11 and a second sub-layer 21b covering the sidewall of the first sub-layer 21a. Figure 1a In the example, the first sidewall 21 does not cover the sidewall of the trapezoidal portion of the gate structure 11, meaning the height of the first sidewall 21 is close to the height of the lower portion of the trapezoidal shape of the gate structure 11. However, in... Figure 2 In the example shown, the gate structure 11 is rectangular, and the first sidewall 21 covers the lower portion of the sidewall of the gate structure 11. Of course, in... Figure 1a and Figure 2 In the example, the heights of the first sub-layer 21a and the second sub-layer 21b in the first sidewall 21 are substantially the same. In other examples of this embodiment, the height of the first sub-layer 21a in the first sidewall 21 may also be greater than the height of the second sub-layer 21b, that is, the height of the second sub-layer 21b is used as the height of the first sidewall 21. Furthermore, the aforementioned first sub-layer 21a may extend to cover the active region surface between the source / drain structure 23 and the gate structure 11, so that the entire first sidewall 21 is L-shaped. In some examples, the material of the first sub-layer 21a may be an oxide (e.g., silicon oxide), while the material of the second sub-layer 21b may be a nitride (e.g., silicon nitride); in other examples, the material of the first sub-layer 21a may be a nitride, while the material of the second sub-layer 21b may be an oxide.

[0061] Please continue to refer to Figure 1aThe first sidewall 21 is spaced a certain distance from the source / drain structure 23, thereby forming a gap 24 between the first sidewall 21 and the source / drain structure 23. The first dielectric layer 25 conformally covers the source / drain structure 23, the metal contact layer 26, the first sidewall 21, the gate structure 11, and the surface of the substrate 10. The first dielectric layer 25 may be made of an oxide with a low dielectric constant (e.g., silicon oxide). The first dielectric layer 25 covers the sidewall of the gate structure 11 exposed due to the removal of part of the first sidewall 21 (the sidewall located at its top), fills (or partially fills) the gap 24 between the source / drain structure 23 and the first sidewall 21, and forms a first recess 27 extending toward the gap 24 at the gap 24. The second dielectric layer 28 serves as an etch stop layer. It is made of a relatively hard material with a relatively high dielectric constant, and its material can be, for example, a nitride (e.g., silicon nitride). The second dielectric layer 28 conformally covers the first dielectric layer 25 and fills the first recess 27. The second dielectric layer 28 includes a protrusion 28a filling the first recess 27. Specifically, the bottom (lowest point) of the first recess 27 is lower than the top surface of the first sidewall 21; that is, the bottom surface of the protrusion 28a filling the first recess 27 is lower than the top surface of the first sidewall 21. In some examples, such as... Figure 1b As shown in the enlarged view, the protrusion 28a of the second dielectric layer 28 also includes a gap 28b, that is, the second dielectric layer 28 did not seal the first recess 27 in advance when filling it, so that the first recess 27 was not completely filled, which helps to reduce the dielectric value at that point. Compared to the multilayer sidewall structure in related technologies that is located between the gate structure and the source / drain structure and covers the entire sidewall of the gate structure, in this embodiment, the first sidewall 21 only occupies part of the space between the source / drain structure 23 and the gate structure 11, while the remaining space between the source / drain structure 23 and the gate structure 11 (i.e., the gap 24) is filled by a first dielectric layer 25 with a smaller dielectric constant. Moreover, the first sidewall 21 only covers the sidewall of a portion of the height (bottom) of the gate structure 11, and the sidewall of the remaining height (top) of the gate structure 11 is also covered by the first dielectric layer 25. Thus, in this embodiment, a larger number of first dielectric layers 25 are used between the source / drain structure 23 and the gate structure 11, thereby reducing the dielectric value between the source / drain structure 23 (and the plug 29 thereon) and the gate structure 11 (and the plug 29 thereon), thereby improving the performance of the semiconductor device by optimizing the parasitic effects and RC delay between the two.

[0062] Furthermore, such as Figure 1aAs shown in the transistor on the left, a second sidewall 22b is provided between the bottom of the first sidewall 21 and the bottom of the source-drain structure 23. That is, the second sidewall 22b is located on the active region (or the first sub-layer 21a of the active region) of both. The top surface of the second sidewall 22b is lower than the top surface of the source-drain structure 23 in the vertical direction (and also lower than the top surface of the first sidewall 21). In other words, the bottom of the gap 24 between the first sidewall 21 and the source-drain structure 23 is the top surface of the second sidewall 22b. When the first dielectric layer 25 fills the gap 24, it also covers the top surface of the second sidewall 22b. Figure 1a In the two transistors shown, the gate structure 11 has a second sidewall 22b on both sides or neither side has a second sidewall 22b. In other examples of transistors in this embodiment, the gate structure 11 has a second sidewall 22b on one side and no second sidewall 22b on the other side.

[0063] Example 2

[0064] Example 2 provides a semiconductor device.

[0065] Figure 2 This is a schematic diagram of the semiconductor device provided in Embodiment 2.

[0066] like Figure 2 As shown, the semiconductor device provided in this embodiment includes a substrate 10, a gate structure 11, a source / drain structure 23, a first sidewall 21, a first dielectric layer 25, and a second dielectric layer 28. The gate structure 11 is disposed on the substrate 10. The source / drain structure 23 is disposed on both sides of the gate structure 11 and protrudes from the surface of the substrate 10. The first sidewall 21 covers a portion of the sidewall of the gate structure 11, and a gap 24 is provided between the first sidewall 21 and the source / drain structure 23. The first dielectric layer 25 fills the gap 24 and covers the source / drain structure 23, the first sidewall 21, and the gate structure 11. The second dielectric layer 28 covers the first dielectric layer 25. The first sidewall 21 has an L-shaped profile.

[0067] The substrate 10 can be made of any suitable semiconductor substrate, such as silicon, germanium, germanium-silicon, or silicon-on-insulator. The substrate 10 has isolation structures to define several active regions. The semiconductor device in this embodiment is a transistor structure disposed on the active regions. In one example, the transistor structure is P-type, the conductivity type of the active regions can be N-type, the source / drain structure 23 can be P-type, and it can be a germanium-silicon epitaxial structure. In another example, the transistor structure is N-type, the conductivity type of the active regions can be P-type, the source / drain structure 23 can be N-type, and it can be a silicon epitaxial structure or a silicon-carbon epitaxial structure. This embodiment does not limit the type of transistor structure.

[0068] Please continue to refer to Figure 2The gate structure 11 is partially embedded in the active region between the two source / drain structures 23, and its height relative to the surface of the substrate 10 (the height exceeding the surface of the substrate 10) is greater than the height of the source / drain structures 23 on the substrate 10. In such a case... Figure 2 In the example shown, the gate structure 11 can be rectangular or approximately rectangular, meaning that the top width and bottom width of the gate structure 11 are basically the same, which is also the same as the width of the metal contact layer 26 on the gate structure 11.

[0069] Please continue to refer to Figure 2 A first sidewall 21 is disposed between the gate structure 11 and the source / drain structure 23, covering a portion of the sidewall of the gate structure 11, specifically the lower portion of the sidewall of the gate structure 11. In other words, the height of the first sidewall 21 on the substrate 10 (active region) is less than the height of the gate structure 11. The first sidewall 21 may include a first sub-layer 21a covering the sidewall of the gate structure 11 and a second sub-layer 21b covering the sidewall of the first sub-layer 21a. The first sub-layer 21a may further extend to cover the surface of the active region between the source / drain structure 23 and the gate structure 11, so that the entire first sidewall 21 is L-shaped.

[0070] Please continue to refer to Figure 2 The first sidewall 21 is spaced a certain distance from the source / drain structure 23, thereby forming a gap 24 between the first sidewall 21 and the source / drain structure 23. The first dielectric layer 25 conformally covers the source / drain structure 23, the metal contact layer 26, the first sidewall 21, the gate structure 11, and the surface of the substrate 10, to completely cover the surface of the substrate 10 and the structures on the substrate 10 (except for the plug 29). The first dielectric layer 25 may be made of an oxide with a low dielectric constant (e.g., silicon oxide), and the first dielectric layer 25 fills the gap 24. The second dielectric layer 28 serves as an etch stop layer, and its material is relatively hard and has a relatively high dielectric constant. Its material may be, for example, a nitride (e.g., silicon nitride), and the second dielectric layer 28 conformally covers the first dielectric layer 25. Compared to the multilayer sidewall structure in related technologies that is located between the gate structure and the source / drain structure and covers the entire sidewall of the gate structure, in this embodiment, the first sidewall 21 only occupies part of the space between the source / drain structure 23 and the gate structure 11, while the remaining space between the source / drain structure 23 and the gate structure 11 (i.e., the gap 24) is filled by a first dielectric layer 25 with a smaller dielectric constant. Moreover, the first sidewall 21 only covers the sidewall of a portion of the height (bottom) of the gate structure 11, and the sidewall of the remaining height (top) of the gate structure 11 is also covered by the first dielectric layer 25. Thus, in this embodiment, a larger number of first dielectric layers 25 are used between the source / drain structure 23 and the gate structure 11, thereby reducing the dielectric value between the source / drain structure 23 (and the plug 29 thereon) and the gate structure 11 (and the plug 29 thereon), thereby improving the performance of the semiconductor device by optimizing the parasitic effects and RC delay between the two.

[0071] Furthermore, such as Figure 2 As shown in the transistor on the left, a second sidewall 22b is provided between the bottom of the first sidewall 21 and the bottom of the source-drain structure 23. That is, the second sidewall 22b is located on the active region (or the first sub-layer 21a of the active region) of both. The top surface of the second sidewall 22b is lower than the top surface of the source-drain structure 23 in the vertical direction (and also lower than the top surface of the first sidewall 21). In other words, the bottom of the gap 24 between the first sidewall 21 and the source-drain structure 23 is the top surface of the second sidewall 22b. When the first dielectric layer 25 fills the gap 24, it also covers the top surface of the second sidewall 22b. Figure 2 In the two transistors shown, the gate structure 11 has a second sidewall 22b on both sides or neither side has a second sidewall 22b. In other examples of transistors in this embodiment, the gate structure 11 has a second sidewall 22b on one side and no second sidewall 22b on the other side.

[0072] Example 3

[0073] Example 3 provides a method for fabricating a semiconductor device.

[0074] Figure 3a This is a flowchart of the semiconductor device fabrication method provided in Example 3.

[0075] like Figure 3a As shown, the semiconductor device fabrication method provided in this embodiment is used to form the semiconductor device as provided in Embodiment 1, and the fabrication method includes:

[0076] S01: A substrate is provided, on which a gate structure and a first sidewall located on the sidewall of the gate structure are provided;

[0077] S02: Form a sacrificial sidewall to cover the sidewall of the first sidewall;

[0078] S03: A source / drain structure protruding from the surface of the substrate is formed in the substrate on both sides of the gate structure;

[0079] S04: At least a portion of the sacrificial sidewalls are removed to expose the sidewalls of a portion of the gate structure.

[0080] And a gap is formed between the source / drain structure and the first sidewall;

[0081] S05: A first dielectric layer is formed to conformally cover the source / drain structure, the first sidewall, and the gate structure, and to partially fill the gap, wherein the first dielectric layer has a first recess extending toward the gap;

[0082] S06: A second dielectric layer is formed to conformally cover the first dielectric layer, and the second dielectric layer includes a protrusion that fills the first depression.

[0083] Figures 4a to 4k The diagram below shows the structural schematics corresponding to the steps of the semiconductor device fabrication method provided in Example 3. Next, we will combine... Figures 4a to 4k The method for fabricating the semiconductor device is described in detail.

[0084] First, perform step S01, please refer to... Figure 4a A substrate 10 is provided, on which a gate structure 11 and a first sidewall 21 located on the sidewall of the gate structure 11 are provided.

[0085] The substrate 10 can be made of any suitable semiconductor substrate, such as silicon, germanium, silicon germanium, or silicon-on-insulator. An isolation structure is provided in the substrate 10 to define several active regions. This embodiment does not limit the conductivity type of the active regions; they can be N-type or P-type, i.e., it does not limit the type of transistor formed on the active regions. This embodiment is illustrated by forming two P-type transistors on the substrate 10, where the conductivity type of the active regions can be N-type. The gate structure 11 may include a gate dielectric layer disposed on the active regions and a gate conductive layer disposed on the gate dielectric layer. A hard mask layer may also be retained on the top surface of the gate structure 11, the material of which includes, for example, stacked silicon oxide and silicon nitride. A first sidewall 21 is disposed on the sidewall of the gate structure 11, and it may include a first sub-layer 21a covering the sidewall of the gate structure 11 and a second sub-layer 21b covering the sidewall of the first sub-layer 21a. The first sub-layer 21a may also extend to cover the surface of the substrate 10 (active regions), so that the first sidewall 21 is L-shaped. It should be noted that the gate structure 11 is rectangular at this time, and the height of the first sidewall 21 is basically the same as the height of the gate structure 11.

[0086] In some examples, the first sublayer 21a may be made of an oxide (e.g., silicon oxide), while the second sublayer 21b may be made of a nitride (e.g., silicon nitride); in other examples, the first sublayer 21a may be made of a nitride, while the second sublayer 21b may be made of an oxide.

[0087] Next, proceed to step S02, please refer to... Figure 4b This forms a sacrificial sidewall 22a that covers the sidewall of the first sidewall 21.

[0088] The sacrificial sidewall 22a defines the space in which the source / drain structure 23 grows toward the gate structure 11, that is, it defines the boundary of the source / drain structure 23 protruding from the substrate 10 near the gate structure 11. The material of the sacrificial sidewall 22a may include a second nitride (e.g., a second silicon nitride), and a pad oxide layer may also be provided between the second nitride and the first sidewall 21 (first nitride). In this case, the height of the sacrificial sidewall 22a is close to or slightly lower than the height of the first sidewall 21.

[0089] Next, proceed to step S03, please refer to... Figure 4c Source and drain structures 23 protruding from the surface of substrate 10 are formed in the substrate 10 on both sides of gate structure 11.

[0090] The lower portion of the source-drain structure 23 is embedded in the active regions on both sides of the gate structure 11, and the upper portion of the source-drain structure 23 protrudes from the active regions. The height of the portion of the source-drain structure 23 protruding from the active regions is lower than the height of the sacrificial sidewall 22a, the first sidewall 21, and the gate structure 11. The source-drain structure 23 is adjacent to or in contact with the sacrificial sidewall 22a on the side facing the gate structure 11. The type and material of the source-drain structure 23 match the type of the transistor. In one example, the formed transistor is P-type, and the conductivity type of its corresponding source-drain structure 23 is P-type, and its material is germanium-silicon epitaxial material. In another example, the formed transistor is N-type, and the conductivity type of its corresponding source-drain structure 23 is N-type, and its material is silicon carbide epitaxial material.

[0091] Next, proceed to step S04, please refer to... Figure 4d At least a portion of the sacrificial sidewall 22a is removed to expose a portion of the height of the gate structure 11 sidewall, and a gap 24 is formed between the source / drain structure 23 and the first sidewall 21.

[0092] Specifically, a dry etching process can be used to etch the structures on the substrate 10, including the sacrificial sidewall 22a, the first sidewall 21, the source / drain structure 23, and the hard mask layer on the surface of the gate structure 11, to remove at least a portion of the height of the sacrificial sidewall 22a, making the height of the remaining sacrificial sidewall 22a less than the height of the source / drain structure 23, and using the remaining sacrificial sidewall 22a as the second sidewall 22b, that is, the top surface of the second sidewall 22b is lower than the top surface of the source / drain structure 23. Of course, in an ideal situation, the sacrificial sidewall 22a is completely removed, i.e., there is no second sidewall 22b. However, in practice, to facilitate the simultaneous etching of all structures on the substrate 10 using dry etching, completely removing the sacrificial sidewall 22a may have unacceptable effects on other structures. Therefore, a remaining portion of the height of the sacrificial sidewall 22a at the bottom of the first sidewall 21 is also acceptable. Therefore, when the transistor structure has a second sidewall 22b, the bottom of the gap 24 formed between the source / drain structure 23 and the first sidewall 21 is the top surface of the second sidewall 22b. Conversely, when the transistor structure does not have a second sidewall 22b, the bottom of the gap 24 formed between the source / drain structure 23 and the first sidewall 21 is the surface of the active region (or the surface of the first sublayer 21a on the active region). Furthermore, in situations such as... Figure 4d On the left side of the transistor structure, second sidewalls 22b are formed on both sides of the gate structure 11. Figure 4d It is also possible that the gate structure 11 of the transistor structure on the right does not have a second sidewall 22b on both sides, or that the gate structure 11 has a second sidewall 22b on one side and not on the other side.

[0093] It should be noted that, in this embodiment, the dry etching process removes part of the sacrificial sidewall 22a and also removes a portion of the thickness of the first sidewall 21, thereby exposing the sidewall at the top of the gate structure 11. Since the sacrificial sidewall 22a has a larger exposure area than the first sidewall 21, the etching rate of the sacrificial sidewall 22a is greater than the etching rate of the first sidewall 21 during dry etching. This results in the first sidewall 21 having a greater height than the second sidewall 22b after dry etching.

[0094] Furthermore, during the dry etching process described above, when removing the hard mask layer on the top surface of the gate structure 11, the top sidewall of the gate structure 11 is exposed after the first sidewall 21 is partially etched. The etching rate at the top edge of the gate structure 11 is faster than the etching rate at its top center, resulting in more etching at the top edge of the gate structure 11, thus forming a trapezoidal shape on the top of the gate structure 11. Of course, in other examples of this embodiment, it is also feasible if the top of the gate structure 11 does not form the aforementioned trapezoidal shape. Additionally, in other examples, the first sub-layer 21a covering the area between the gate structure 11 and the source / drain structure 23 is retained or partially retained after the dry etching process, thereby making the formed first sidewall 21 L-shaped.

[0095] Next, step S05 is performed to form a first dielectric layer 25 that conformally covers the source / drain structure 23, the first sidewall 21, and the gate structure 11, and partially fills the gap 24, and the first dielectric layer 25 has a first recess 27 extending toward the gap 24.

[0096] For details, please refer to Figure 4e A second oxide layer 25a is formed to conformally cover the source / drain structure 23, the first sidewall 21, and the gate structure 11, and partially fills the gap 24. Of course, if the bottom of the gap 24 is the second sidewall 22b, the second oxide layer 25a also covers the top surface of the second sidewall 22b. In a preferred example, atomic layer deposition (ALD) can be used to form the second oxide layer 25a to improve its step coverage. However, the second oxide layer 25a may not completely fill the gap 24; that is, the thickness of the second oxide layer 25a may be relatively thin to mitigate the impact of the low deposition rate of the ALD process on production efficiency.

[0097] Please refer to Figure 4f A patterning process is performed on the second oxide layer 25a to expose the top surface of the source / drain structure 23 and the gate structure 11.

[0098] Please refer to Figure 4gA metal contact layer 26 is formed on the top surface of the source / drain structure 23 and the gate structure 11. The metal contact layer 26 can be made of metal silicide, that is, metal silicide is formed by annealing a metal (e.g., titanium, cobalt, etc.) with silicon material in the area not covered by the second oxide layer 25a and exposed to silicon material. It can be understood that if the top of the gate structure 11 has a trapezoidal shape, the width of the top surface of the second oxide layer 25a exposing the gate structure 11 is smaller than the width (bottom width) of the gate structure 11, so that the width of the metal contact layer 26 formed on the top surface of the gate structure 11 is smaller than the bottom width of the gate structure 11.

[0099] Please refer to Figure 4h A third oxide layer 25b is formed to conformally cover the second oxide layer 25a and the metal contact layer 26. The third oxide layer 25b has a first recess 27 extending toward the gap 24, and the second oxide layer 25a and the third oxide layer 25b serve as the first dielectric layer 25. Similar to the formation of the second oxide layer 25a, the third oxide layer 25b can be formed using an atomic layer deposition process to improve its step coverage. Moreover, the thickness of the third oxide layer 25b is relatively thin. As a result, the first dielectric layer 25 composed of the second oxide layer 25a and the third oxide layer 25b does not completely fill the gap 24, and a first recess 27 extending toward the gap 24 is formed at the gap 24.

[0100] Next, proceed to step S06, please refer to... Figure 4i A second dielectric layer 28 is formed to conformally cover the first dielectric layer 25, and the second dielectric layer 28 includes protrusions 28a filling the first recess 27. The second dielectric layer 28 serves as an etching stop layer for subsequent etching to form contact holes. It is made of a relatively hard material and typically has a relatively high dielectric constant; its material may be, for example, a nitride (e.g., silicon nitride). Figure 4j In the magnified region of the gap, when the second dielectric layer 28 fills the first recess 27 to form the protrusion 28a, it is also feasible to form a gap 28b in the protrusion 28a, for example, by pre-sealing the opening. Of course, the formation of a gap 28b in the protrusion 28a is related to the material of the second dielectric layer 28 and the method of forming the second dielectric layer 28. Taking silicon nitride as an example, when the second dielectric layer 28 is formed by atomic layer deposition, the probability of forming a gap 28b in the protrusion 28a is low due to its high step coverage. However, when conventional CVD methods (such as LPCVD, PECVD, etc.) are used, the probability of forming a gap 28b in the protrusion 28a is relatively high due to its general step coverage.

[0101] Next, please refer to Figure 4kAn interlayer dielectric layer can also be formed on the second dielectric layer 28, and a plug 29 can be formed that penetrates the interlayer dielectric layer, the second dielectric layer 28 and the first dielectric layer 25 and is electrically connected to the metal contact layer 26 on the source / drain structure 23 and the gate structure 11.

[0102] Example 4

[0103] Example 4 provides a method for fabricating a semiconductor device.

[0104] Figure 3b This is a flowchart of the semiconductor device fabrication method provided in Example 4.

[0105] like Figure 3b As shown, the semiconductor device fabrication method provided in this embodiment is used to form the semiconductor device as provided in Embodiment 2, and the fabrication method includes:

[0106] S01: A substrate is provided, on which a gate structure and a first sidewall located on the sidewall of the gate structure are provided;

[0107] S02: Form a sacrificial sidewall to cover the sidewall of the first sidewall;

[0108] S03: A source / drain structure protruding from the surface of the substrate is formed in the substrate on both sides of the gate structure;

[0109] S04: At least a portion of the sacrificial sidewalls are removed to expose the sidewalls of a portion of the gate structure.

[0110] And a gap is formed between the source / drain structure and the first sidewall;

[0111] S05: Form a first dielectric layer conformally covering the source / drain structure, the first sidewall, and the gate structure, and filling the gaps;

[0112] S06: Form a second dielectric layer to conformally cover the first dielectric layer.

[0113] Figures 5a to 5j The diagram below shows the structural schematics corresponding to the steps of the semiconductor device fabrication method provided in Example 4. Next, we will discuss the following... Figures 5a to 5j The method for fabricating the semiconductor device is described in detail.

[0114] First, perform step S01, please refer to... Figure 5a A substrate 10 is provided, on which a gate structure 11 and a first sidewall 21 located on the sidewall of the gate structure 11 are provided.

[0115] The substrate 10 can be made of any suitable semiconductor substrate, such as silicon, germanium, silicon germanium, or silicon-on-insulator. An isolation structure is provided in the substrate 10 to define several active regions. This embodiment does not limit the conductivity type of the active regions; they can be N-type or P-type, i.e., it does not limit the type of transistor formed on the active regions. This embodiment is illustrated by forming two P-type transistors on the substrate 10, where the conductivity type of the active regions can be N-type. The gate structure 11 may include a gate dielectric layer disposed on the active regions and a gate conductive layer disposed on the gate dielectric layer. A hard mask layer may also be retained on the top surface of the gate structure 11, the material of which includes, for example, stacked silicon oxide and silicon nitride. A first sidewall 21 is disposed on the sidewall of the gate structure 11, and it may include a first sub-layer 21a covering the sidewall of the gate structure 11 and a second sub-layer 21b covering the sidewall of the first sub-layer 21a. The first sub-layer 21a may also extend to cover the surface of the substrate 10 (active regions), so that the first sidewall 21 is L-shaped. It should be noted that the gate structure 11 is rectangular at this time, and the height of the first sidewall 21 is basically the same as the height of the gate structure 11.

[0116] Next, proceed to step S02, please refer to... Figure 5b This forms a sacrificial sidewall 22a that covers the sidewall of the first sidewall 21.

[0117] The sacrificial sidewall 22a defines the space in which the source / drain structure 23 grows toward the gate structure 11, that is, it defines the boundary of the source / drain structure 23 protruding from the substrate 10 near the gate structure 11. The material of the sacrificial sidewall 22a may include a second nitride (e.g., a second silicon nitride), and a pad oxide layer may also be provided between the second nitride and the first sidewall 21 (second sublayer 21b). In this case, the height of the sacrificial sidewall 22a is close to or slightly lower than the height of the first sidewall 21.

[0118] Next, proceed to step S03, please refer to... Figure 5c Source and drain structures 23 protruding from the surface of substrate 10 are formed in the substrate 10 on both sides of gate structure 11.

[0119] The lower portion of the source-drain structure 23 is embedded in the active regions on both sides of the gate structure 11, and the upper portion of the source-drain structure 23 protrudes from the active regions. The height of the portion of the source-drain structure 23 protruding from the active regions is lower than the height of the sacrificial sidewall 22a, the first sidewall 21, and the gate structure 11. The source-drain structure 23 is adjacent to or in contact with the sacrificial sidewall 22a on the side facing the gate structure 11. The type and material of the source-drain structure 23 match the type of the transistor. In one example, the formed transistor is P-type, and the conductivity type of its corresponding source-drain structure 23 is P-type, and its material is germanium-silicon epitaxial material. In another example, the formed transistor is N-type, and the conductivity type of its corresponding source-drain structure 23 is N-type, and its material is silicon carbide epitaxial material.

[0120] Next, proceed to step S04, please refer to... Figure 5d At least a portion of the sacrificial sidewall 22a is removed to expose a portion of the height of the gate structure 11 sidewall, and a gap 24 is formed between the source / drain structure 23 and the first sidewall 21.

[0121] Specifically, a dry etching process can be used to etch the structures on the substrate 10, including the sacrificial sidewall 22a, the first sidewall 21, the source / drain structure 23, and the hard mask layer on the surface of the gate structure 11, to remove at least a portion of the height of the sacrificial sidewall 22a, making the height of the remaining sacrificial sidewall 22a less than the height of the source / drain structure 23, and using the remaining sacrificial sidewall 22a as the second sidewall 22b, that is, the top surface of the second sidewall 22b is lower than the top surface of the source / drain structure 23. Of course, in an ideal situation, the sacrificial sidewall 22a is completely removed, i.e., there is no second sidewall 22b. However, in practice, to facilitate the simultaneous etching of all structures on the substrate 10 using dry etching, completely removing the sacrificial sidewall 22a may have unacceptable effects on other structures. Therefore, a remaining portion of the height of the sacrificial sidewall 22a at the bottom of the first sidewall 21 is also acceptable. Therefore, when the transistor structure has a second sidewall 22b, the bottom of the gap 24 formed between the source / drain structure 23 and the first sidewall 21 is the top surface of the second sidewall 22b. Conversely, when the transistor structure does not have a second sidewall 22b, the bottom of the gap 24 formed between the source / drain structure 23 and the first sidewall 21 is the surface of the active region (or the surface of the first sublayer 21a on the active region). Furthermore, in situations such as... Figure 5d On the left side of the transistor structure, second sidewalls 22b are formed on both sides of the gate structure 11. Figure 5d It is also possible that the gate structure 11 of the transistor structure on the right does not have a second sidewall 22b on both sides, or that the gate structure 11 has a second sidewall 22b on one side and not on the other side.

[0122] It should be noted that in this embodiment, the dry etching process removes part of the sacrificial sidewall 22a and also removes a portion of the thickness of the first sidewall 21, thereby exposing the top sidewall of the gate structure 11. Since the exposed area of ​​the sacrificial sidewall 22a is larger than that of the first sidewall 21, the etching rate of the sacrificial sidewall 22a is greater than that of the first sidewall 21 during dry etching. This results in the height of the first sidewall 21 being greater than the height of the second sidewall 22b after dry etching. In this embodiment, a portion of the hard mask layer remains on the top surface of the gate structure 11 after dry etching, meaning that the gate structure 11 remains essentially rectangular, making the width of the top surface of the gate structure 11 essentially the same as the width of its bottom surface. Of course, in other examples of this embodiment, such as in Embodiment 3 where the top of the gate structure 11 after dry etching is trapezoidal, this is also feasible. In other examples, the first sublayer 21a covering the gate structure 11 and the source / drain structure 23 is retained or partially retained after the above-described dry etching, so that the formed first sidewall 21 is L-shaped.

[0123] Next, step S05 is performed to form a first dielectric layer 25 that conformally covers the source / drain structure 23, the first sidewall 21, and the gate structure 11, and fills the gap 24.

[0124] For details, please refer to Figure 5e A second oxide layer 25a is formed to conformally cover the source / drain structure 23, the first sidewall 21, and the gate structure 11, and fill the gap 24. Of course, if the bottom of the gap 24 is the second sidewall 22b, the second oxide layer 25a also covers the top surface of the second sidewall 22b. In this embodiment, the second oxide layer 25a can fill the gap 24 as much as possible while ensuring production efficiency (production time). In one example, an atomic layer deposition process can be used to form the second oxide layer 25a to improve its step coverage; in other examples, a CVD process (e.g., LPCVD, PECVD) can also be used to form the second oxide layer 25a to ensure production efficiency.

[0125] Please refer to Figure 5f A patterning process is performed on the second oxide layer 25a to expose the top surface of the source / drain structure 23 and the gate structure 11.

[0126] Please refer to Figure 5gA metal contact layer 26 is formed on the top surface of the source / drain structure 23 and the gate structure 11. The metal contact layer 26 can be made of metal silicide, that is, metal silicide is formed by annealing a metal (such as titanium, cobalt, etc.) with silicon material in the area not covered by the second oxide layer 25a and exposed to silicon material. The top of the gate structure 11 is rectangular, and the width of the top surface of the second oxide layer 25a exposed to the gate structure 11 is basically the same as the width of the bottom surface of the gate structure 11, so that the width of the metal contact layer 26 formed on the top surface of the gate structure 11 is close to the width of the bottom surface of the gate structure 11.

[0127] Please refer to Figure 5h A third oxide layer 25b is formed to conformally cover the second oxide layer 25a and the metal contact layer 26, and the second oxide layer 25a and the third oxide layer 25b serve as the first dielectric layer 25. The material of the third oxide layer 25b can be the same as that of the second oxide layer 25a. The third oxide layer 25b fills the gap 24, that is, the lowest height of the third oxide layer 25b at the gap 24 is equal to or higher than the height of the metal contact layer 26 on the source-drain structure 23.

[0128] Next, proceed to step S06, please refer to... Figure 5i A second dielectric layer 28 is formed to conformally cover the first dielectric layer 25. The second dielectric layer 28 serves as an etch stop layer for subsequent etching to form contact holes. It is made of a relatively hard material and typically has a relatively high dielectric constant. Its material can be, for example, a nitride (e.g., silicon nitride).

[0129] Next, please refer to Figure 5j An interlayer dielectric layer can also be formed on the second dielectric layer 28, and a plug 29 can be formed that penetrates the interlayer dielectric layer, the second dielectric layer 28 and the first dielectric layer 25 and is electrically connected to the metal contact layer 26 on the source / drain structure 23 and the gate structure 11.

[0130] In summary, the semiconductor device of the present invention includes a substrate; a gate structure disposed on the substrate; source / drain structures disposed on both sides of the gate structure, the source / drain structures protruding from the surface of the substrate; a first sidewall covering a portion of the sidewall of the gate structure, a gap being provided between the first sidewall and the source / drain structures; a first dielectric layer partially filling the gap and covering the source / drain structures, the first sidewall, and the gate structure, the first dielectric layer having a first recess extending toward the gap; and a second dielectric layer covering the first dielectric layer, including a protrusion filling the first recess. Compared to the multilayer sidewall structure in related technologies that is located between the gate structure and the source / drain structure and covers the entire sidewall of the gate structure, in this invention, the first sidewall only occupies part of the space between the source / drain structure and the gate structure, while the remaining space (i.e., the gap) between the source / drain structure and the gate structure is filled by a first dielectric layer with a smaller dielectric constant. Moreover, the first sidewall only covers the sidewall of a portion of the gate structure's height (bottom), and the sidewall of the remaining height of the gate structure (top) is also covered by the first dielectric layer. Thus, by using more first dielectric layers between the source / drain structure and the gate structure in this invention, the dielectric value between the source / drain structure and the gate structure is reduced, thereby improving the performance of the semiconductor device through optimized parasitic effects and RC delay between the two.

[0131] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A semiconductor device, characterized by, The substrate; The gate structure is provided on the substrate; The source / drain structure is provided on both sides of the gate structure, and protrudes from the surface of the substrate; The first sidewall covers part of the sidewall of the gate structure, and the top of the first sidewall is lower than the top of the gate structure, and a gap is provided between the first sidewall and the source / drain structure; The first dielectric layer partially fills the gap, covers the source / drain structure, the first sidewall and the top surface of the gate structure, and has a first recess extending towards the gap, and the dielectric constant of the first dielectric layer is less than that of the first sidewall; The second dielectric layer covers the first dielectric layer, and includes a protruding part filling the first recess. A second sidewall is further provided at the bottom of the gap, and the top surface of the second sidewall is lower than the top surface of the first sidewall in the vertical direction.

2. The semiconductor device according to claim 1, wherein The first dielectric layer covers the top surface of the second sidewall.

3. The semiconductor device of claim 2, wherein, The top surface of the second sidewall is lower than the top surface of the source / drain structure in the vertical direction.

4. The semiconductor device according to claim 2, wherein The bottom surface of the second dielectric layer on the gap is lower than the top surface of the first sidewall.

5. The semiconductor device of claim 1, wherein The protruding part of the second dielectric layer contains a gap.

6. The semiconductor device of claim 1, wherein A metal contact layer is further provided on the top of the gate structure and the source / drain structure and covered by the first dielectric layer, and the width of the metal contact layer on the gate structure is less than the width of the gate structure.

7. The semiconductor device of claim 1, wherein The substrate; 8. A semiconductor device, characterized by The gate structure is provided on the substrate; The source / drain structure is provided on both sides of the gate structure, and protrudes from the surface of the substrate; The first sidewall covers part of the sidewall of the gate structure, and the top of the first sidewall is lower than the top of the gate structure, and a gap is provided between the first sidewall and the source / drain structure; The first dielectric layer fills the gap and conformally covers the source / drain structure, the first sidewall and the top surface of the gate structure, and the dielectric constant of the first dielectric layer is less than that of the first sidewall; The second dielectric layer covers the first dielectric layer; The first sidewall has an L-shaped profile. The substrate is provided with a gate structure and a first sidewall on the sidewall of the gate structure; A sacrificial sidewall is formed to cover the sidewall of the first sidewall; 9. A method of manufacturing a semiconductor device, characterized by, The source / drain structure protruding from the surface of the substrate is formed in the substrate on both sides of the gate structure; At least part of the sacrificial sidewall and the first sidewall are removed to expose part of the sidewall of the gate structure and form a gap between the source / drain structure and the first sidewall; The first dielectric layer conformally covers the source / drain structure, the first sidewall and the top surface of the gate structure, and partially fills the gap, and the first dielectric layer has a first recess extending towards the gap, and the dielectric constant of the first dielectric layer is less than that of the first sidewall; The second dielectric layer conformally covers the first dielectric layer, and the second dielectric layer includes a protruding part filling the first recess. The first sidewall includes a first sub-layer covering the sidewall of the gate structure and a second sub-layer covering the first sub-layer, and the first sub-layer further extends to cover the surface of the substrate between the gate structure and the source / drain structure, so that the first sidewall has an L shape. ​ ​ 10. The method of producing a semiconductor device according to Claim 9, wherein ​ 11. The method of producing a semiconductor device according to Claim 9, wherein In etching the sacrificial sidewalls, the sacrificial sidewalls are also partially removed, and the first sidewalls and the gate structure are simultaneously etched so that the height of the first sidewalls is lower than the height of the gate structure, and / or so that the top width of the gate structure is smaller than the bottom width of the gate structure.

12. The method of producing a semiconductor device according to Claim 9, wherein In etching the sacrificial sidewalls, the sacrificial sidewalls are also partially removed, and the first sidewalls and the gate structure are simultaneously etched so that the height of the first sidewalls is lower than the height of the gate structure, and / or so that the top width of the gate structure is smaller than the bottom width of the gate structure.

13. The method of producing a semiconductor device according to Claim 9, wherein The step of forming the first dielectric layer includes: forming a second oxide layer covering the source / drain structure, the first sidewalls, the gate structure, and partially filling the gap; performing a patterning process on the second oxide layer so that the second oxide layer exposes the top of the source / drain structure and the gate structure; forming a metal contact layer on the top of the source / drain structure and the gate structure; forming a third oxide layer conformally covering the second oxide layer and the metal contact layer, the third oxide layer having a first recess extending toward the gap, and the second oxide layer and the third oxide layer serving as the first dielectric layer.

14. The method of producing a semiconductor device according to Claim 9, wherein The second dielectric layer includes a second nitride layer, and in filling the first recess to form a protrusion, the second nitride layer also forms a void in the first recess.

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