A test mode interface circuit suitable for multi-power supply system and control method thereof
By designing a test mode interface circuit including reference current source and multiple logic gates in a multi-power system, using voltage control signal management, the problem that traditional test mode interface circuits are prone to misent into the test mode is achieved, and more stable and Flexible test mode operation.
CN118971866BActive Publication Date: 2024-12-24DIOO MICROCIRCUITS CO LTD
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Patent Information
- Application Number
- CN202411419357.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-12
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2044-10-12
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Figure CN118971866B_ABST
Abstract
The invention discloses a test mode interface circuit suitable for a multi-power supply system and a control method thereof, comprising a reference current source I0, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, an NMOS tube NM4, an NMOS tube NM5, a PMOS tube PM1, a PMOS tube PM2, a Schmitt trigger SMT1, a Schmitt trigger SMT2, an inverter INV1, an inverter INV2, an inverter INV3, a NAND gate NAND1 and an RS trigger Q1, wherein the NMOS tube NM1, the NMOS tube NM2 and the NMOS tube NM3 constitute a current mirror. The circuit structure of the invention is simple, the test mode is not easily triggered in the normal working mode, the circuit operation is safer and more stable, and the test mode can be internally locked at the same time, and the working conditions are more flexible.
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