Snn accelerator and ssn synapse weight hybrid compression storage method

Abstract

This invention provides an SNN accelerator and a hybrid compression storage method for SNN synaptic weights. The SNN accelerator includes 16 neural computation cores, each of which includes a weight storage module. The 16 neural computation cores include 8 first computation cores, 4 second computation cores, and 4 third computation cores. The weight storage modules in the first computation cores employ a weightless compression storage algorithm, the weight storage modules in the second computation cores employ a first weight compression storage algorithm, and the weight storage modules in the third computation cores employ a second weight compression storage algorithm. The weightless compression storage algorithm is used for weightless compression storage of dense synaptic weight arrays, the first weight compression storage algorithm is used for compression storage of first sparse synaptic weight arrays, and the second weight compression storage algorithm is used for compression storage of second sparse synaptic weight arrays. This invention utilizes the difference in sparsity of synaptic weights between different layers to design a multi-core heterogeneous spiking neural network accelerator, maximizing matrix compression efficiency and improving peak computing power, throughput, and energy efficiency.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence technology, and in particular to an SNN accelerator and a method for hybrid compressed storage of SNN synaptic weights. Background Technology

[0002] As a third-generation neural network, spiking neural networks combine biological rationality with low power consumption, making them more suitable for deployment on mobile devices.

[0003] Currently, there are two types of spiking neural network accelerators: one uses an unweighted compressed storage algorithm for inference computation of spiking neural networks, and the other uses a single-weighted compressed storage algorithm.

[0004] With the continuous development of pruning techniques, the sparsity of synaptic weights in spiking neural network (SNN) models has become increasingly apparent. SNN accelerators using unweighted compression storage algorithms typically cannot effectively utilize the sparsity of synaptic weights in SNN models, resulting in low computational efficiency, high power consumption, and low peak computing power. While SNN accelerators using single-weight compression storage algorithms do utilize the sparsity of synaptic weights, the difference in weight sparsity across different layers of the SNN model makes it difficult for single-weight compression storage algorithms to adapt to all layers. This leads to significant differences in computational efficiency when the accelerator operates at different layers. Furthermore, such accelerators typically only support convolutional layers or fully connected layers of SNN models, which presents significant limitations. Summary of the Invention

[0005] This invention provides an SNN accelerator, comprising: 16 neural computation kernels, each of which includes a weight storage module, the weight storage module being used to perform uncompressed or compressed storage of the synaptic weight array of the neural computation kernel;

[0006] The 16 neural computation cores include 8 first computation cores, 4 second computation cores, and 4 third computation cores. The weight storage module in the first computation cores employs an unweighted compression storage algorithm, the weight storage module in the second computation cores employs a first weighted compression storage algorithm, and the weight storage module in the third computation cores employs a second weighted compression storage algorithm. The unweighted compression storage algorithm is used for unweighted compression storage of dense synaptic weight arrays, the first weighted compression storage algorithm is used for compression storage of first sparse synaptic weight arrays, and the second weighted compression storage algorithm is used for compression storage of second sparse synaptic weight arrays. The density, first sparsity, and second sparsity are determined based on the proportion of non-zero values ​​of synaptic weights in the synaptic weight arrays.

[0007] According to the SNN accelerator provided by the present invention, the first computational core includes a reconfigurable synaptic cross array, which is suitable for operation of convolutional network structures and fully connected network structures.

[0008] According to the SNN accelerator provided by the present invention, each neural computation kernel further includes a data packet routing module, an input pulse storage module, an input pulse decoding module, a weight decompression and accumulated membrane potential module, and a leakage integral firing neuron computation module;

[0009] The data packet routing module is used to control data communication between the computing cores.

[0010] The input pulse storage module is used to store the input pulse vectors of each of the neural computation kernels;

[0011] The input pulse decoding module is used to decode the input pulse vector of each of the neural computing kernels;

[0012] The weight decompression and membrane potential accumulation module is used to decompress the synaptic weight array and accumulate the membrane potential according to the compressed storage state of the synaptic weight array in each neural computing nucleus using a corresponding weight decompression algorithm; the weight decompression and membrane potential accumulation module includes a calculation unit, which is used to perform corresponding calculations on the synaptic weights in each neural computing nucleus;

[0013] The leakage integral firing neuron calculation module is used to perform corresponding neurodynamic behavior on the accumulated membrane potential.

[0014] According to the SNN accelerator provided by the present invention, the weight storage module of the first computational core is a 576×512 BRAM, and the 576×512 BRAM is used to store the dense 576×64 reconfigurable synaptic cross array weights.

[0015] According to the SNN accelerator provided by the present invention, the weight storage module of the second computational kernel is a 256×1296 BRAM.

[0016] According to the SNN accelerator provided by the present invention, the weight storage module of the second computation kernel includes a row offset module, a bitmap module, and a non-zero weight module. The row offset module, bitmap module, and non-zero weight module are respectively used to store the row offset, bitmap, and non-zero weight of the synaptic weights in the second computation kernel.

[0017] According to the SNN accelerator provided by the present invention, the weight storage module of the third computational core is a 256×336 BRAM.

[0018] According to the SNN accelerator provided by the present invention, the weight storage module of the third computational core includes an odd-row offset module, an even-row offset module, a column index module, and a non-zero weight module. The odd-row offset module, even-row offset module, column index module, and non-zero weight module are respectively used to store the odd-row offset, even-row offset, column and non-zero weight of the synaptic weight in the second computational core.

[0019] According to the SNN accelerator provided by the present invention, in the first computational core, the computational unit of the weight decompression and membrane potential accumulation module includes 64 first processing units and 1 first allocation algorithm logic unit. The 64 first processing units are 64 adders, which are used to obtain 64 weights. The first allocation algorithm logic unit is used to accumulate the 64 weights obtained by the 64 first processing units onto the membrane potential of the corresponding neuron in one cycle.

[0020] According to the SNN accelerator provided by the present invention, in the second computational core, the computational unit of the weight decompression and membrane potential accumulation module includes 32 second processing units and 1 second allocation algorithm logic unit. The 32 second processing units are used to judge the weight values ​​of the 32 weight storage addresses, and when the weight values ​​are non-zero, they allocate and calculate the non-zero weight values. The second allocation algorithm logic unit is used to accumulate the non-zero weight values ​​obtained by each second processing unit to the membrane potential of the corresponding neuron within one cycle.

[0021] According to the SNN accelerator provided by the present invention, in the third computational core, the computational unit of the weight decompression and membrane potential accumulation module comprises 32 third processing units and 1 third allocation algorithm logic unit. The 32 third processing units are used to judge the weight values ​​of the 32 weight storage addresses. If the weight value is non-zero, they obtain the column of the non-zero weight value and the start and end nodes of the non-zero weight value. The third allocation algorithm logic unit is used to accumulate the non-zero weight values ​​between the start node and the end node onto the membrane potential of the neuron in the column where the non-zero weight value is located.

[0022] According to the SNN accelerator provided by the present invention, in convolution mode, each address of the BRAM corresponds to the weights at the same position of all convolution kernels, and the same position of different addresses of the BRAM corresponds to all the weights of the same convolution kernel; in fully connected mode, each address of the BRAM corresponds to the weights of the same input to all neurons, and the same position of different addresses of the BRAM corresponds to all the weights of the same neuron.

[0023] According to the SNN accelerator provided by the present invention, input pulses within different convolutional sliding windows can be reused in convolutional network structures.

[0024] According to the SNN accelerator provided by the present invention, the kernel size of the convolutional structure network supported by the first computation kernel is configurable.

[0025] The present invention also provides a method for hybrid compressed storage of SNN synaptic weights, the method being implemented using the SNN accelerator described in any of the preceding claims, the method comprising:

[0026] Obtain the proportion of non-zero values ​​of synaptic weights in the synaptic weight array of the current computation layer of the SNN model. The proportion of non-zero values ​​is used to determine whether the synaptic weight array is a dense representation, a first sparse representation, or a second sparse representation.

[0027] Based on the proportion of non-zero values, the synaptic weight compression storage algorithm used in the current computation layer of the SNN model is determined, wherein the weight compression storage algorithm includes a weightless compression storage algorithm, a first weight compression storage algorithm, and a second compression storage algorithm.

[0028] Based on the synaptic weight compression storage algorithm, the computational kernel used in the current computational layer of the SNN model is determined;

[0029] The computation kernel performs calculations on the current computation layer of the SNN model.

[0030] According to the SNN synaptic weight hybrid compression storage method provided by the present invention, the step of determining the synaptic weight compression storage algorithm used in the current computation layer of the SNN model based on the proportion of non-zero values ​​specifically includes:

[0031] Based on the proportion of non-zero values, determine the storage space required when the current computational layer of the SNN model adopts the compression storage algorithm for each synaptic weight;

[0032] Based on the storage space, determine the storage efficiency of the compression storage algorithm for each synaptic weight;

[0033] The synaptic weight compression storage algorithm with the highest storage efficiency is determined to be the synaptic weight compression storage algorithm used in the current computation layer of the SNN model.

[0034] According to the SNN synaptic weight hybrid compression storage method provided by the present invention, the step of determining the computational kernel used in the current computational layer of the SNN model based on the synaptic weight compression storage algorithm specifically includes:

[0035] When the synaptic weight compression storage algorithm is a weightless compression storage algorithm, the computation kernel used in the current computation layer of the SNN model is determined to be the first computation kernel;

[0036] When the synaptic weight compression storage algorithm is the first weight compression storage algorithm, the computation kernel used in the current computation layer of the SNN model is determined to be the second computation kernel;

[0037] When the synaptic weight compression storage algorithm is the second weight compression storage algorithm, the computation kernel used in the current computation layer of the SNN model is determined to be the third computation kernel.

[0038] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the SNN synaptic weight hybrid compressed storage method as described above.

[0039] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the SNN synaptic weight hybrid compressed storage method as described above.

[0040] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the SNN synaptic weight hybrid compressed storage method as described above.

[0041] The SNN accelerator and SNN synaptic weight hybrid compression storage method provided by this invention configures the 16 neural computation cores of the SNN accelerator as a first computation core, a second computation core, and a third computation core, respectively. The weight storage module in the first computation core employs a weightless compression storage algorithm, the weight storage module in the second computation core employs a first weight compression storage algorithm, and the weight storage module in the third computation core employs a second weight compression storage algorithm. The weightless compression storage algorithm is used for weightless compression storage of dense synaptic weight arrays, the first weight compression storage algorithm is used for compression storage of first sparse synaptic weight arrays, and the second weight compression storage algorithm is used for compression storage of second sparse synaptic weight arrays. The density, first sparsity, and second sparsity are determined based on the proportion of non-zero values ​​of the synaptic weights in the synaptic weight arrays. Compared to spiking neural network accelerators using unweighted compression storage algorithms, this invention utilizes the sparsity of synaptic weights in spiking neural networks to design corresponding circuits that skip accessing and calculating zero-value weights, thereby improving peak computing power, throughput, and energy efficiency. Compared to spiking neural network accelerators using single-weight compression storage algorithms, this invention fully considers the storage efficiency of matrix compression storage algorithms under different non-zero value ratios. It utilizes the differences in synaptic weight sparsity between different layers to design a multi-core heterogeneous spiking neural network accelerator, maximizing matrix compression efficiency and improving peak computing power, throughput, and energy efficiency. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0043] Figure 1 The diagram shows the algorithm structure of the spiking neural network model provided in this embodiment of the invention.

[0044] Figure 2 This is a schematic diagram of the structure of the SNN accelerator provided in an embodiment of the present invention.

[0045] Figure 3 This is a schematic diagram of the weight allocation algorithm for the BITMASK computing kernel provided in an embodiment of the present invention.

[0046] Figure 4 A schematic diagram of the weight allocation algorithm for the CSR calculation kernel provided in an embodiment of the present invention.

[0047] Figure 5 This is a schematic diagram of several matrix compression storage algorithms provided in embodiments of the present invention.

[0048] Figure 6 This is a graph showing the relationship between storage space and the proportion of non-zero values ​​under different matrix compression storage algorithms provided in embodiments of the present invention.

[0049] Figure 7 This is a schematic diagram of the weight partitioning of the DENSE calculation kernel provided in an embodiment of the present invention.

[0050] Figure 8 This is a schematic diagram of pulse multiplexing between sliding windows provided in an embodiment of the present invention.

[0051] Figure 9 This is a flowchart illustrating the SNN synaptic weight hybrid compression storage method provided in an embodiment of the present invention.

[0052] Figure 10 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0054] In practical applications, on the one hand, the input of a spiking neural network (SNN) is encoded as a sequence of pulses with multiple timesteps. Therefore, weight calculation only requires adders, avoiding the use of multipliers, which have higher power consumption. On the other hand, due to the event-driven nature of SNNs, only activated neurons participate in the computation at any given time, while the remaining neurons remain silent. Therefore, as a third-generation neural network, the spiking neural network combines biological rationality with low power consumption, making it more suitable for deployment on mobile devices. With the continuous development of pruning techniques, the sparsity of synaptic weights in SNN models is becoming increasingly apparent. Current spiking neural network accelerators often do not employ or only employ a fixed weight compression scheme, while the sparsity of weights between different layers of the SNN model varies greatly. Therefore, a high-energy-efficiency spiking neural network hardware platform that can fully utilize the differences in weight sparsity between different layers of the SNN model is needed. Furthermore, SNN models typically include both convolutional layers and fully connected layers, while current spiking neural network accelerators often only support convolutional layer or fully connected layer computation independently. Therefore, a reconfigurable spiking neural network computation core that can be flexibly configured to perform convolutional layer computation and fully connected layer computation is also needed.

[0055] Meanwhile, deep neural network accelerators are generally unsuitable for inference computations of spiking neural network (SNN) models. Due to the high computational cost and energy consumption of artificial neural networks, they are difficult to deploy effectively on edge devices. Other SNN accelerators cannot utilize the differences in weight sparsity between different layers of the SNN model, resulting in low peak computing power and energy efficiency. For SNN accelerators using a single weight compression storage algorithm, if all layers use this accelerator, the different layers of the model, due to varying weight sparsity, cannot maximize their computing power and energy efficiency by using the same weight compression storage algorithm for all layers.

[0056] In view of this, the present invention provides an SNN accelerator and a hybrid compression storage method for SNN synaptic weights. It aims to explore a novel hardware architecture similar to the biological brain from the perspective of digital circuit design, under the von Neumann bottleneck of traditional computing architecture, in order to support spiking neural network (SNN) models with synaptic weight sparsity.

[0057] In some possible implementations, to simplify the circuit hardware design and implementation of the spiking neural network algorithm, corresponding simplifications are made to the algorithm itself, such as... Figure 1 As shown, Figure 1This is a diagram illustrating the algorithm structure of the spiking neural network model provided in this embodiment of the invention. The algorithm simplifies by requiring minimal resources for circuit implementation, aiming for low power consumption and fast computation. The supported spiking neural network neurons are linear LIF (Liquidity-Induced Fluid) models. After accumulating the pulse timing sequence as input, linear leakage operations, threshold comparisons, and pulse emission are performed. The membrane potential dynamics equation of the LIF neuron model is as follows:

[0058] V j (t+1)=V j (t)+∑x i w ij -λ j (1)

[0059] Where V j (t) represents the membrane potential of neuron j at time t, w ij Let x be the weight of the i-th synaptic connection. i λ is the input of the i-th synaptic connection. j This represents the linear leakage of neuron j.

[0060] Based on the above embodiments, in some possible implementation schemes, Figure 2 This is a schematic diagram of the SNN accelerator provided in an embodiment of the present invention, as shown below. Figure 2 As shown, this solution provides an SNN accelerator, including: 16 neural computing cores, each of which includes a weight storage module, the weight storage module being used to perform uncompressed or compressed storage of the synaptic weight array of the neural computing core;

[0061] The 16 neural computation cores include 8 first computation cores, 4 second computation cores, and 4 third computation cores. The weight storage module in the first computation cores employs an unweighted compression storage algorithm, the weight storage module in the second computation cores employs a first weighted compression storage algorithm, and the weight storage module in the third computation cores employs a second weighted compression storage algorithm. The unweighted compression storage algorithm is used for unweighted compression storage of dense synaptic weight arrays, the first weighted compression storage algorithm is used for compression storage of first sparse synaptic weight arrays, and the second weighted compression storage algorithm is used for compression storage of second sparse synaptic weight arrays. The density, first sparsity, and second sparsity are determined based on the proportion of non-zero values ​​of synaptic weights in the synaptic weight arrays.

[0062] It's important to note that most current spiking neural network accelerators use crossbar arrays to store synaptic weights, where every element, regardless of its value (whether zero or not), is involved in the computation. However, the sparse synaptic weight array in spiking neural network models contains a large number of zeros, which can be stored using compression algorithms, requiring the design of corresponding decompression circuits. Furthermore, the sparsity of synaptic weights varies significantly between different layers of a spiking neural network model, necessitating the use of different matrix compression algorithms to maximize storage efficiency.

[0063] Therefore, this invention is based on a brain-like neuromorphic architecture, uses three matrix compression storage methods to store synaptic weights, and designs corresponding decompression circuits to improve the peak computing power and energy efficiency of the accelerator.

[0064] In some possible implementations, the first computational core includes a reconfigurable synaptic cross array, which is suitable for operation of convolutional network structures and fully connected network structures.

[0065] Specifically, this embodiment provides an implementation of a first computational core. In order to increase the flexibility of the SNN accelerator, the first computational core adopts a reconfigurable and configurable Crossbar structure with fused convolutional modes, so that the computational core can run both convolutional networks and fully connected networks.

[0066] In some possible implementations, each of the neural computational cores further includes a data packet routing module, an input pulse storage module, an input pulse decoding module, a weight decompression and membrane potential accumulation module, and a leakage integral firing neuron computation module; wherein, the data packet routing module is used to control data communication between the computational cores;

[0067] The input pulse storage module is used to store the input pulse vectors of each of the neural computation kernels;

[0068] The input pulse decoding module is used to decode the input pulse vector of each of the neural computing kernels;

[0069] The weight decompression and membrane potential accumulation module is used to decompress the synaptic weight array and accumulate the membrane potential according to the compressed storage state of the synaptic weight array in each neural computing nucleus using a corresponding weight decompression algorithm; the weight decompression and membrane potential accumulation module includes a calculation unit, which is used to perform corresponding calculations on the synaptic weights in each neural computing nucleus;

[0070] The leakage integral firing neuron calculation module is used to perform corresponding neurodynamic behavior on the accumulated membrane potential.

[0071] Specifically, this embodiment provides an implementation method for an SNN accelerator, which divides the neural computing kernel into different computing kernels according to different weight array compression methods, and designs corresponding decompression circuits to improve the peak computing power and energy efficiency of the accelerator.

[0072] In a possible embodiment, the SNN accelerator in this solution is a hybrid weighted compressed multi-core heterogeneous spiking neural network accelerator, employing an on-chip near-memory computing architecture, with input and output using an asynchronous two-way handshake protocol. See still. Figure 2 The overall architecture is as follows Figure 2 As shown in (a), it consists of 16 computational cores. The 16 computational cores use three matrix compression methods, DENSE, BITMASK and CSR (Compressed Sparse Row), to store synaptic weights. Therefore, they are divided into three types of computational cores: the first computational core is the DENSE computational core, the second computational core is the BITMASK computational core, and the third computational core is the CSR computational core. The main differences between these three types of computational cores are that the weight storage compression algorithms are different and that the DENSE computational core supports reconfigurable crossbars.

[0073] In some possible implementations, the block diagram of a single computational core is as follows: Figure 2 As shown in (b), each computational core includes a data packet routing module, an input pulse storage module, an input pulse decoding module, a weight storage module, a weight decompression and accumulated membrane potential module, and a leakage integral firing neuron computation module.

[0074] Specifically, the packet routing module is mainly used for inter-core communication within the accelerator. It encodes the pulse results output by the local leaky integral distribution neuron computation module into Address Event Representation (AER) packets, containing spatiotemporal information such as the target address of the pulse and its corresponding biological cycle. It also receives packets input from each direction and selects the corresponding routing direction based on the target address of the packet. The packet routing module also supports one-to-many broadcast routing.

[0075] In some possible implementations, the input pulse storage module is primarily used to store the input pulses for each computing core.

[0076] In a possible embodiment, the BITMASK and CSR computation cores comprise a 256×256 BRAM. Each word address in the BRAM corresponds to a timestep in the spiking neural network, and each bit value is either 1 or 0 to indicate the presence or absence of a pulse. The DENSE computation core comprises a 1024×64 BRAM. In fully connected mode, every 9 addresses correspond to a timestep in the spiking neural network, and each bit value is either 1 or 0 to indicate the presence or absence of a pulse. In convolutional mode, each address represents a pixel in the input feature map (containing all input channels), and each bit value is either 1 or 0 to indicate the presence or absence of a pulse.

[0077] In some possible implementations, the input pulse decoding module is primarily used to decode the pulse vector transmitted from the input pulse storage module. In each clock cycle, the input pulse decoding module receives a multi-bit pulse vector. The address of the valid pulse (i.e., the position of a 1 in the multi-bit pulse vector) is obtained using the following formula:

[0078] onehot_address=bitmap&(~(bitmap-1)) (2)

[0079] Here, onehot_address represents the address of the valid pulse, and bitmap represents the time step of the spiking neural network corresponding to every 9 addresses.

[0080] In some possible implementations, the weight storage module is primarily used to store the synaptic weights of each computational core, with a weight precision of 8 bits.

[0081] In a possible embodiment, the weight storage module of the first computational core is a 576×512 BRAM, which is used to store the dense 576×64 reconfigurable synaptic cross array weights.

[0082] Specifically, for the first computing core, the DENSE computing core, this module mainly consists of a 576×512 BRAM, which is used to store dense 576×64 Crossbar weights.

[0083] In a possible embodiment, the weight storage module of the second computing core is a 256×1296 BRAM.

[0084] In a possible embodiment, the weight storage module of the second computational core includes a row offset module, a bitmap module, and a non-zero weight module. The row offset module, bitmap module, and non-zero weight module are respectively used to store the row offset, bitmap, and non-zero weight of the synaptic weights in the second computational core.

[0085] Specifically, for the second computing core, the BITMASK computing core, this module mainly consists of a 256×1296 BRAM. This module can be further divided into three parts: a row offset module, a bitmap module, and a non-zero weight module, which are used to store row offsets, bitmaps, and non-zero weights, respectively. It can support at least 50% weight sparsity of 256×256 Crossbar weights.

[0086] In a possible embodiment, the weight storage module of the third computing core is a 256×336 BRAM.

[0087] In a possible embodiment, the weight storage module of the third computational core includes an odd-row offset module, an even-row offset module, a column index module, and a non-zero weight module. The odd-row offset module, even-row offset module, column index module, and non-zero weight module are respectively used to store the odd-row offset, even-row offset, column and non-zero weight of the synaptic weight in the second computational core.

[0088] Specifically, for the third computational core, which is the CSR computational core, this module mainly consists of a 256×336 BRAM. This module can be further divided into four parts: an odd-row offset module, an even-row offset module, a column index module, and a non-zero weight module, which are used to store the odd-row offset, even-row offset, column non-zero weight, and non-zero weight, respectively. It can support at least 92.19% weight sparsity with 256×256 Crossbar weights.

[0089] In some possible implementations, the weight decompression and membrane potential accumulation module is used to decompress the synaptic weight array and accumulate the membrane potential according to the compressed storage state of the intranuclear synaptic weight array of each neural computation nucleus.

[0090] In a possible embodiment, the weight decompression and accumulation membrane potential module includes a calculation unit for performing corresponding calculations on the synaptic weights within each of the neural computational nuclei.

[0091] In a possible embodiment, in the first computational core, the computational unit of the weight decompression and membrane potential accumulation module includes 64 first processing units and 1 first allocation algorithm logic unit. The 64 first processing units are 64 adders, which are used to obtain 64 weights. The first allocation algorithm logic unit is used to accumulate the 64 weights obtained by the 64 first processing units onto the membrane potential of the corresponding neuron within one cycle.

[0092] Specifically, for the first computational kernel, which is the DENSE computational kernel, the computational unit has a total of 64 processing units (PEs), which are 64 adders. The computational unit contains allocation algorithm logic, which can accumulate 64 weights onto the membrane potential of the corresponding neuron in one cycle.

[0093] In a possible embodiment, in the second computational core, the computational unit of the weight decompression and membrane potential accumulation module includes 32 second processing units and 1 second allocation algorithm logic unit. The 32 second processing units are used to judge the weight values ​​of the 32 weight storage addresses, and when the weight values ​​are non-zero, they allocate and calculate the non-zero weight values. The second allocation algorithm logic unit is used to accumulate the non-zero weight values ​​obtained by each second processing unit to the membrane potential of the corresponding neuron within one cycle.

[0094] Specifically, the second computing core, the BITMASK computing core, has a total of 32 processing units (PEs), and each computing unit contains allocation algorithm logic, such as... Figure 3 As shown. It mainly consists of the following four steps:

[0095] Step 1: The valid pulse address first indexes the row offset and bitmap of the row. In order to reduce the latency of subsequent combinational logic, the bitmap is retrieved in 32-bit increments.

[0096] Step 2: Determine if the 32-bit bitmap is entirely zero. If it is, it means these 32 positions have no non-zero weights, and you will return to Step 1. Otherwise, it means these 32 positions have non-zero weights, and you will proceed to Step 3.

[0097] Step 3: Check each of the 32 bitmap positions for a value of 0. If a value is 0, return to Step 2. Otherwise,

[0098] Step four;

[0099] Step 4: This step involves weight allocation and calculation. The calculation of s[i] can be found in [reference needed]. Figure 5 The left half (the main logic is to add the bitmaps one by one).

[0100] In a possible embodiment, the third computational core comprises 32 third processing units and 1 third allocation algorithm logic unit in the weight decompression and membrane potential accumulation module. The 32 third processing units are used to determine the weight values ​​of the 32 weight storage addresses. If the weight value is non-zero, they obtain the column of the non-zero weight value and the start and end nodes of the non-zero weight value. The third allocation algorithm logic unit is used to accumulate the non-zero weight values ​​between the start and end nodes onto the membrane potential of the neurons in the column where the non-zero weight value is located.

[0101] Specifically, for the third computing core, which is the CSR computing core, the computing unit has a total of 32 PEs, and this computing unit includes allocation algorithm logic, which is as follows: Figure 4 As shown. The valid pulse address first indexes the odd-numbered row offset and the even-numbered row offset. These two row offset values ​​then become the starting and ending nodes for non-zero weight columns and non-zero weights, respectively. Assuming the odd-numbered row offset and even-numbered row offset corresponding to a certain valid pulse address are 32 and 65, respectively, then based on these two nodes, the weights W 32-W 63 and W 64-W 65, and their corresponding columns CI 32-CI63 and CI 64-CI 65, can be accessed in two cycles. Next, the allocator uses CI as the neuron index and adds the corresponding W to the membrane potential of the CI-th neuron.

[0102] In some possible implementations, the leakage integral issuing neuron computation module is mainly used for threshold comparison and leakage detection of the accumulated membrane potential. The membrane potential portion passed from the weight decompression and membrane potential accumulation module is first added to the membrane potential of the previous time step, and then added to the leakage value. The result is compared with the threshold; if it exceeds the threshold, a pulse is emitted to reset the membrane potential, and the reset membrane potential is written back to RAM. To improve system throughput, a ping-pong cache structure is used for storing the membrane potential.

[0103] In some possible implementations, this scheme demonstrates several common matrix compression algorithms. Figure 5 Schematic diagrams of several matrix compression algorithms provided in embodiments of the present invention, such as... Figure 5As shown, this scheme also provides the matrix compression storage algorithm Coordinate (COO). Therefore, the matrix compression storage algorithms in this scheme specifically include Coordinate (COO), Compressed Sparse Row (CSR), BITMASK, and the original storage format DENSE. COO divides the original matrix into three parts: row index, column index, and non-zero values; CSR divides the original matrix into three parts: row offset, column index, and non-zero values; ELL is a diagonal storage format that divides the original matrix into two parts: column index and non-zero values; BITMASK divides the original matrix into two parts: bitmap and non-zero values. Two points need to be noted here: First, because ELL has strict requirements for the arrangement of data in the matrix, it is not suitable as a storage algorithm for synaptic weights (because the distribution of non-zero values ​​in synaptic weights is usually random); second, to achieve the event-driven characteristics of spiking neural networks, the BITMASK algorithm requires additional row offsets to help index the weights, i.e., additional storage space is needed. For a 256×256 synaptic cross array, assuming there are n non-zero values, Table 1 summarizes the storage space usage of the above compression algorithms.

[0104] Table 1

[0105]

[0106] In a possible embodiment, Figure 6 This is a graph showing the relationship between storage space and the proportion of non-zero values ​​under different matrix compression storage algorithms provided in this embodiment of the invention. Figure 6 The relationship between storage space and the proportion of non-zero values ​​under different matrix compression algorithms was further characterized, from... Figure 6 As can be seen, CSR has the highest storage efficiency when the proportion of non-zero values ​​is less than or equal to 12.5%. BITMASK has the highest storage efficiency when the proportion of non-zero values ​​is greater than 12.5% ​​but less than or equal to 86.7%. DENSE has the highest storage efficiency when the proportion of non-zero values ​​is greater than 86.7%. The above settings of this invention provide a basis for selecting a hybrid compression algorithm for spiking neural networks, namely, the proportion of non-zero values ​​in that layer of the spiking neural network model should fall within a certain range. Figure 6 Within different intervals of the x-axis, the compression algorithm with the highest storage efficiency is selected. The applicable scenarios for the three core types in this invention are shown in Table 2.

[0107] Table 2

[0108]

[0109] In some possible implementations, for the DENSE computation kernel, since it needs to be compatible with the computation of fully connected layers of convolutional layers, the weight storage first needs to be partitioned.

[0110] In a possible embodiment, Figure 7 This is a schematic diagram of the weight partitioning of the DENSE computation kernel provided in an embodiment of the present invention, as shown below. Figure 7 As shown, for the same 576×512 BRAM, in convolutional mode, each address of the BRAM corresponds to the weights at the same location in all convolutional kernels, and the same location at different addresses in the BRAM corresponds to all the weights of the same convolutional kernel. In fully connected mode, each address of the BRAM corresponds to the weights of the same input to all neurons, and the same location at different addresses in the BRAM corresponds to all the weights of the same neuron.

[0111] Furthermore, in convolution mode, input pulses within different sliding windows can be reused without repeated reading; the first computational kernel supports a configurable convolution kernel size.

[0112] Specifically, Figure 8 This is a schematic diagram of inter-window pulse multiplexing provided in an embodiment of the present invention, as shown below. Figure 8 As shown, in convolution mode, input pulses from different sliding windows can be reused without repeated reading. For a 3×3 convolution kernel with a stride of 1, pulses at 6 addresses can be reused between adjacent sliding windows. Only the remaining 3 addresses need to be updated. The update strategy for these 3 addresses can be implemented using the pulse address register update strategy in convolution mode.

[0113] More specifically, taking a 3×3 convolution kernel and stride = 1 as an example, the pulse address register update strategy for the convolution mode in the above embodiment can be specifically described as follows: In the initial state, the nine address registers a0-a8 are 0, 1, 2, 32, 33, 34, 64, 65, and 66, respectively. If the total input feature map size is 3×3, the calculation will end; otherwise, it will jump to the right sliding state. In the right sliding state, a2, a5, and a8 are incremented by 1, and then a judgment is made on whether the total number of sliding windows and the number of sliding windows for the current row have been reached. If the total number of sliding windows has been reached, the calculation ends; if the total number of sliding windows has not been reached, but the number of sliding windows for the current row has been reached, then it will jump to the down sliding state. If neither of the above two sliding window counts has been reached, it will continue to stay in the right sliding state. In the down sliding state, a6, a7, and a8 are incremented by 32, and then a direction judgment is made to determine whether the next state is left or right sliding. In the left sliding state, a0, a3, and a6 are decremented by 1, and the remaining judgments are similar to those in the right sliding state. The DENSE computation kernel supports configurable kernel sizes, and the configurable types are shown in Table 3.

[0114] Table 3

[0115] kernel size 1×1.3×3,5×5.7×7 Maximum input channel 64，64，23，0-11 Maximum output channel 64 Maximum input feature map size 32×32 Step length 1.2

[0116] The SNN accelerator proposed in this invention includes 16 cores (computational cores), which are connected to each other via a 2D-Mesh Network on Chip (NoC). The 16 cores incorporate three types of weight compression and decompression algorithms: 8 DENSE computational cores, 4 CSR computational cores, and 4 BITMASK computational cores. The DENSE computational cores propose a reconfigurable crossbar that integrates convolutional modes, enabling this core to run both convolutional and fully connected networks. Each of the 16 cores consists of a packet routing module, an input pulse storage module, an input pulse decoding module, a weight storage module, a weight decompression and membrane potential accumulation module, and a Leaky Integrate-and-Fire (LIF) neuron computation module. The weight storage module and the weight decompression and membrane potential accumulation module differ in structure among the three types of computational cores, while the remaining modules have the same structure.

[0117] In specific embodiments, this invention, based on a brain-like neuromorphic architecture, uses three matrix compression storage methods—CSR (Compressed Sparse Row), BITMASK, and DENSE—to store synaptic weights, and designs corresponding decompression circuits to improve the accelerator's peak computing power and energy efficiency. Furthermore, to increase the accelerator's flexibility, for the DENSE computation kernel, this embodiment proposes a configurable Crossbar structure, enabling it to run both convolutional layer SNN models and fully connected layer SNN models.

[0118] The SNN accelerator provided in this invention, compared to spiking neural network accelerators with no weighted compression storage algorithm, utilizes the sparsity of synaptic weights in spiking neural networks to design corresponding matrix compression and decompression circuits, skipping access and calculation of zero-value weights, thereby improving peak computing power, throughput, and energy efficiency. Compared to spiking neural network accelerators using a single-weight compression storage algorithm, the storage efficiency of matrix compression algorithms under different non-zero value ratios is fully discussed. A multi-core heterogeneous spiking neural network accelerator is designed using the differences in synaptic weight sparsity between different layers to maximize matrix compression efficiency, thereby improving peak computing power, throughput, and energy efficiency. In addition, this invention also proposes a reconfigurable Crossbar structure, enhancing the flexibility of the SNN accelerator.

[0119] In some possible embodiments of the present invention, a hybrid compressed storage method for SNN synaptic weights is also provided, the method being implemented using an SNN accelerator as provided in any of the above embodiments, such as... Figure 9 As shown, the method includes:

[0120] Step 910: Obtain the proportion of non-zero values ​​of synaptic weights in the synaptic weight array of the current computation layer of the SNN model. The proportion of non-zero values ​​is used to determine whether the synaptic weight array is a dense representation, a first sparse representation, or a second sparse representation.

[0121] Step 920: Based on the proportion of non-zero values, determine the synaptic weight compression storage algorithm used in the current computation layer of the SNN model, wherein the weight compression storage algorithm includes a weightless compression storage algorithm, a first weight compression storage algorithm, and a second compression storage algorithm;

[0122] Step 930: Determine the computation kernel used in the current computation layer of the SNN model according to the synaptic weight compression storage algorithm; Step 940: Perform computation on the current computation layer of the SNN model using the computation kernel.

[0123] In some possible implementations, the step of determining the synaptic weight compression storage algorithm used in the current computation layer of the SNN model based on the proportion of non-zero values ​​specifically includes:

[0124] Based on the proportion of non-zero values, determine the storage space required when the current computational layer of the SNN model adopts the compression storage algorithm for each synaptic weight;

[0125] Based on the storage space, determine the storage efficiency of the compression storage algorithm for each synaptic weight;

[0126] The synaptic weight compression storage algorithm with the highest storage efficiency is determined as the synaptic weight compression storage algorithm used in the current computation layer of the SNN model. In some possible implementations, the step of determining the computation kernel used in the current computation layer of the SNN model based on the synaptic weight compression storage algorithm specifically includes:

[0127] When the synaptic weight compression storage algorithm is a weightless compression storage algorithm, the computation kernel used in the current computation layer of the SNN model is determined to be the first computation kernel;

[0128] When the synaptic weight compression storage algorithm is the first weight compression storage algorithm, the computation kernel used in the current computation layer of the SNN model is determined to be the second computation kernel;

[0129] When the synaptic weight compression storage algorithm is the second weight compression storage algorithm, the computation kernel used in the current computation layer of the SNN model is determined to be the third computation kernel.

[0130] The SNN synaptic weight hybrid compression storage method provided in this embodiment of the invention has a similar implementation principle and beneficial effects to the SNN accelerator shown in the above embodiment. For details, please refer to the implementation principle and beneficial effects of the SNN accelerator shown in the above embodiment, which will not be repeated here.

[0131] Figure 10 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 10 As shown, the electronic device may include: a processor 1010, a communications interface 1020, a memory 1030, and a communications bus 1040, wherein the processor 1010, the communications interface 1020, and the memory 1030 communicate with each other through the communications bus 1040. The processor 1010 can call logic instructions in the memory 1030 to execute a hybrid compression storage method for SNN synaptic weights. This method includes: obtaining the proportion of non-zero values ​​in the synaptic weight array of the current computational layer of the SNN model, wherein the proportion of non-zero values ​​is used to determine whether the synaptic weight array is a dense representation, a first sparse representation, or a second sparse representation; determining the synaptic weight compression storage algorithm used by the current computational layer of the SNN model based on the proportion of non-zero values, wherein the weight compression storage algorithm includes a weightless compression storage algorithm, a first weight compression storage algorithm, and a second compression storage algorithm; determining the computational kernel used by the current computational layer of the SNN model according to the synaptic weight compression storage algorithm; and performing computation on the current computational layer of the SNN model using the computational kernel.

[0132] Furthermore, the logical instructions in the aforementioned memory 1030 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0133] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the SNN synaptic weight hybrid compression storage method provided by the above methods. The method includes: obtaining the proportion of non-zero values ​​of synaptic weights in the synaptic weight array in the current computation layer of the SNN model, wherein the proportion of non-zero values ​​is used to determine whether the synaptic weight array is a dense representation, a first sparse representation, or a second sparse representation; determining the synaptic weight compression storage algorithm used by the current computation layer of the SNN model based on the proportion of non-zero values, wherein the weight compression storage algorithm includes a weightless compression storage algorithm, a first weight compression storage algorithm, and a second compression storage algorithm; determining the computation kernel used by the current computation layer of the SNN model according to the synaptic weight compression storage algorithm; and performing computation on the current computation layer of the SNN model through the computation kernel.

[0134] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements the SNN synaptic weight hybrid compression storage method provided by the above methods. The method includes: obtaining the proportion of non-zero values ​​of synaptic weights in the synaptic weight array in the current computational layer of the SNN model, wherein the proportion of non-zero values ​​is used to determine whether the synaptic weight array is a dense representation, a first sparse representation, or a second sparse representation; determining the synaptic weight compression storage algorithm used by the current computational layer of the SNN model based on the proportion of non-zero values, wherein the weight compression storage algorithm includes a weightless compression storage algorithm, a first weight compression storage algorithm, and a second compression storage algorithm; determining the computational kernel used by the current computational layer of the SNN model according to the synaptic weight compression storage algorithm; and performing computation on the current computational layer of the SNN model using the computational kernel.

[0135] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0136] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0137] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An SNN accelerator, characterized in that, include: The system comprises 16 neural computation cores, each of which includes a weight storage module. The weight storage module is used to store the synaptic weight array of the neural computation core in either uncompressed or compressed form. The 16 neural computation cores include 8 first computation cores, 4 second computation cores and 4 third computation cores. The weight storage module in the first computation core adopts an unweighted compressed storage algorithm, the weight storage module in the second computation core adopts a first weight compressed storage algorithm, and the weight storage module in the third computation core adopts a second weight compressed storage algorithm. The unweighted compression storage algorithm is used to perform unweighted compression storage on a dense synaptic weight array, the first weighted compression storage algorithm is used to perform compression storage on a first sparse synaptic weight array, and the second weighted compression storage algorithm is used to perform compression storage on a second sparse synaptic weight array; wherein, the density, the first sparsity, and the second sparsity are determined based on the proportion of non-zero values ​​of synaptic weights in the synaptic weight array. The first computational core includes a reconfigurable synaptic cross array, which is used for computation in convolutional networks or fully connected network structures. In convolutional mode, each address of the BRAM corresponds to the weights at the same position in all convolutional kernels, and the same position at different addresses of the BRAM corresponds to all the weights of the same convolutional kernel; in fully connected mode, each address of the BRAM corresponds to the weights of the same input to all neurons, and the same position at different addresses of the BRAM corresponds to all the weights of the same neuron.

2. The SNN accelerator according to claim 1, characterized in that, Each of the neural computation kernels further includes a data packet routing module, an input pulse storage module, an input pulse decoding module, a weight decompression and accumulated membrane potential module, and a leakage integral firing neuron computation module; The data packet routing module is used to control data communication between the computing cores. The input pulse storage module is used to store the input pulse vectors of each of the neural computation kernels; The input pulse decoding module is used to decode the input pulse vector of each of the neural computing kernels; The weight decompression and membrane potential accumulation module is used to decompress the synaptic weight array and accumulate the membrane potential according to the compressed storage state of the synaptic weight array in each neural computing nucleus using a corresponding weight decompression algorithm; the weight decompression and membrane potential accumulation module includes a calculation unit, which is used to perform corresponding calculations on the synaptic weights in each neural computing nucleus; The leakage integral firing neuron calculation module is used to perform corresponding neurodynamic behavior on the accumulated membrane potential.

3. The SNN accelerator according to claim 2, characterized in that, The weight storage module of the first computing core is a 576×512 BRAM, which is used to store the dense 576×64 reconfigurable synaptic cross array weights.

4. The SNN accelerator according to claim 2, characterized in that, The weight storage module of the second computing core is a 256×1296 BRAM.

5. The SNN accelerator according to claim 4, characterized in that, The weight storage module of the second computational core includes a row offset module, a bitmap module, and a non-zero weight module. The row offset module, bitmap module, and non-zero weight module are used to store the row offset, bitmap, and non-zero weight of the synaptic weights in the second computational core, respectively.

6. The SNN accelerator according to claim 2, characterized in that, The weight storage module of the third computing core is a 256×336 BRAM.

7. The SNN accelerator according to claim 6, characterized in that, The weight storage module of the third computing core includes an odd row offset module, an even row offset module, a column index module, and a non-zero weight module. The odd row offset module, even row offset module, column index module, and non-zero weight module are respectively used to store the odd row offset, even row offset, column and non-zero weight of the synaptic weight in the second computing core.

8. The SNN accelerator according to claim 3, characterized in that, In the first computational core, the computational unit of the weight decompression and membrane potential accumulation module includes 64 first processing units and 1 first allocation algorithm logic unit. The 64 first processing units are 64 adders, which are used to obtain 64 weights. The first allocation algorithm logic unit is used to accumulate the 64 weights obtained by the 64 first processing units onto the membrane potential of the corresponding neuron within one cycle.

9. The SNN accelerator according to claim 5, characterized in that, In the second calculation core, the calculation unit of the weight decompression and membrane potential accumulation module includes 32 second processing units and 1 second allocation algorithm logic unit. The 32 second processing units are used to judge the weight values ​​of the 32 weight storage addresses. If the weight value is a non-zero weight value, the non-zero weight value is allocated and calculated. The second allocation algorithm logic unit is used to accumulate the non-zero weight values ​​obtained by each second processing unit to the membrane potential of the corresponding neuron within one cycle.

10. The SNN accelerator according to claim 7, characterized in that, In the third computational core, the computational unit of the weight decompression and membrane potential accumulation module comprises 32 third processing units and 1 third allocation algorithm logic unit. The 32 third processing units are used to judge the weight values ​​of the 32 weight storage addresses. If the weight value is non-zero, they obtain the column of the non-zero weight value and the start and end nodes of the non-zero weight value. The third allocation algorithm logic unit is used to accumulate the non-zero weight values ​​between the start and end nodes onto the membrane potential of the neurons in the column where the non-zero weight value is located.

11. The SNN accelerator according to claim 2, characterized in that, In convolutional network structures, input pulses within different convolutional sliding windows can be reused.

12. The SNN accelerator according to claim 2, characterized in that, The kernel size of the convolutional structure network supported by the first computation kernel is configurable.

13. A method for hybrid compressed storage of SNN synaptic weights, characterized in that, The method is implemented using the SNN accelerator as described in any one of claims 1-12, and the method includes: Obtain the proportion of non-zero values ​​of synaptic weights in the synaptic weight array of the current computation layer of the SNN model. The proportion of non-zero values ​​is used to determine whether the synaptic weight array is a dense representation, a first sparse representation, or a second sparse representation. Based on the proportion of non-zero values, the synaptic weight compression storage algorithm used in the current computation layer of the SNN model is determined, wherein the weight compression storage algorithm includes a weightless compression storage algorithm, a first weight compression storage algorithm, and a second compression storage algorithm. Based on the synaptic weight compression storage algorithm, the computational kernel used in the current computational layer of the SNN model is determined; The computation kernel performs calculations on the current computation layer of the SNN model.

14. The SNN synaptic weight hybrid compressed storage method according to claim 13, characterized in that, The steps for determining the synaptic weight compression storage algorithm used in the current computation layer of the SNN model based on the proportion of non-zero values ​​specifically include: Based on the proportion of non-zero values, determine the storage space required when the current computational layer of the SNN model adopts the compression storage algorithm for each synaptic weight; Based on the storage space, determine the storage efficiency of the compression storage algorithm for each synaptic weight; The synaptic weight compression storage algorithm with the highest storage efficiency is determined to be the synaptic weight compression storage algorithm used in the current computation layer of the SNN model.

15. The SNN synaptic weight hybrid compressed storage method according to claim 13, characterized in that, The steps for determining the computational kernel used in the current computational layer of the SNN model based on the synaptic weight compression storage algorithm specifically include: When the synaptic weight compression storage algorithm is a weightless compression storage algorithm, the computation kernel used in the current computation layer of the SNN model is determined to be the first computation kernel; When the synaptic weight compression storage algorithm is the first weight compression storage algorithm, the computation kernel used in the current computation layer of the SNN model is determined to be the second computation kernel; When the synaptic weight compression storage algorithm is the second weight compression storage algorithm, the computation kernel used in the current computation layer of the SNN model is determined to be the third computation kernel.

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