A package structure for improving warpage and heat dissipation and a manufacturing method thereof

Abstract

This invention discloses a packaging structure and its fabrication method for improving warpage and heat dissipation. The packaging structure includes a silicon wafer with grooves and vias formed on the back side. Chip I is disposed within the grooves, and metal is filled into the vias. Chip II is disposed on Chip I and the metal. A thin chip is disposed on the front side of the silicon wafer. This invention deposits a dielectric layer on the front side of the silicon wafer, then deposits a passivation layer and a redistribution layer on the dielectric layer, and then bonds glass or ceramic materials, which helps to improve warpage. Grooves and vias are formed on the back side of the silicon wafer, and Chip I is then attached into the grooves. Electroplating is then performed to fill the vias, and Chip II is soldered onto the surface and filled with a base adhesive, which further improves warpage and increases heat dissipation. Finally, the glass or ceramic materials are removed, and the thin chip is connected on the redistribution layer, with the gap between them filled with a filler material. This enables stacked interconnection in the vertical direction of the die, reducing warpage. The overall fabrication process is efficient, with high product yield and low manufacturing cost, making it suitable for industrial-scale application.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to a packaging structure and its manufacturing method that improves warpage and heat dissipation. Background Technology

[0002] As people's demands for the performance of electronic products continue to increase, semiconductor packaging structures are developing towards miniaturization, high density, multifunctionality, and system integration. Current packaging structures directly interconnect chips vertically via adapter boards, resulting in severe warpage issues. This significantly limits the diversification and integration density of chip integration, presenting considerable challenges in integrating multiple chips or components. Furthermore, product reliability and heat dissipation need improvement. In addition, existing packaging processes are complex, have high production costs, and require further improvement in product yield. Summary of the Invention

[0003] To address the technical problems existing in the prior art, the present invention aims to provide a packaging structure and its manufacturing method that improves warpage and heat dissipation.

[0004] To achieve the above objectives and technical effects, the technical solution adopted by this invention is as follows:

[0005] A packaging structure for improving warpage and heat dissipation includes a silicon wafer with a groove and a through hole on the back side of the silicon wafer. A chip I is disposed in the groove, and the through hole is filled with metal. A chip II is disposed on the chip I and the metal. A thin chip is disposed on the front side of the silicon wafer.

[0006] Furthermore, a dielectric layer is provided on the front side of the silicon wafer, and a passivation layer and a redistribution layer are provided on the dielectric layer, with pads formed on the outermost surface.

[0007] Furthermore, the front side of the silicon wafer is connected to a thin chip via a redistribution layer, the thickness of which is 50–150 micrometers, and the gap between the redistribution layer and the thin chip is filled with a filler material.

[0008] Furthermore, the chip I is fixed in the groove by an adhesive material, and the chip I is provided in one or more stacked positions.

[0009] Furthermore, the gap between chip I and the metal and chip II is filled with adhesive to improve warpage and increase heat dissipation.

[0010] This invention also discloses a method for fabricating a packaging structure that improves warpage and heat dissipation, comprising the following steps:

[0011] Step 1: Deposit a dielectric layer on the surface of the silicon wafer, which serves as an insulating layer and a silicon etching cutoff layer;

[0012] Step 2: Passivation layer and redistribution layer are sequentially deposited on the dielectric layer, and pads are formed on the outermost surface. Then, glass or ceramic materials are bonded.

[0013] Step 3: Etch the back of the silicon wafer to form grooves;

[0014] Step 4: Etch on the back of the silicon wafer to form through-holes;

[0015] Step 5: Place chip I into the groove;

[0016] Step 6: Passivate the vias and silicon wafer surface. Fill the vias with metal through an electroplating process, remove the surface metal, and then form a redistribution structure.

[0017] Step 7: Weld chip II onto the surface of the semi-finished product obtained in step 6, and fill the gap between the two with primer to improve warping and increase heat dissipation;

[0018] Step 8: Remove the glass or ceramic material, connect the thin chip to the redistribution layer, fill the gap between the redistribution layer and the thin chip with filler material, and create solder joints on the pads.

[0019] Furthermore, in step one, the dielectric layer is made of silicon oxide or silicon nitride, with a thickness of 0.5 to 2 micrometers.

[0020] Furthermore, in step five, chip I is fixed into the groove by adhesive material. Chip I is provided as one or more stacked to improve warping in the X and Y directions.

[0021] Furthermore, in step six, the vias and silicon wafer surface are first passivated by depositing a node layer, then the vias are filled with metal by electroplating, and after the surface metal is removed, a redistribution structure is formed. The thickness of the node layer is 0.5 to 2 micrometers.

[0022] Furthermore, in step eight, the thickness of the thin chip is 50 to 150 micrometers.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] This invention discloses a packaging structure and its fabrication method for improving warpage and heat dissipation. First, a dielectric layer is deposited on the front side of a silicon wafer. Then, a passivation layer and a redistribution layer are sequentially deposited on the dielectric layer. Next, glass or ceramic material is bonded, which helps improve warpage. Grooves and vias are formed on the back side of the silicon wafer. Chip I to be mounted is then placed into the grooves, and electroplating is performed to fill the vias. Chip II is then soldered onto the surface and filled with a base adhesive to improve warpage and increase heat dissipation. Finally, the glass or ceramic material is removed, and a thin chip is connected to the redistribution layer. A filler material is used to fill the gap between the redistribution layer and the thin chip. This design approach can reduce warpage in the vertical stacking interconnect of the die, while improving product reliability and heat dissipation. The overall fabrication process is simple and efficient, with high product yield and low manufacturing cost, making it suitable for industrial-scale application. Attached Figure Description

[0025] Figure 1 This is a structural schematic diagram of step one of the present invention;

[0026] Figure 2 This is a schematic diagram of the structure of step two of the present invention;

[0027] Figure 3 This is a schematic diagram of step three of the present invention;

[0028] Figure 4 This is a top view of the groove in step three of the present invention;

[0029] Figure 5 This is a diagram showing the warping force direction in step three of the present invention;

[0030] Figure 6 This is a structural schematic diagram of step four of the present invention;

[0031] Figure 7 This is a top view of the through hole in step four of the present invention;

[0032] Figure 8 This is a structural schematic diagram of step five of the present invention;

[0033] Figure 9 This is a schematic diagram of step six of the present invention;

[0034] Figure 10 This is a structural schematic diagram of step seven of the present invention;

[0035] Figure 11 This is a schematic diagram of step eight of the present invention. Detailed Implementation

[0036] The present invention will now be described in detail so that its advantages and features can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0037] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0038] like Figure 1-11 As shown, this invention discloses a packaging structure for improving warpage and heat dissipation, including a silicon wafer 2. A dielectric layer 1 is disposed on the front side of the silicon wafer 2. A passivation layer 3 and a redistribution layer 4 are disposed on the dielectric layer 1. A pad 5 is formed on the outermost surface. The front side of the silicon wafer 2 is connected to a thin chip 16 through the redistribution layer 4. The thickness of the thin chip 16 is 50-150 micrometers. The gap between the redistribution layer 4 and the thin chip 16 is filled with a filler material 17. A groove 7 and a through hole 8 are formed on the back side of the silicon wafer 2. Chip I 9 is fixed in the groove 7 by an adhesive material 10. One or more chips I 9 are stacked. The through hole 8 is filled with metal 11. Chip II 14 is disposed on chip I 9 and metal 11. The gap between chip I 9, metal 11 and chip II 14 is filled with a base adhesive 15 to improve warpage and increase heat dissipation.

[0039] Chip I 9, Chip II 14, and Thin Chip 16 are selected according to customer needs, and will not be elaborated here.

[0040] This invention also discloses a method for fabricating a packaging structure that improves warpage and heat dissipation, comprising the following steps:

[0041] Step 1: As Figure 1 As shown, a dielectric layer 1 is deposited on the surface of silicon wafer 2, serving as an insulating layer and a silicon etching stop layer. The dielectric layer 1 can be made of materials such as silicon oxide or silicon nitride, with a thickness of 0.5–2 micrometers.

[0042] Step Two: As Figure 2 As shown, a passivation layer 3 and a redistribution layer 4 are sequentially disposed on the dielectric layer 1, with pads 5 formed on the outermost surface, and then glass 6 or ceramic material is bonded. For the purpose of forming a high-density package, the linewidth and spacing of the redistribution layer 4 in this step can be 2 micrometers, 2 micrometers, or even 1.5 micrometers, 1.5 micrometers. The number of redistribution layers can be two or more. Redistribution is typically copper wiring. The passivation layer 3 can be a solid dry film or PI adhesive, with a thickness of 10-20 micrometers. By bonding glass 6 or ceramic material, the warpage problem in step three can be controlled and improved. If the chip is mounted in this step instead of bonding glass 6 or ceramic material, a smile-shaped warpage will occur, and in step three, the groove corners will be subjected to extended stress, causing a risk of microcracks.

[0043] Step 3: As Figure 3-5 As shown, the thickness of silicon wafer 2 is reduced by grinding. On the back side of silicon wafer 2, a groove 7 is formed by silicon oxide etching and silicon etching. The volume of the groove 7 is adapted to the volume of the chip I9 to be mounted. The morphology of the groove 7 after etching is as follows. Figure 4 As shown. The shape of the etched grooves is offset from the dicing channels (65-80 micrometer dicing channels are created through exposure development or etching; the dicing channels are between the dies) by an angle of 10° to 45°, achieved through photolithography. This is based on the direction of the warping force. Figure 5 If the forces are superimposed in the direction of the force, the warping will increase. The superposition of forces in the vertical direction can be reduced by shifting the angle, thereby improving the warping.

[0044] Step Four: As Figure 6-7 As shown, via 8 is formed by silicon etching process, and the morphology after etching is as follows. Figure 7 As shown, via 8 penetrates the silicon wafer 2 but does not penetrate the dielectric layer 1, and the diameter of via 8 is 10 to 80 micrometers;

[0045] Step 5: As Figure 8 As shown, chip I9 is ​​placed into the groove 7 and fixed with adhesive material 10. The embedded chip I9 can be a single chip or multiple stacked chips. This placement method can improve warping in the X and Y directions;

[0046] Step Six: As Figure 9 As shown, the via 8 and the silicon wafer surface are passivated by depositing a node layer 12. The node layer 12 can be made of materials such as silicon oxide or silicon nitride, and its thickness is 0.5 to 2 micrometers. The via 8 is filled with metal 11 through an electroplating process, and the surface metal is removed by methods such as grinding, chemical mechanical polishing, and etching. A redistribution structure 13 is then formed, which can be one layer or multiple layers.

[0047] Step Seven: As Figure 10 As shown, chip II 14 is welded to the surface of the semi-finished product obtained in step six, and primer 15 is filled in the gap between the two to improve warping and increase heat dissipation;

[0048] Step 8: As Figure 11 As shown, after removing the glass 6 or ceramic material, a thin chip 16 with a thickness of 50-150 micrometers is connected to the redistribution layer 4. Then, the gap between the redistribution layer 4 and the thin chip 16 is filled with filler material 17, and finally, solder joints 18 are made on the pads 5.

[0049] Example 1

[0050] like Figure 1-11As shown, a packaging structure for improving warpage and heat dissipation includes a silicon wafer 2. A dielectric layer 1 is disposed on the front side of the silicon wafer 2. A passivation layer 3 and a redistribution layer 4 are disposed on the dielectric layer 1. A pad 5 is formed on the outermost surface. The front side of the silicon wafer 2 is connected to a thin chip 16 through the redistribution layer 4. The thickness of the thin chip 16 is 50 micrometers. The gap between the redistribution layer 4 and the thin chip 16 is filled with a filler material 17. A groove 7 and a through hole 8 are formed on the back side of the silicon wafer 2. Chip I 9 is fixed in the groove 7 by an adhesive material 10. Chip I 9 is provided in one location. The through hole 8 is filled with metal 11. Chip II 14 is disposed on chip I 9 and metal 11. The gap between chip I 9, metal 11 and chip II 14 is filled with a base adhesive 15 to improve warpage and increase heat dissipation.

[0051] A method for fabricating a packaging structure that improves warpage and heat dissipation includes the following steps:

[0052] Step 1: As Figure 1 As shown, a dielectric layer 1 is deposited on the surface of silicon wafer 2, serving as both an insulating layer and a silicon etching stop layer. Dielectric layer 1 is made of silicon oxide and has a thickness of 0.5 micrometers.

[0053] Step Two: As Figure 2 As shown, a passivation layer 3 and a redistribution layer 4 are sequentially disposed on dielectric layer 1, with pads 5 formed on the outermost surface, and then bonding glass 6 is applied. For the purpose of forming a high-density package, the linewidth and spacing of the redistribution layer 4 in this step are 2 micrometers and 2 micrometers, respectively. Two redistribution layers are used. The redistribution is typically copper wiring. The passivation layer 3 is a solid dry film with a thickness of 10 micrometers. The bonding glass 6 can control and improve warpage during step three. If the chip is mounted in this step instead of bonding glass 6, a smile-shaped warpage will occur, and in step three, the groove corners will be subjected to extended stress, creating a risk of microcracks.

[0054] Step 3: As Figure 3-5 As shown, the thickness of silicon wafer 2 is reduced by grinding. On the back side of silicon wafer 2, a groove 7 is formed by silicon oxide etching and silicon etching. The volume of the groove 7 is adapted to the volume of the chip I9 to be mounted. The morphology of the groove 7 after etching is as follows. Figure 4 As shown. The etched groove shape is offset by 10° from the cut channel (a 65-micron cut channel is created through exposure development or etching; the cut channel is between the die pieces), achieved through photolithography. This is based on the warping force direction. Figure 5 If the forces are superimposed in the direction of the force, the warping will increase. The superposition of forces in the vertical direction can be reduced by shifting the angle, thereby improving the warping.

[0055] Step Four: As Figure 6-7 As shown, via 8 is formed by silicon etching process, and the morphology after etching is as follows. Figure 7As shown, via 8 penetrates the silicon wafer 2 but does not penetrate the dielectric layer 1, and the diameter of via 8 is 10 micrometers;

[0056] Step 5: As Figure 8 As shown, chip I9 is ​​placed into the groove 7 and fixed with adhesive material 10. The embedded chip I9 is ​​a single chip; this placement method can improve warping in the X and Y directions.

[0057] Step Six: As Figure 9 As shown, the via 8 and the silicon wafer surface are passivated by depositing a node layer 12, which is made of silicon oxide and has a thickness of 0.5 micrometers. The via 8 is filled with metal 11 through electroplating, and the surface metal is removed by grinding, chemical mechanical polishing, etching, and other methods. A redistribution structure 13 is then formed, which can be a single layer.

[0058] Step Seven: As Figure 10 As shown, chip II 14 is welded to the surface of the semi-finished product obtained in step six, and primer 15 is filled in the gap between the two to improve warping and increase heat dissipation;

[0059] Step 8: As Figure 11 As shown, after removing the glass 6, a thin chip 16 with a thickness of 50 micrometers is connected to the redistribution layer 4. Then, the gap between the redistribution layer 4 and the thin chip 16 is filled with filler material 17, and finally, solder joints 18 are made on the pads 5.

[0060] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.

[0061] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for fabricating a packaging structure that improves warpage and heat dissipation, characterized in that, The packaging structure for improving warpage and heat dissipation includes a silicon wafer with a groove and a through hole on the back side. A chip I is disposed in the groove, and the through hole is filled with metal. A chip II is disposed on the chip I and the metal. A thin chip is disposed on the front side of the silicon wafer, and the thickness of the thin chip is 50~150 micrometers. The manufacturing method includes the following steps: Step 1: Deposit a dielectric layer on the surface of the silicon wafer, which serves as an insulating layer and a silicon etching cutoff layer; Step 2: Passivation layer and redistribution layer are sequentially deposited on the dielectric layer, and pads are formed on the outermost surface. Then, glass or ceramic materials are bonded. Step 3: Reduce the thickness of the silicon wafer by grinding. On the back of the silicon wafer, form a quadrilateral groove by etching silicon oxide and silicon. The shape of the etched groove is offset from the cutting track by an angle of 10° to 45°. Step 4: Etch on the back of the silicon wafer to form through-holes; Step 5: Place chip I into the groove; Step 6: Passivate the vias and silicon wafer surface. Fill the vias with metal through an electroplating process, remove the surface metal, and then form a redistribution structure. Step 7: Weld chip II onto the surface of the semi-finished product obtained in step 6, and fill the gap between the two with primer to improve warping and increase heat dissipation; Step 8: Remove the glass or ceramic material, connect the thin chip to the redistribution layer, fill the gap between the redistribution layer and the thin chip with filler material, and create solder joints on the pads. A dielectric layer is provided on the front side of the silicon wafer, and a passivation layer and a redistribution layer are provided on the dielectric layer, with pads formed on the outermost surface.

2. The method for manufacturing a packaging structure to improve warpage and heat dissipation according to claim 1, characterized in that, The front side of the silicon wafer is connected to the thin chip via a redistribution layer, and the gap between the redistribution layer and the thin chip is filled with a filler material.

3. The method for fabricating a packaging structure to improve warpage and heat dissipation according to claim 1, characterized in that, The chip I is fixed in the groove by an adhesive material, and the chip I is provided in one or multiple stacked.

4. The method for fabricating a packaging structure to improve warpage and heat dissipation according to claim 1, characterized in that, The gap between chip I and the metal and chip II is filled with adhesive to improve warpage and increase heat dissipation.

5. The method for fabricating a packaging structure to improve warpage and heat dissipation according to claim 1, characterized in that, In step one, the dielectric layer is made of silicon oxide or silicon nitride, with a thickness of 0.5 to 2 micrometers.

6. The method for fabricating a packaging structure for improving warpage and heat dissipation according to claim 1, characterized in that, In step five, chip I is fixed into the groove by adhesive material. Chip I is provided as one or more stacked to improve warping in the X and Y directions.

7. The method for fabricating a packaging structure for improving warpage and heat dissipation according to claim 1, characterized in that, In step six, the vias and silicon wafer surface are first passivated by depositing a node layer, then the vias are filled with metal by electroplating, and after the surface metal is removed, a redistribution structure is formed.

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