Semiconductor devices, test systems and methods, computer storage media

Abstract

This disclosure provides a semiconductor device, a testing system and method, and a computer storage medium. The semiconductor device includes: a selection signal generation circuit configured to generate a selection signal; the selection signal includes a first state and a second state; a data interface circuit configured to select a corresponding data signal for operation based on the selection signal; when the selection signal is in the first state, a first sub-data signal is selected; when the selection signal is in the second state, a second sub-data signal is selected; the first sub-data signal and the second sub-data signal together constitute a data signal.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a testing system and method, and a computer storage medium. Background Technology

[0002] Wafer testing is a method for testing the electrical performance of dies on a wafer and screening for defective products, which can reflect the yield of semiconductor manufacturing in a timely manner. Wafers usually need to be tested on high-speed testing equipment, but the number of high-speed interfaces configured on high-speed testing equipment to connect to the wafer is limited, which may result in some dies on the wafer not being tested, affecting testing throughput. Summary of the Invention

[0003] This disclosure provides a semiconductor device, a testing system and method, and a computer storage medium that can improve wafer testing capacity.

[0004] The technical solution disclosed herein is implemented as follows:

[0005] This disclosure provides a semiconductor device, including:

[0006] A selection signal generation circuit is configured to generate a selection signal; the selection signal includes a first state and a second state.

[0007] The data interface circuit is configured to select a corresponding data signal for operation based on the selection signal; when the selection signal is in the first state, a first sub-data signal is selected; when the selection signal is in the second state, a second sub-data signal is selected; the first sub-data signal and the second sub-data signal together constitute a data signal.

[0008] In some embodiments, the selection signal is a data masking signal.

[0009] In some embodiments, the selection signal generation circuit is configured to generate the selection signal based on a test mode signal.

[0010] In some embodiments, the data interface circuit includes: a transmission mode control module, a data latch module, and a data selection module;

[0011] The transmission mode control module is configured to determine the transmission mode as input mode when the transmission signal is in the first transmission state.

[0012] In the input mode, the data latching module is configured to continuously receive the first sub-data signal and the second sub-data signal through the data transmission interface within one cycle of the selection signal, and transmit the first sub-data signal and the second sub-data signal to the data selection module in parallel.

[0013] The data selection module is configured to output the first sub-data signal through a first output terminal when the selection signal is in the first state, and to output the second sub-data signal through a second output terminal when the selection signal is in the second state.

[0014] In some embodiments, the data interface circuit includes: a transmission mode control module, a data latch module, and a data selection module;

[0015] The transmission mode control module is configured to determine that the transmission mode is an output mode when the transmission signal is in the second transmission state.

[0016] In the output mode, the data selection module is configured to receive the first sub-data signal through the first input terminal and the second sub-data signal through the second input terminal; when the selection signal is in the first state, the first sub-data signal is transmitted to the data latch module; when the selection signal is in the second state, the second sub-data signal is transmitted to the data latch module.

[0017] The data latch module is configured to output the first sub-data signal and the second sub-data signal sequentially through the data transmission interface within one cycle of the selection signal.

[0018] This disclosure provides a testing system, including: a semiconductor device and a testing device;

[0019] The semiconductor device includes: a selection signal generation circuit configured to generate a selection signal; the selection signal including a first state and a second state; a data interface circuit configured to select a corresponding data signal for operation according to the selection signal; when the selection signal is in the first state, selecting a first sub-data signal; when the selection signal is in the second state, selecting a second sub-data signal; the first sub-data signal and the second sub-data signal together constitute a data signal;

[0020] The test device is configured to transmit the data signal to the semiconductor device via a data transmission interface, or to receive the data signal from the semiconductor device.

[0021] In some embodiments, the test device is further configured to transmit the first sub-data signal between itself and the semiconductor device via the data transmission interface when the selection signal is in the first state; and to transmit the second sub-data signal between itself and the semiconductor device via the data transmission interface when the selection signal is in the second state.

[0022] In some embodiments, the data interface circuit includes: a transmission mode control module, a data latch module, and a data selection module;

[0023] The transmission mode control module is configured to determine the transmission mode as input mode when the transmission signal is in the first transmission state.

[0024] In the input mode, the data latching module is configured to continuously receive the first sub-data signal and the second sub-data signal through the data transmission interface within one cycle of the selection signal, and transmit the first sub-data signal and the second sub-data signal to the data selection module in parallel.

[0025] The data selection module is configured to output the first sub-data signal through a first output terminal when the selection signal is in the first state, and to output the second sub-data signal through a second output terminal when the selection signal is in the second state.

[0026] In some embodiments, the data interface circuit includes: a transmission mode control module, a data latch module, and a data selection module;

[0027] The transmission mode control module is configured to determine that the transmission mode is an output mode when the transmission signal is in the second transmission state.

[0028] In the output mode, the data selection module is configured to receive the first sub-data signal through a first input terminal, and transmit the first sub-data signal to the data latch module when the selection signal is in the first state; and to receive the second sub-data signal through a second input terminal, and transmit the second sub-data signal to the data latch module when the selection signal is in the second state.

[0029] The data latch module is configured to output the first sub-data signal and the second sub-data signal sequentially through the data transmission interface within one cycle of the selection signal.

[0030] This disclosure provides a testing method, including:

[0031] A selection signal is generated by a selection signal generation circuit; the selection signal includes a first state and a second state; a corresponding data signal is selected for operation according to the selection signal by a data interface circuit; when the selection signal is in the first state, a first sub-data signal is selected; when the selection signal is in the second state, a second sub-data signal is selected; the first sub-data signal and the second sub-data signal together constitute a data signal; the data signal is used for transmission between the test device and the device under test, so that the test device can test the device under test based on the data signal.

[0032] This disclosure provides a computer storage medium storing executable instructions that, when executed by a processor, implement the above-described test method.

[0033] The semiconductor device, test system and method, and computer storage medium provided in this disclosure can select different sub-data signals from the data signal for transmission under different signal states. In this way, two sub-data signals can share a high-speed interface, thereby meeting the test capacity of the device under test with greater data demand. Attached Figure Description

[0034] Figure 1 A schematic diagram of an interface of a test system in a related art provided in this disclosure embodiment;

[0035] Figure 2 A schematic diagram of the structure of an optional semiconductor device provided in an embodiment of this disclosure;

[0036] Figure 3 A schematic diagram of the structure of an optional semiconductor device provided in an embodiment of this disclosure;

[0037] Figure 4 A schematic diagram of an optional testing system provided in an embodiment of this disclosure;

[0038] Figure 5 A schematic diagram of an optional testing system provided in an embodiment of this disclosure;

[0039] Figure 6 A timing diagram illustrating an optional data transmission method provided in an embodiment of this disclosure;

[0040] Figure 7 This is a schematic diagram of a test method flow provided in an embodiment of the present disclosure;

[0041] Figure 8 This is a schematic diagram of the composition of an optional semiconductor device provided in an embodiment of this disclosure. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this disclosure clearer, the disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0043] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0044] In the following description, the terms “first, second, third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first, second, third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0046] To facilitate understanding of this solution, the application background of the embodiments of this disclosure will be explained before describing the embodiments of this disclosure.

[0047] After wafer manufacturing is completed, each die on the wafer needs to undergo electrical testing to screen for good products. At this time, the wafer needs to receive and receive data through the high-speed interface (I / O pin) on the testing equipment (such as Automatic Test Equipment (ATE) or high-speed test platform FPGA) to realize wafer testing. Figure 1 A schematic diagram of an optional high-speed interface configuration for a test device is shown, such as... Figure 1As shown, test equipment typically includes command transfer interfaces (CMD I / O) and data transfer interfaces (DATA I / O), which connect to the chips on the wafer. For example, a wafer may contain 770 chips (Die 1–Die 770), each chip including: 17 command transfer interfaces (CMD[16:0]), 16 data transfer interfaces (DATA[15:0]), one DQS interface, one DQSB interface, and one DM interface, totaling 36 high-speed interfaces; that is, a wafer requires 36 * 770 = 27720 interfaces. If the probe card is configured with only 21560 interfaces, only 598 chips on the wafer can be tested at a time, leaving 172 chips untested, thus affecting the wafer's testing capacity.

[0048] This disclosure provides a semiconductor device, a testing system and method, and a computer storage medium, which can improve the testing capacity of semiconductor devices.

[0049] Figure 2 This is a schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure, see below. Figure 2 The semiconductor device 10 includes a selection signal generation circuit 101 and a data interface circuit 102. The selection signal generation circuit 101 is configured to generate a selection signal; the selection signal includes a first state and a second state; the data interface circuit 102 is configured to select a corresponding data signal for operation based on the selection signal; when the selection signal is in the first state, a first sub-data signal is selected; when the selection signal is in the second state, a second sub-data signal is selected; the first sub-data signal and the second sub-data signal together constitute a data signal.

[0050] In this embodiment of the disclosure, the selection signal includes a first state and a second state; different states are used to instruct the data interface circuit 102 to select a sub-data signal from the data signal; wherein, when the selection signal is in the first state, the data interface circuit 102 selects a first sub-data signal from the data signal; when the selection signal is in the second state, the data interface circuit 102 selects a second sub-data signal from the data signal.

[0051] In this embodiment of the disclosure, the selection signal can be a 1-bit signal, where 1'b0 and 1'b1 represent two states respectively; the selection signal can also be a 2-bit signal, where any one of 2'b00-2'b11 can represent the two states of the selection signal; here, the selection signal and its two states can be set as needed, and this embodiment of the disclosure does not impose any restrictions.

[0052] In this embodiment of the disclosure, the two states of the selection signal can be represented by a high level and a low level. In some embodiments, the first state of the selection signal can be a low level and the second state of the selection signal can be a high level. In some embodiments, the first state of the selection signal can be a high level and the second state of the selection signal can be a low level. This can be set as needed, and this embodiment of the disclosure does not impose any limitations.

[0053] In this embodiment, the semiconductor device 10 and the test device are connected. The semiconductor device 10 can select a sub-data signal through the data interface circuit 102 for transmission with the test device. Here, the sub-data signal selected by the data interface circuit 102 can be a signal read by the test device from the semiconductor device 10, or a signal written by the test device to the semiconductor device 10; this can be set as needed, and this embodiment does not impose any limitations.

[0054] It is understandable that, since the semiconductor device 10 can select different sub-data signals in the data signal for transmission under different states of the selection signal, the two sub-data signals can share a high-speed interface, thereby meeting the testing capacity of semiconductor devices with greater data demand.

[0055] In some embodiments of this disclosure, the selection signal may be a data mask (DM) signal.

[0056] In this embodiment, the DM signal can function as a selection signal in the selection function mode; when the selection function mode is off, it functions as a data shielding signal, shielding part of the data and transmitting only the other part. The state of the DM signal can be represented by its high or low level, thus eliminating the need for an additional selection signal interface and reducing the interface requirements of semiconductor devices.

[0057] In some embodiments of this disclosure, a first state of the selection signal represents a low-level state of the DM signal; a second state of the selection signal represents a high-level state of the DM signal.

[0058] In some embodiments of this disclosure, a first state of the selection signal represents a high-level state of the DM signal; a second state of the selection signal represents a low-level state of the DM signal.

[0059] It is understandable that within one cycle of the DM signal, the data interface circuit 102 can select the first sub-data signal and the second sub-data signal from the data signal respectively to realize time-division multiplexing of the high-speed interface.

[0060] In some embodiments of this disclosure, the selection signal generation circuit 101 is configured to generate a selection signal based on a test mode signal.

[0061] In this embodiment of the disclosure, the selection signal generation circuit 101 can receive a test mode signal and generate a selection signal based on the test mode signal.

[0062] In some embodiments of this disclosure, the selection signal generation circuit 101 can generate a selection signal when the test mode signal is valid. A valid test mode signal indicates that the semiconductor device 10 has entered test mode, during which the semiconductor device can be tested, thereby reducing the resource consumption of the selection signal generation circuit 101.

[0063] In some embodiments of this disclosure, the selection signal generation circuit 101 can use the DM signal as a selection signal when the test mode signal is valid. When the test mode signal is valid, the semiconductor device 10 enters the test mode. In the test mode, the DM signal is not used as a data mask signal, but as a selection signal for data output.

[0064] based on Figure 2 , Figure 3 A schematic diagram of an optional semiconductor device is shown, such as... Figure 3 As shown, the data interface circuit 102 includes a transmission mode control module 1021, a data latch module 1022, and a data selection module 1023. The transmission mode control module 1021 is configured to determine the transmission mode as input mode when the transmission signal is in a first transmission state. In input mode, the data latch module 1022 is configured to continuously receive a first sub-data signal and a second sub-data signal through the data transmission interface D1 within one cycle of the selection signal, and transmit the first sub-data signal and the second sub-data signal in parallel to the data selection module 1023. The data selection module 1023 is configured to output the first sub-data signal through the first output terminal D21 when the selection signal is in the first state, and output the second sub-data signal through the second output terminal D22 when the selection signal is in the second state.

[0065] In this embodiment, the transmission mode control module 1021 can determine the transmission mode of the semiconductor device based on the transmission signal. The transmission mode includes an input mode and an output mode. When the transmission signal is in the first transmission state, the transmission mode control module 1021 can determine that the transmission mode of the semiconductor device is the input mode. In this case, the semiconductor device receives two sub-data signals in a time-division multiplexing manner through the data transmission interface D1 of the data latch module 1022, and outputs the two sub-data signals respectively through the two output terminals of the data selection module 1023.

[0066] In this embodiment, the data latch module 1022 can continuously receive the first sub-data signal and the second sub-data signal within one cycle of the selection signal. That is, within one cycle of the selection signal, the first sub-data signal and the second sub-data signal are received sequentially through the data transmission interface D1. Then, the first sub-data signal and the second sub-data signal are transmitted in parallel to the data selection module 1023; thus, the data selection module 1023 can select one sub-data signal from the first sub-data signal and the second sub-data signal according to the state of the selection signal and output it from the corresponding output terminal.

[0067] It is understandable that semiconductor devices can select the transmission mode according to the transmission signal. When the transmission signal is in the first transmission state, two sub-data signals can be received in a time-division manner through the data transmission interface D1 of the data latch module, and then the two sub-data signals can be output through the two output terminals D21 and D22 of the data selection module respectively. In this way, two sub-data signals from one data transmission interface can be output from the two output terminals D21 and D22 respectively, thereby improving the effectiveness of testing semiconductor devices through data signals.

[0068] In some embodiments of this disclosure, the data interface circuit 102 includes a transmission mode control module 1021, a data latch module 1022, and a data selection module 1023. The transmission mode control module 1021 is configured to determine the transmission mode as an output mode when the transmission signal is in a second transmission state. In the output mode, the data selection module 1023 is configured to receive a first sub-data signal through a first input terminal D211, and transmit the first sub-data signal to the data latch module 1022 when the selection signal is in a first state; and to receive a second sub-data signal through a second input terminal D221, and transmit the second sub-data signal to the data latch module 1022 when the selection signal is in a second state. The data latch module 1022 is configured to output the first sub-data signal and the second sub-data signal sequentially through the data transmission interface D1 within one cycle of the selection signal.

[0069] In this embodiment of the disclosure, the transmission mode control module 1021 can determine that the transmission mode of the semiconductor device 10 is the output mode when the transmission signal is in the second transmission state. At this time, the semiconductor device 10 can receive the first sub-data signal through the first input terminal D211 and the second sub-data signal through the second input terminal D221 within one cycle of the selection signal, and output the first sub-data signal and the second sub-data signal through the data transmission interface D1.

[0070] In this embodiment, the data selection module 1023 can receive a first sub-data signal through the first input terminal D211 and a second sub-data signal through the second input terminal D221. When the selection signal is in a first state, the first sub-data signal is sent to the data latch module 1022, which then outputs the first sub-data signal through the data transmission interface D1. When the selection signal is in a second state, the data selection module 1023 can send the second sub-data signal to the data latch module 1022, which then outputs the second sub-data signal through the data transmission interface D1. Thus, the data latch module 1022 can output the first sub-data signal through the data transmission interface in the first state of the selection signal and output the second sub-data signal through the data transmission interface in the second state of the selection signal, achieving sequential output of the first and second sub-data signals through a single interface within one cycle of the selection signal.

[0071] In some embodiments of this application, the first output terminal D21 can be the first input terminal D211, and the first output terminal D22 can be the first input terminal D221.

[0072] Understandably, semiconductor devices can select a transmission mode based on the transmission signal. When the transmission signal is in the second transmission state, two sub-data signals can be received through the two input terminals of the data selection module 1023, and then the two sub-data signals can be output in a time-division manner through the data transmission interface D1 of the data latch module 1022. In this way, two sub-data signals originating from two different interfaces can be output from a single data transmission interface, thereby reducing the number of data transmission interfaces required for the test device to receive these two sub-data signals.

[0073] Based on the semiconductor devices provided in the above embodiments, this disclosure provides a testing system, such as... Figure 4 As shown, the test system includes a semiconductor device 10 and a test device 20. The semiconductor device 10 includes a selection signal generation circuit 101 and a data interface circuit 102. The selection signal generation circuit 101 is configured to generate a selection signal; the selection signal includes a first state and a second state. The data interface circuit 102 is configured to select a corresponding data signal based on the selection signal; when the selection signal is in the first state, a first sub-data signal is selected; when the selection signal is in the second state, a second sub-data signal is selected; the first and second sub-data signals together constitute a data signal. The test device 20 is configured to transmit the data signal to the semiconductor device 10 via a data transmission interface, or to receive the data signal from the semiconductor device 10.

[0074] In this embodiment, the description of the semiconductor device 10 is detailed in the above embodiments and will not be repeated here. The test device 20 is used to test the electrical performance of the semiconductor device. The test device 20 can write data signals to the semiconductor device 10 and read data signals from the semiconductor device 10.

[0075] In this embodiment of the disclosure, the test device 20 can serially output the first sub-data signal and the second sub-data signal within one cycle of the selection signal, and the semiconductor device 10 can acquire the first sub-data signal and the second sub-data signal in parallel within one cycle of the selection signal.

[0076] It is understandable that, since the semiconductor device 10 can select different sub-data signals in the data signal under different states of the selection signal and transmit them with the test device 20 through the data transmission interface, the data signal can be transmitted serially during the test device 20's testing of the semiconductor device 10, thereby reducing the number of data transmission interfaces required by the semiconductor device 10 for the test device 20, and thus improving the testing capacity of the semiconductor device 10.

[0077] In some embodiments of this disclosure, the test device 20 is further configured to transmit a first sub-data signal between itself and the semiconductor device 10 via a data transmission interface when the selection signal is in a first state; and to transmit a second sub-data signal between itself and the semiconductor device 10 via a data transmission interface when the selection signal is in a second state.

[0078] In this embodiment of the disclosure, the selection signal includes a first state and a second state within one cycle. The test device 20 can transmit different sub-data signals with the semiconductor device 10 through the data transmission interface under different states of the selection signal, thereby realizing serial transmission of data signals with the semiconductor device 10 within one cycle.

[0079] It is understandable that the test device 20 can transmit data signals with the semiconductor device 10 in a time-division manner, thereby receiving two sub-data signals through one data transmission interface. Compared with receiving sub-data signals through two separate data transmission interfaces, this reduces the number of data transmission interfaces and improves the testing flexibility of the test device 20 for semiconductor devices 10 with different data signal requirements.

[0080] In some embodiments of this disclosure, the selection signal is a data shielding (DM) signal.

[0081] In some embodiments of this disclosure, the selection signal generation circuit is configured to generate the selection signal based on a test mode signal.

[0082] In some embodiments of this disclosure, the first state indicates that the data shielding signal is in a low-level state; the second state indicates that the data shielding signal is in a high-level state.

[0083] In some embodiments of this disclosure, the data interface circuit includes: a transmission mode control module, a data latch module, and a data selection module; the transmission mode control module is configured to determine the transmission mode as an input mode when the transmission signal is in a first transmission state; in the input mode, the data latch module is configured to continuously receive the first sub-data signal and the second sub-data signal through the data transmission interface within one cycle of the selection signal, and transmit the first sub-data signal and the second sub-data signal in parallel to the data selection module; the data selection module is configured to output the first sub-data signal through a first output terminal when the selection signal is in the first state, and output the second sub-data signal through a second output terminal when the selection signal is in the second state.

[0084] In this embodiment, the test device 20 can divide the data signal into a first sub-data signal and a second sub-data signal, and transmit the first sub-data signal and the second sub-data signal to the data transmission interface in a time-division multiplexing manner within one cycle. Here, the division method of the first sub-data signal and the second sub-data signal can be set as needed, and this embodiment does not impose any limitations.

[0085] For example, the data signal includes eight signals, DQ0-DQ7. The test device 20 can use DQ0-DQ3 as the first sub-data signal and DQ4-DQ7 as the second sub-data signal; the test device 20 can also use DQ0, DQ2, DQ4 and DQ6 as the first sub-data signal and DQ1, DQ3, DQ5 and DQ7 as the second sub-data signal.

[0086] In some embodiments of this disclosure, the data interface circuit includes: a transmission mode control module, a data latch module, and a data selection module; the transmission mode control module is configured to determine the transmission mode as an output mode when the transmission signal is in a second transmission state; in the output mode, the data selection module is configured to receive a first sub-data signal through a first input terminal and a second sub-data signal through a second input terminal; when the selection signal is in the first state, the first sub-data signal is transmitted to the data latch module; when the selection signal is in the second state, the second sub-data signal is transmitted to the data latch module; the data latch module is configured to sequentially output the first sub-data signal and the second sub-data signal through the data transmission interface within one cycle of the selection signal.

[0087] based on Figure 4 , Figure 5 A schematic diagram of an optional testing system is shown, such as... Figure 5 As shown, the test device 20 is implemented as a test probe card, the data latch module 1022 is implemented as a serial-to-parallel conversion module, and the selection signal is implemented as a DM signal; the semiconductor device 10 includes: a selection signal generation circuit 101, a transmission mode control module 1021, a serial-to-parallel conversion module 1022, a data selection module 1023, and a gating circuit (Data MUX buffer) 1024. The semiconductor device is a chip on a wafer.

[0088] In this embodiment of the disclosure, for any chip, the test probe card can output 16 data points (DQ0-DQ15) through 8 interfaces (Pin1-Pin8). These 16 data points can be divided into 8 groups, where the first sub-data includes 8 data points where X is an even number in DQX (Even 8DQ), and the second sub-data includes 8 data points where X is an odd number in DQX (Odd8DQ). Interface Pin1 transmits the first group of sub-data: DQ0 and DQ1, interface Pin2 transmits the second group of sub-data: DQ2 and DQ3, and so on, with interface Pin8 transmitting the eighth group of sub-data: DQ14 and DQ15. The series-parallel conversion module may include series-parallel conversion circuits 1-8, the transmission mode control module 1021 may include sub-control modules 1-8, and the data latch module 1023 may include sub-latch modules (ctrl buffer) 1-8. Thus, for any set of sub-data, the semiconductor device 10 can control its transmission mode through a corresponding sub-control module, perform series-parallel conversion through a corresponding series-parallel conversion circuit, and select a sub-data through a corresponding sub-latch module, thereby transmitting these 8 sets of sub-data between the selection circuit 1024 and the gating circuit 1024, and transmitting these 16 data between the internal circuit and the gating circuit 1024.

[0089] In this embodiment, the sampling clock signal includes a set of opposite signals: DQS and DQSB. Data sampling is triggered on the rising edge of DQS, which is also the falling edge of DQSB, for data transmission. Half a cycle of the DM signal equals one cycle of the sampling clock signal. When the DM signal is low (L), Even 8DQ is transmitted; when the DM signal is high (H), Odd 8DQ is transmitted. Figure 6 As shown.

[0090] Table 1 shows a comparison of the high-speed interfaces required for a chip in this disclosure and related technologies. It can be seen that the 16 data transmission interfaces in the related technologies can be implemented using the 8 data transmission interfaces in the embodiments of this disclosure, with the selection signal implemented through the DM signal. For Figure 1 The 770 chips in the wafer shown are tested using the test system disclosed herein, requiring 21,560 interfaces. Thus, the total number of interfaces configured on the test probe card can meet the testing requirements of the wafer.

[0091] Understandably, test probe cards can perform chip testing by time-division multiplexing the interfaces on the chip, even when there are fewer interfaces than the chip requires, thereby greatly improving the chip testing capacity.

[0092]

[0093] Based on the above testing system, this disclosure provides an optional testing method, such as... Figure 7 As shown, the method may include: S101-S102.

[0094] S101. A selection signal is generated by the selection signal generation circuit; the selection signal includes a first state and a second state.

[0095] S102. Through the data interface circuit, the corresponding data signal is selected for operation according to the selection signal; when the selection signal is in the first state, the first sub-data signal is selected; when the selection signal is in the second state, the second sub-data signal is selected; the first sub-data signal and the second sub-data signal together constitute the data signal; the data signal is used to transmit between the test device and the device under test, so that the test device can test the device under test based on the data signal.

[0096] In the embodiments disclosed herein, the descriptions of S101-S102 can be found in the above description and will not be repeated here.

[0097] In some embodiments of this disclosure, the selection signal is a data shielding (DM) signal.

[0098] In some embodiments of this disclosure, the method further includes: generating the selection signal based on the test mode signal through the selection signal generation circuit.

[0099] In some embodiments of this disclosure, the first state indicates that the data shielding signal is in a low-level state; the second state indicates that the data shielding signal is in a high-level state.

[0100] In some embodiments of this disclosure, the method further includes: determining the transmission mode as an input mode by a transmission mode control module when the transmission signal is in a first transmission state; in the input mode, continuously receiving the first sub-data signal and the second sub-data signal through a data transmission interface within one cycle of the selection signal by a data latch module, and transmitting the first sub-data signal and the second sub-data signal in parallel to the data selection module; outputting the first sub-data signal through a first output terminal by the data selection module when the selection signal is in the first state; and outputting the second sub-data signal through a second output terminal when the selection signal is in the second state.

[0101] In some embodiments of this disclosure, the method further includes: determining the transmission mode as an output mode by a transmission mode control module when the transmission signal is in a second transmission state; in the output mode, receiving the first sub-data signal through a first input terminal by a data selection module, and transmitting the first sub-data signal to the data latch module when the selection signal is in the first state; receiving the second sub-data signal through a second input terminal, and transmitting the second sub-data signal to the data latch module when the selection signal is in the second state; and sequentially outputting the first sub-data signal and the second sub-data signal through the data transmission interface by the data latch module within one cycle of the selection signal.

[0102] Figure 8 This is a schematic diagram illustrating the composition of an optional semiconductor device provided in an embodiment of this disclosure, such as... Figure 8 As shown, the semiconductor device 110 includes a memory 1107, a processor 1108, and a computer program stored in the memory 1107 and executable on the processor 1108; wherein, when the processor 1108 runs the computer program, it performs the test method as described in the foregoing embodiments.

[0103] It is understood that the semiconductor device 110 also includes a bus system 1109; the various components in the semiconductor device 110 are coupled together through the bus system 1109. It is understood that the bus system 1109 is used to realize the connection and communication between these components. In addition to a data bus, the bus system 1109 also includes a power bus, a control bus, and a status signal bus.

[0104] It is understood that the memory in the embodiments of this disclosure can be volatile memory or non-volatile memory, or both. Specifically, non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); magnetic surface memory can be disk storage or magnetic tape storage. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).The memories described in the embodiments of this disclosure are intended to include, but are not limited to, these and any other suitable types of memories.

[0105] The methods disclosed in the embodiments of this disclosure can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor may be a general-purpose processor, a DSP, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory. The processor reads information from the memory and, in conjunction with its hardware, completes the steps of the aforementioned method.

[0106] This disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the above-described test method.

[0107] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple modules or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or modules can be electrical, mechanical, or other forms.

[0108] The above description is merely an embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this disclosure are included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A selection signal generation circuit is configured to generate a selection signal; the selection signal includes a first state and a second state. The data interface circuit is configured to select a corresponding data signal for operation based on the selection signal; when the selection signal is in the first state, to select a first sub-data signal; and when the selection signal is in the second state, to select a second sub-data signal. The first sub-data signal and the second sub-data signal together constitute a data signal; The data interface circuit includes: a transmission mode control module, a data latch module, and a data selection module; The transmission mode control module is configured to determine the transmission mode as input mode when the transmission signal is in the first transmission state. In the input mode, the data latching module is configured to continuously receive the first sub-data signal and the second sub-data signal through the data transmission interface within one cycle of the selection signal, and transmit the first sub-data signal and the second sub-data signal to the data selection module in parallel. The data selection module is configured to output the first sub-data signal through a first output terminal when the selection signal is in the first state, and to output the second sub-data signal through a second output terminal when the selection signal is in the second state. The selection signal is a data masking signal; The selection signal generation circuit is configured to generate the selection signal based on the test mode signal.

2. The semiconductor device according to claim 1, characterized in that, The transmission mode control module is configured to determine the transmission mode as output mode when the transmission signal is in the second transmission state. In the output mode, the data selection module is configured to receive the first sub-data signal through the first input terminal and the second sub-data signal through the second input terminal; when the selection signal is in the first state, the first sub-data signal is transmitted to the data latch module; when the selection signal is in the second state, the second sub-data signal is transmitted to the data latch module. The data latch module is configured to output the first sub-data signal and the second sub-data signal sequentially through the data transmission interface within one cycle of the selection signal.

3. A testing system, characterized in that, include: Semiconductor devices and testing devices; The semiconductor device includes: A selection signal generation circuit is configured to generate a selection signal; the selection signal includes a first state and a second state. The data interface circuit is configured to select a corresponding data signal for operation based on the selection signal; when the selection signal is in the first state, a first sub-data signal is selected; when the selection signal is in the second state, a second sub-data signal is selected; the first sub-data signal and the second sub-data signal together constitute a data signal. The test device is configured to transmit the data signal to the semiconductor device via a data transmission interface, or to receive the data signal from the semiconductor device; the test device is further configured to transmit a first sub-data signal between itself and the semiconductor device via the data transmission interface when the selection signal is in the first state; and to transmit a second sub-data signal between itself and the semiconductor device via the data transmission interface when the selection signal is in the second state. The data interface circuit includes: a transmission mode control module, a data latch module, and a data selection module; The transmission mode control module is configured to determine the transmission mode as input mode when the transmission signal is in the first transmission state. In the input mode, the data latching module is configured to continuously receive the first sub-data signal and the second sub-data signal through the data transmission interface within one cycle of the selection signal, and transmit the first sub-data signal and the second sub-data signal to the data selection module in parallel. The data selection module is configured to output the first sub-data signal through a first output terminal when the selection signal is in the first state, and to output the second sub-data signal through a second output terminal when the selection signal is in the second state. The selection signal is a data masking signal; The selection signal generation circuit is configured to generate the selection signal based on the test mode signal.

4. The testing system according to claim 3, characterized in that, The data interface circuit includes: a transmission mode control module, a data latch module, and a data selection module; The transmission mode control module is configured to determine the transmission mode as input mode when the transmission signal is in the first transmission state. In the input mode, the data latching module is configured to continuously receive the first sub-data signal and the second sub-data signal through the data transmission interface within one cycle of the selection signal, and transmit the first sub-data signal and the second sub-data signal to the data selection module in parallel. The data selection module is configured to output the first sub-data signal through a first output terminal when the selection signal is in the first state, and to output the second sub-data signal through a second output terminal when the selection signal is in the second state.

5. The testing system according to claim 3, characterized in that, The data interface circuit includes: a transmission mode control module, a data latch module, and a data selection module; The transmission mode control module is configured to determine the transmission mode as output mode when the transmission signal is in the second transmission state. In the output mode, the data selection module is configured to receive the first sub-data signal through the first input terminal and the second sub-data signal through the second input terminal; when the selection signal is in the first state, the first sub-data signal is transmitted to the data latch module; when the selection signal is in the second state, the second sub-data signal is transmitted to the data latch module. The data latch module is configured to output the first sub-data signal and the second sub-data signal sequentially through the data transmission interface within one cycle of the selection signal.

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