An online upgrade architecture and method for inverter programs

Abstract

This application discloses an online inverter program upgrade architecture and method. The architecture includes a controller, an encoding and identification module, and a latching unit. The controller is adapted to control a relay group via control signals. The output side of the controller is communicatively connected to the encoding and identification module, which is adapted to convert the control signals issued by the controller into logic level signals. The latching unit outputs a level signal based on the received logic level signal, or latches the high-level signal of the controller before the upgrade. The method utilizes the above architecture for online inverter program upgrade control. The advantages of this application are: uninterrupted load power supply during the program upgrade process is achieved through a single controller, resulting in lower cost and higher power density; and no additional IO interface is required, minimizing resource consumption on the controller. It can also be applied to scenarios with multiple controllers, enabling uninterrupted load power supply when multiple controllers are simultaneously undergoing program upgrades.

Description

Technical Field

[0001] This application relates to the field of new energy power generation technology, and in particular to an online upgrade architecture and method for inverter programs. Background Technology

[0002] The existing software upgrade scheme for photovoltaic-storage inverters is shown in Figure 1. An MCU controller 420 (or DSP) controls each converter (including DC / DC unit 120, bidirectional DC / DC unit 140, DC / AC unit 150, and relay group 160, etc.). During the upgrade process, the host computer 410 typically sends an upgrade command to the MCU controller 420. However, during the program upgrade, due to the reset of the MCU controller 420, the relay control signal relay_ctrl is pulled low, causing the relay to disconnect and resulting in a power outage for the load 300.

[0003] To maintain uninterrupted power supply to the load during program upgrades, there are two existing solutions: one is to add a bypass relay between the power grid and the load, and add a control bit for the bypass relay in the boot program, thereby significantly reducing power interruption time; the other is to use multiple MCUs to redundantly control the relay, so that when one MCU is being upgraded, another MCU maintains the relay control.

[0004] However, existing solutions have the following drawbacks: For the bypass relay solution mentioned above, the need for additional relays increases costs and reduces power density. Furthermore, power supply interruptions may still occur between MCU reset and program startup. For solutions using multiple MCUs for redundant relay control, the cost is higher than a single MCU solution; and for machines with multiple MCUs, relay disconnection can still occur in scenarios where multiple MCUs need simultaneous program upgrades, failing to maintain continuous power supply to the load. Summary of the Invention

[0005] One objective of this application is to provide an architecture for implementing an online inverter program upgrade method that can address at least one of the deficiencies in the aforementioned background technology.

[0006] To achieve the aforementioned objective, the technical solution adopted in this application is as follows: an online upgrade architecture for an inverter program, comprising a host computer, a controller, an encoding and identification module, and a latching unit; the host computer is adapted to issue upgrade commands, the controller is communicatively connected to the host computer, and the controller is adapted to control the relay group through a control signal, which is an encoded signal; the output side of the controller is communicatively connected to the encoding and identification module, and the encoding and identification module is adapted to convert the control signal issued by the controller into a corresponding logic level signal; the latching unit is communicatively connected to the output end of the encoding and identification module, and the latching unit is adapted to output a level signal to the control signal issued by the controller according to the received logic level signal, or to latch the high-level signal of the controller before the upgrade, thereby continuing to enable the relay group to close.

[0007] Preferably, the encoding and recognition module includes two output terminals, and the latch unit adopts a D latch; the inverter program online upgrade architecture also includes a latch data generation unit and a clock signal generation unit; the output terminals of the latch data generation unit and the clock signal generation unit are respectively connected to the D port and EN port of the latch unit; one output terminal of the encoding and recognition module and the control signal output by the controller are both connected to the input terminal of the latch data generation unit; the other output terminal of the encoding and recognition module is connected to the input terminal of the clock signal generation unit.

[0008] Preferably, the encoding and recognition module includes a duty cycle conversion unit, a voltage range recognition unit, and an output signal generation unit that are connected in sequence; the duty cycle conversion unit is adapted to convert the duty cycle information of the control signal issued by the controller into voltage information; the voltage range recognition unit is adapted to compare the voltage information with a set threshold; and the output signal generation unit is adapted to output a corresponding level signal based on the comparison result.

[0009] Preferably, the two output terminals of the output signal generation unit send level signals EN1 and EN2 to the latch data generation unit and the clock signal generation unit, respectively; the voltage range identification unit includes two comparators, one input terminal of each comparator receives voltage information v sent by the duty cycle conversion unit, and the other input terminal of each comparator receives a set threshold v. th1 and v th2 , and v th1 <v th2 If the controller sends a high-level signal to control the relay group during normal operation; when v > v th2 When v < v, both level signals EN1 and EN2 are 0; when v < v th1When v is at that time, the level signal EN1 is 0 and the level signal EN2 is 1; when v th1 <v<v th2 When v > v, both level signals EN1 and EN2 are 1; if the controller is operating normally, it sends a low duty cycle signal to control the relay group; when v > v th2 When v < v, the level signal EN1 is 1 and the level signal EN2 is 0; th1 When v is at that time, both level signals EN1 and EN2 are 0; when v th1 <v<v th2 At that time, the level signal EN1 is 0 and the level signal EN2 is 1.

[0010] Preferably, if the controller sends a high-level signal to control the relay group during normal operation; the corresponding threshold v th2 The output of the comparator is directly used as the output level signal EN2 of the output signal generation unit; the output signal generation unit further includes a second AND gate unit, the two input terminals of the second AND gate unit are respectively communicatively connected to the output terminals of the two comparators, and the output level signal EN1 of the second AND gate unit.

[0011] Preferably, if the controller sends a low duty cycle signal to control the relay group during normal operation; the corresponding threshold v th2 The output of the comparator is directly used as the output level signal EN1 of the output signal generation unit; the output signal generation unit also includes a NOT gate unit and a second AND gate unit, the input terminal of the NOT gate unit is communicatively connected to the level signal EN1, the output terminal of the NOT gate unit and the output terminal of another comparator are connected to the input terminal of the second AND gate unit, and the AND gate unit outputs the level signal EN2.

[0012] Preferably, if the controller sends a high-level signal to control the relay group during normal operation, the clock signal generation unit includes an inverter and a delay unit connected in sequence; the inverter is adapted to receive the level signal EN2 and send it to the delay unit after flipping the level state; the delay unit is adapted to send the flipped level signal to the EN port of the latch unit after delaying it for a set time; if the controller sends a low duty cycle signal to control the relay group during normal operation, the clock signal generation unit includes a delay unit, which is adapted to receive the level signal EN2 and send it to the EN port of the latch unit after delaying it for a set time.

[0013] Preferably, the online upgrade architecture for the inverter program further includes a software protection unit, which employs a third AND gate unit; the input of the third AND gate unit is communicatively connected to the controller, and the output of the third AND gate unit is communicatively connected to the input of the encoding and identification module; the controller sends control signals and software protection signals to the input of the third AND gate unit respectively.

[0014] Preferably, there are multiple controllers, one of which participates in the control of the relay group, while the other controllers do not participate in the control of the relay group; the controller participating in the control of the relay group is communicatively connected to the encoding and identification module, and the other controllers are communicatively connected to the controller connected to the encoding and identification module or the host computer.

[0015] Preferably, there are multiple controllers, encoding and recognition modules, and latching units. Each controller is connected to a corresponding encoding and recognition module and a latching unit to form a control branch. The controllers, which serve as input terminals of each control branch, are interconnected or are all interconnected with the host computer. The latching units, which serve as output terminals of each control branch, simultaneously output level control signals to control the relay group.

[0016] An online inverter program upgrade method utilizing the aforementioned online inverter program upgrade architecture includes the following steps: a host computer sends a program upgrade preparation command to the controller; upon receiving the command, the controller controls the current operating mode of the inverter, enabling the inverter to operate in grid-connected mode and execute a relay sustaining control mode; after the inverter completes the switch to the relay sustaining mode, the controller sends feedback to the host computer that the program upgrade preparation is complete; upon receiving the preparation completion information, the host computer sends an upgrade package to the controller and performs the upgrade; after the controller completes the upgrade, it outputs a corresponding control signal to control the relay group to operate normally; wherein, the controller executes the relay sustaining mode using different encoding and waveform transmission methods before and after receiving the upgrade command.

[0017] Preferably, the inverter's operating mode control includes the following process: determining the inverter's current operating mode; if the inverter is in grid-connected mode, the inverter directly executes the relay maintenance control mode; if the inverter is in off-grid mode, further determining whether the inverter meets the grid-connected requirements; for inverters that meet the grid-connected requirements, switching to grid-connected mode and then executing the relay maintenance control mode; for inverters that do not meet the grid-connected requirements, maintaining the off-grid mode; wherein, in the relay maintenance control mode, the relay maintains the state of the previous moment, and the controller's control command at the next moment no longer affects the opening and closing of the relay.

[0018] Compared with the prior art, the beneficial effects of this application are as follows:

[0019] This application enables uninterrupted power supply to the load during program upgrades using a single controller, resulting in lower cost and higher power density. Furthermore, it eliminates the need for additional I / O interfaces, minimizing resource consumption on the controller. Moreover, this application can be applied to scenarios with multiple controllers, ensuring uninterrupted power supply to the load when multiple controllers are simultaneously upgrading programs, with high power supply reliability. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the existing online upgrade architecture for inverter programs.

[0021] Figure 2 This is a schematic diagram illustrating a specific example of the online upgrade architecture for inverter programs in a single-controller scenario described in this application.

[0022] Figure 3 This is the truth table when the latch unit in this application uses a D latch.

[0023] Figure 4 For this application Figure 2 The diagram shows the structure of the encoding and identification module in the online upgrade architecture of the inverter program.

[0024] Figure 5 For this application Figure 4 The diagram shows the recognition module's duty cycle changing from 100% to 50%.

[0025] Figure 6 For this application Figure 4 The diagram shows the recognition module's duty cycle changing from 100% to 0%.

[0026] Figure 7 This is a schematic diagram of a specific example two of the online upgrade architecture for inverter programs in a single-controller scenario in this application.

[0027] Figure 8 For this application Figure 7 The diagram shows the structure of the encoding and identification module in the online upgrade architecture of the inverter program.

[0028] Figure 9 For this application Figure 8 The diagram shows the recognition module's duty cycle changing from 50% to 100%.

[0029] Figure 10 This is a schematic diagram of the online upgrade architecture for the inverter program with software protection function in this application.

[0030] Figure 11 This is a schematic diagram of an example of the online upgrade architecture for inverter programs in multi-controller scenarios in this application.

[0031] Figure 12 This is a schematic diagram of Example 2 of the online upgrade architecture for inverter programs in multi-controller scenarios in this application.

[0032] Figure 13 This is a schematic diagram of Example 3 of the online upgrade architecture for inverter programs in multi-controller scenarios in this application.

[0033] Figure 14 This is a schematic diagram of the overall workflow of the online inverter program upgrade method in this application.

[0034] Figure 15 This is a timing diagram of the inverter in this application during program upgrade.

[0035] Figure 16 This is a timing diagram of the controller performing a power-on reset in this application.

[0036] Figure 17 This is a timing diagram of relay switching during normal operation of the inverter in this application.

[0037] In the diagram: PV unit 110, DC / DC unit 120, energy storage unit 130, bidirectional DC / DC unit 140, DC / AC unit 150, relay group 160, power grid 200, load 300, host computer 410, controller 420, software protection unit 421, reset pull-down device 430, protection unit 440, first AND gate unit 450, encoding recognition module 460, duty cycle conversion unit 461, voltage range recognition unit 462, output signal generation unit 463, latch unit 470, latched data generation unit 480, clock signal generation unit 490. Detailed Implementation

[0038] The present application will be further described below with reference to specific embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0039] In the description of this application, it should be noted that the terms "center", "lateral", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., which indicate the orientation and positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and should not be construed as limiting the specific protection scope of this application.

[0040] It should be noted that the terms "first," "second," etc., in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0041] The terms “comprising” and “having”, and any variations thereof, in the specification and claims of this application are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0042] To facilitate understanding of the following solutions, a simple description of the structure of a traditional inverter system can be provided first. An inverter system may include a power generation system, an energy storage system, and a UPS system, etc.; that is, the technical solution of this application can implement a pre-generation system, an energy storage system, and a UPS system, etc.

[0043] For ease of understanding, this application will be described using a photovoltaic energy storage system as an example. Figure 1 As shown, a traditional photovoltaic energy storage system mainly includes a PV unit 110, an energy storage unit 130, a DC / DC unit 120, a bidirectional DC / DC unit 140, and a DC / AC unit 150. The PV unit 110 and the energy storage unit 130 are connected in parallel to the input bus of the DC / AC unit 150 after being connected to the corresponding DC / DC unit 120 and bidirectional DC / DC unit 140, respectively. The output of the DC / AC unit 150 is connected to the power grid 200 through a control switch, and the load 300 is also connected in parallel to the output of the DC / AC unit 150 through a control switch.

[0044] In this field, relays are commonly used control switches. The relays installed on the positive and negative buses between the grid 200 and the DC / AC unit 150, and the relays installed on the positive and negative buses between the load 300 and the DC / AC unit 150, can respectively form corresponding relay groups 160. When the inverter system is connected to the grid, the inverter system can supply power to the load 300 by closing the relay group 160; when the inverter system is disconnected from the grid, if the load 300 wants to continue operating, it can continue to supply power from the grid 200 to the load 300 by closing the relay group 160.

[0045] One aspect of this application provides an online inverter program upgrade architecture, such as... Figure 2 and Figure 7As shown, one preferred embodiment includes a host computer 410, a controller 420, an encoding and recognition module 460, and a latching unit 470. The host computer 410 and the controller 420 are communicatively connected, and the host computer 410 can send program upgrade commands to the controller 420. The controller 420 can output coded control signals to the relay group 160 for control. The controller 420 is communicatively connected to the input side of the encoding and recognition module 460, and the output end of the encoding and recognition module 460 is communicatively connected to the input side of the latching unit 470. Thus, the control signals output by the controller 420 can be encoded by the encoding and recognition module 460 and converted into logic level signals, which are then output through the latching unit 470.

[0046] When the controller 420 is operating normally, it can send a constant level control signal to the encoding and identification module 460. At this time, the encoding and identification module 460 can output a corresponding logic level signal according to the control signal sent by the controller 420 and send it to the latch unit 470. Then, the latch unit 470 also outputs a corresponding level signal to the relay group 160 according to the received logic level signal, thereby controlling the relay group 160 to enter the closed enable state to ensure that the inverter system can operate normally in grid connection.

[0047] When the controller 420 needs to be upgraded, it can send an coded control signal to the encoding and recognition module 460. The encoding and recognition module 460 then converts the control signal from the controller 420 into a corresponding logic level signal and sends it to the latch unit 470. The latch unit 470 can latch the logic level signal of the controller 420 before the upgrade based on the received logic level signal. Therefore, during the upgrade process, the latch unit 470 can continue to send corresponding enable signals to the relay group 160, keeping the relay group 160 closed to ensure that the load 300 can continue to operate normally through the power supply from the power grid 200. Compared to traditional methods, this application can achieve uninterrupted power supply to the load 300 during the program upgrade process using a single controller 420, with lower cost and higher power density. Furthermore, it does not require additional I / O interfaces for the controller 420, thus minimizing resource consumption on the controller 420.

[0048] It should be understood that the controller 420 commonly uses an MCU controller in this field. Its specific structure and working principle are well-known to those skilled in the art and will not be described in detail here. Common MCU controllers include DSPs. The upgrade instructions for the controller 420 can be implemented through the host computer 410, i.e., the host computer 410 communicates with the controller 420 via signal lines. Common signal lines include boot, reset, and communication buses such as SCI. When the controller 420 is operating normally, the host computer 410 can send corresponding level signals to the controller 420 via the boot and reset signal lines, enabling the controller 420 to output the corresponding relay control signal relay_ctrl to the encoding and recognition module 460. The relay control signal relay_ctrl is an encoded signal. It is a constant level signal when the controller 420 is operating normally, and a pulse signal with a constant duty cycle during the upgrade process. Common relay control signals relay_ctrl include various types, such as PWM signals. The specific structure and working principle of the host computer 410 are also well-known to those skilled in the art; common host computers 410 include ARM processors.

[0049] In this embodiment, to ensure the security of the online architecture for inverter program upgrades, such as... Figure 2 As shown, the online architecture for inverter program upgrades also includes a first AND gate unit 450 and a protection unit 440. The output of the latch unit 470 is communicatively connected to the input of the first AND gate unit 450, and the protection unit 440 is connected to the other input of the first AND gate unit 450; the output of the first AND gate unit 450 is control-connected to the relay group 160. The protection unit 440 can continuously send a constant high-level blocking signal to the first AND gate unit 450; the latch unit 470 can send the level signal converted from the relay control signal sent by the controller 420 to the first AND gate unit 450, and then the first AND gate unit 450 can perform corresponding enable control on the relay group 160 according to the output level change of the latch unit 470.

[0050] It should be understood that the specific structure and working principle of the first AND gate unit 450 are well-known to those skilled in the art, and therefore will not be described in detail here; the working logic of the AND gate unit is that it only outputs a high level when all input terminals are high level. The protection unit 440 can be hardware protection or software protection; in this embodiment, hardware protection is preferred. The specific structure and working principle of the protection unit 440 are well-known to those skilled in the art, and therefore will not be described in detail here.

[0051] In this embodiment, the latch unit 470, which can latch the output signal of the controller 420, has various specific structures. For ease of understanding, one of these structures will be described in detail below. Figure 2 and Figure 7 As shown, the encoding and recognition module 460 includes two output terminals, and the latch unit 470 uses a D latch. The inverter program online upgrade architecture also includes a latch data generation unit 480 and a clock signal generation unit 490. The input terminal of the latch data generation unit 480 is communicatively connected to one of the output terminals of the encoding and recognition module 460 and the output terminal of the controller 420, respectively. Thus, the controller 420 can send a relay control signal `relay_ctrl` to the latch data generation unit 480, and the encoding and recognition module 460 can send a level signal `EN1` to the latch data generation unit 480. The output terminal of the latch data generation unit 480 is communicatively connected to the D port of the latch unit 470, so the latch data generation unit 480 can send a relay control signal `relay_ctrl` to the D port of the latch unit 470. The input terminal of the clock signal generation unit 490 is connected to the other output terminal of the encoding and recognition module 460, so the encoding and recognition module 460 can send a level signal `EN2` to the clock signal generation unit 490. The output of the clock signal generation unit 490 is communicatively connected to the EN port of the latch unit 470, so that the clock signal generation unit 490 can send the clock signal clk to the EN port of the latch unit 470. The Q port of the latch unit 470 is communicatively connected to the input of the first AND gate unit 450, so that the latch unit 470 can send the relay control signal relay_ctrl" for controlling the relay group 160 to the first AND gate unit 450; it should be noted that the relay control signal relay_ctrl" here represents a group of signals, and can actually be the control signals of multiple different relays.

[0052] When the controller 420 is operating normally, the constant-level relay control signal relay_ctrl issued by the controller 420 is converted into corresponding level signals EN1 and EN2 by the encoding and recognition module 460. The latch output generation unit 480 and the clock signal generation unit 490 send the relay control signal relay_ctrl" and the clock signal clk to the latch unit 470 respectively according to the corresponding level signals. Then, the latch unit 470 can output the corresponding relay control signal relay_ctrl". The relay control signal relay_ctrl" output by the latch unit 470 and the high-level blocking signal relay_block sent by the protection unit 440 are passed through the first AND gate unit 450 to output a relay drive signal relay_drv with the same level as the relay control signal relay_ctrl to drive the relay group 160. The circuit for driving the relay group 160 is the same as the conventional scheme, so it will not be described in detail here.

[0053] When the host computer 410 sends an upgrade command to the controller 420, the controller 420 can enter upgrade mode. At this time, the controller 420 can send a relay control signal `relay_ctrl` with a constant duty cycle to the encoding and recognition module 460. Then, the encoding and recognition module 460 can convert the pulse signal of the relay control signal `relay_ctrl` into a corresponding level signal and send it to the latch signal generation unit 480 and the clock signal generation unit 490. The latch signal generation unit 480 can send the relay control signal `relay_ctrl` to the latch unit 470 based on the received level signal, and the clock signal generation unit 490 can send the clock signal `clk` to the latch unit 470 based on the received level signal. According to the working logic of the D latch, the latch unit 470 will latch and maintain the relay control signal relay_ctrl´ corresponding to the relay control signal relay_ctrl output by the controller 420 in the previous moment. Then the latch unit 470 can continue to output the relay control signal relay_ctrl” from the previous moment. The first AND gate unit 450 can also continue to output the relay drive signal relay_drv from the previous moment to drive the relay group 160 to continue to remain closed so that the load 300 can continue to work without power loss.

[0054] It should be understood that the specific structure and working principle of the D latch are well-known to those skilled in the art, and therefore will not be described in detail here; for ease of understanding, the truth table of the D latch is as follows: Figure 3 As shown, when the EN port is high, the Q port can output the level signal of the D port; when the EN port is low, the Q port will maintain the level state of the previous moment.

[0055] It is understandable that, due to potential time errors in port communication, when the controller 420 completes its level reset after the upgrade, it is necessary to ensure that the relay control signal relay_ctrl´ is set to a high level simultaneously with or before the clock signal clk. This is to ensure that the relay control signal relay_ctrl´ output by the D latch meets the requirements for maintaining the normal operation of the relay group 160. Therefore, in this embodiment, the clock signal clk can preferably be delayed; that is, the function of the clock signal generation unit 490 is to generate a clock signal clk that is delayed by the set time of the relay control signal relay_ctrl´.

[0056] In this embodiment, as Figure 2 , Figure 4 , Figure 7 and Figure 8 As shown, the encoding and recognition module 460 includes a duty cycle conversion unit 461, a voltage range recognition unit 462, and an output signal generation unit 463, which are connected in sequence for communication. The duty cycle conversion unit 461, as the input terminal of the encoding and recognition module 460, can communicate with the controller 420. The duty cycle conversion unit 461 can receive the relay control signal `relay_ctrl` from the controller 420 and convert it into voltage information based on its duty cycle information `d`. The voltage range recognition unit 462 can receive the voltage information sent by the duty cycle conversion unit 461 and compare it with a set threshold. The output signal generation unit 463 can receive the comparison result from the voltage range recognition unit 462 and output the corresponding level signals EN1 and EN2 to the latch data generation unit 480 and the clock signal generation unit 490.

[0057] It is understandable that the duty cycle conversion unit 461 can have various structures. In this embodiment, an RC circuit is preferred, where a resistor R is connected in series between the controller 420 and the voltage range identification unit 462, and a capacitor C is connected in parallel to ground with respect to the resistor R. The voltage range identification unit 462 can also have various specific structures. In this embodiment, two comparators are preferred. One input of each comparator receives the voltage information v sent by the duty cycle conversion unit 461, and the other input of each comparator receives a set threshold v. th1 and v th2 , and v th1 <v th2 The output signal generation unit 463 can generate signals based on voltage information v and a threshold v. th1 and v th2 The comparison results are used to output the corresponding level signals EN1 and EN2. The specific structure of the output signal generation unit 463 is related to the level control state of the controller 420 on the relay group 160.

[0058] It should be understood that, generally, the controller 420 can send a high-level signal to control the relay group 160 during normal operation; that is, the controller 420 can use high duty cycle PWM control before the upgrade, and low duty cycle PWM control during the program upgrade preparation phase. However, in some scenarios, the controller 420 can also control the relay group 160 using low duty cycle PWM control during normal operation, and high duty cycle PWM control during the program upgrade preparation phase. It is important to know that in both scenarios, the latch unit 470 always outputs a high-level relay control signal "relay_ctrl" to control the relay group 160; that is, the closing of the relay group 160 is still controlled by a high level. The function of the output signal generation unit 463 is to output corresponding level signals EN1 and EN2 according to the different control scenarios to ensure the normal operation of the latch unit 470. For ease of understanding, the two control scenarios of the controller 420 will be explained in detail below with specific examples.

[0059] Specific example 1:

[0060] This is for a scenario where the controller 420 sends a high-level signal during normal operation to control the relay group 160. For example... Figure 2 and Figures 4 to 6 As shown, the corresponding threshold v th2 The output of the comparator can be directly connected to the input of the clock signal generation unit 490, corresponding to the threshold v. th2 The output of the comparator can be directly used as the output level signal EN2 of the output signal generation unit 463. The output signal generation unit 463 also includes a second AND gate unit. The two inputs of the second AND gate unit are communicatively connected to the outputs of the two comparators, respectively. The output of the second AND gate unit is connected to the input of the latch data generation unit 480, thus allowing the second AND gate unit to send the level signal EN1 to the latch data generation unit 480. The specific structure and working principle of the second AND gate unit are well-known to those skilled in the art and will not be described in detail here. The working logic of the second AND gate unit is that it only outputs a high level when all inputs are high.

[0061] Meanwhile, the latch data generation unit 480 can have various structures, such as using an OR gate. One input of the latch data generation unit 480 is used to receive the level signal EN1, and the other input is used to receive the relay control signal relay_ctrl. The clock signal generation unit 490 includes an inverter and a delay unit connected in sequence. There are various types of inverters, but a NOT gate is generally used. The inverter can receive the level signal EN2, flip its level state, and send it to the delay unit. The delay unit can send the flipped level signal to the EN port of the latch unit 470 after a set delay. The specific structure and working principle of the OR gate and NOT gate are well known to those skilled in the art, and therefore will not be described in detail here. The working logic of the OR gate is that it outputs a low level only when all inputs are low. The working logic of the NOT gate is that the output level is opposite to the input level.

[0062] In this scenario, we can set the condition as v > v th2 When v < v, both level signals EN1 and EN2 are 0; when v < v th1 When v is at that time, the level signal EN1 is 0 and the level signal EN2 is 1; when v th1 <v<v th2 At this time, both the level signals EN1 and EN2 are 1. It can be understood that the threshold v... th1 and v th2 The specific value can be set according to actual needs; for example, a threshold v can be set. th1 Corresponding to a 30% duty cycle, the threshold v th2 This corresponds to a 70% duty cycle. It should be noted that the values ​​0 and 1 for the level signals EN1 and EN2 represent low and high levels, respectively. For ease of understanding, the normal operation, upgrade, and shutdown processes of controller 420 will be described in detail below. The upgrade process of controller 420 will be illustrated by an example of the output duty cycle information d decreasing from 100% to 50%; the shutdown control of controller 420 will be explained in detail by an example of the duty cycle information d decreasing from 100% to 0%.

[0063] Initially, such as Figure 5 and Figure 6 As shown, the duty cycle information d of the relay control signal relay_ctrl output by controller 420 is 100%. At this time, the voltage information v obtained by duty cycle conversion unit 461 after duty cycle conversion is greater than the threshold v. th2This causes both level signals EN1 and EN2 to be 0. At this time, the latch data generation unit 480 can output a relay control signal relay_ctrl" corresponding to the level of the relay control signal relay_ctrl; simultaneously, the clock signal generation unit 490 flips the level signal EN2 to a high level through an inverter and then outputs a clock signal clk after a set delay time through a delay unit. Furthermore, according to the working logic of the latch unit 470, the latch unit 470 can send a high-level relay control signal relay_ctrl" to participate in the high-level enable control of the relay group 160.

[0064] like Figure 5 As shown, when the controller 420 needs to upgrade its program and reduce the duty cycle information d of the output relay control signal relay_ctrl from 100% to 50%, the value of the voltage information v obtained by the duty cycle conversion unit 461 through duty cycle conversion begins to decrease. When the voltage information v decreases to the threshold v th2 At that time, that is Figure 5 The voltage range identification unit 462 can flip the comparator during the duty cycle identification time, i.e., point a. Figure 5 The b region is located in the middle; after passing through the output signal generation unit 463, it can simultaneously output high-level signals EN1 and EN2. At this time, the latch data generation unit 480 will continue to output a high-level relay control signal relay_ctrl´ based on the level signal EN1; simultaneously, the clock signal generation unit 490, under the action of the inverter and the delay unit, can output a low-level clock signal clk after a set delay time; the delay time corresponds to... Figure 5 The position is in region c. At this time, the latch unit 470 can operate in latch mode according to its own logic, latching the high-level relay control signal relay_ctrl´ from the previous moment. Then, the latch unit 470 can continue to output the corresponding high-level relay control signal relay_ctrl" to participate in the high-level enable control of the relay group 160, ensuring that the relay group 160 continues to maintain normal closed operation.

[0065] like Figure 6 As shown, when the controller 420 turns off the relay group 160, reducing the duty cycle information d of the output relay control signal relay_ctrl from 100% to 0%, the value of the voltage information v obtained by the duty cycle conversion unit 461 through duty cycle conversion decreases rapidly. When the voltage information v decreases to the threshold v... th2 At that time, that is Figure 6 At point a1, the comparator in the voltage range identification unit 462 flips, and after passing through the output signal generation unit 463, it can simultaneously output high-level signals EN1 and EN2. However, the voltage signal v will quickly drop to the threshold v. th1,Right now Figure 6 At point a2, the comparator in the voltage range identification unit 462 will flip again, outputting a low-level signal EN1 and a high-level signal EN2.

[0066] During this process, the relay control signal relay_ctrl´ output by the latch data generation unit 480 first goes high and then quickly goes low. Simultaneously, the clock signal generation unit 490, under the action of the inverter and delay unit, can delay the output of a low-level clock signal clk for a set time. At this time, the latch unit 470 can latch the low-level relay control signal relay_ctrl´ according to its own logic, that is, the relay control signal relay_ctrl´ output by the latch unit 470 is low, thus participating in the control of the relay group 160 to realize the turn-off of the relay group 160. Therefore, by reasonably setting the delay time of the clock signal generation unit 490, i.e. Figure 6 Positioning the latch in region c ensures that the latch unit 470 latches the required value without erroneous latching due to transitional states. For example, a 50% duty cycle between 100% and 0% of the duty cycle information d will not affect latching. That is, the low-level clock signal clk is generated from the first toggle of the voltage range identification unit 462, and by the time the latch unit 470 receives the clock signal clk, it has already received the level signal generated by the second toggle of the voltage range identification unit 462.

[0067] Understandably, to avoid comparator mis-flipping, the RC time constant corresponding to the duty cycle conversion unit 461 can be appropriately increased, or a hysteresis comparator can be used to eliminate the impact of disturbances. Meanwhile, based on the above description, during the upgrade process of controller 420, it is necessary to maintain the voltage information v corresponding to its output duty cycle information d at the threshold v. th1 and v th2 The specific structure and working principle of the delay unit are well-known to those skilled in the art, and therefore will not be described in detail here.

[0068] Specific example two:

[0069] This addresses a scenario where the controller 420 sends a low duty cycle signal during normal operation to control the relay group 160. For example... Figures 7 to 9 As shown, the corresponding threshold v th2 The output of the comparator directly sends the level signal EN1 to the latch data generation unit 480. The output signal generation unit 463 also includes a NOT gate unit and a second AND gate unit. The input of the NOT gate unit is communicatively connected to the level signal EN1, and the output of the NOT gate unit and the output of another comparator are connected to the input of the second AND gate unit. The AND gate unit can output the level signal EN2.

[0070] Meanwhile, the latch data generation unit 480 employs an OR gate; one input of the latch data generation unit 480 is used to receive the level signal EN1, and the other input is used to receive the relay control signal relay_ctrl. The clock signal generation unit 490 includes a delay unit, which can receive the level signal EN2 and send it to the EN port of the latch unit 470 after a set delay.

[0071] In this scenario, we can set the condition as v > v th2 When v < v, the level signal EN1 is 1 and the level signal EN2 is 0; th1 When v is at that time, both level signals EN1 and EN2 are 0; when v th1 <v<v th2 At that time, the level signal EN1 is 0, and the level signal EN2 is 1. For ease of understanding, the threshold value v will be used as an example below. th1 Corresponding to a 30% duty cycle, the threshold v th2 The upgrade process for controller 420 corresponding to a 70% duty cycle is described in detail. The upgrade process for controller 420 will be illustrated by an increase in the output duty cycle information d from 50% to 100%; for normal control and shutdown control of controller 420, refer to Example 1 above, where only level inversion is required.

[0072] like Figure 9 As shown, when the controller 420 needs to upgrade its program to increase the duty cycle information d of the output relay control signal relay_ctrl from 50% to 100%, the value of the voltage information v obtained by the duty cycle conversion unit 461 will begin to rise. When the voltage information v rises to the threshold v... th2 At that time, that is Figure 9 The voltage range identification unit 462 can flip the comparator during the duty cycle identification time, i.e., point a. Figure 9 The b region is located in the middle; after passing through the output signal generation unit 463, it can simultaneously output a high-level signal EN1 and a low-level signal EN2.

[0073] At this time, the latch data generation unit 480 will output a high-level relay control signal relay_ctrl´ according to the level signal EN1; simultaneously, the clock signal generation unit 490 will output a low-level clock signal clk according to the level signal EN2 after a set delay time; the delay time corresponds to... Figure 9The position is in region c. At this time, the latch unit 470 can operate in latch mode according to its own logic, latching the high-level relay control signal relay_ctrl´ from the previous moment. Then, the latch unit 470 can continue to output the corresponding high-level relay control signal relay_ctrl" to participate in the high-level enable control of the relay group 160, ensuring that the relay group 160 continues to maintain normal closed operation.

[0074] It is understood that both of the above examples can meet the needs of this application, and those skilled in the art can choose according to their actual needs; for the convenience of the following description, the following content will be described using the above example one as an example.

[0075] In this embodiment, as Figure 2 As shown, after the controller 420 enters the upgrade state, the relay control signal relay_ctrl can be pulled down to a low level by the reset pull-down device 430. The specific structure and working principle of the reset pull-down device 430 are well known to those skilled in the art, and therefore will not be described in detail here. After the controller 420 completes the upgrade, it can be reset. At this time, the relay control signal relay_ctrl can be powered back up to a high level, so that the controller 420 resumes control of the relay group 160. At this time, the latch unit 470 can disengage from the latching state.

[0076] It should be understood that many controllers 420 require software protection functionality; therefore, the online inverter program upgrade architecture in this embodiment requires a software protection circuit with software protection functionality. For ease of understanding, the specific structure of the software protection circuit will be described below.

[0077] Specifically, such as Figure 10 As shown, the software protection circuit includes a software protection unit 421, which employs a third AND gate. The input of the third AND gate is communicatively connected to the controller 420, allowing the controller 420 to send a software protection signal `relay_block_s` and a relay control signal `relay_ctrl` to the input of the third AND gate. The output of the third AND gate is communicatively connected to the input of the encoding and recognition module 460, ensuring that the operating state of the latch unit 470 is affected by the level of the software protection signal `relay_block_s`, thereby realizing the software protection function of the circuit.

[0078] In this embodiment, the operating scenarios of the controller 420 include not only single controller 420 operating scenarios but also multi-controller 420 operating scenarios; a specific example is, for instance... Figures 11 to 13As shown, there are two controllers 420. One controller 420 controls the DC / DC unit 120 and the bidirectional DC / DC unit 140, while the other controller 420 controls the DC / AC unit 150. However, this layout is not the only possible arrangement. Furthermore, in scenarios with multiple controllers 420, the control methods of the relay group 160 by these controllers can vary. For example, only one controller 420 may participate in the control of the relay group 160, while the others may not. Alternatively, multiple controllers 420 may participate in the control of the relay group 160 simultaneously. To facilitate understanding, three specific examples will be used to illustrate this in detail below.

[0079] Example 1: such as Figure 11 As shown, there are multiple controllers 420, one of which participates in the control of relay group 160, while the other controllers 420 do not participate in the control of relay group 160. The controller 420 participating in the control of relay group 160 is communicatively connected to the encoding and identification module 460, while the other controllers 420 are communicatively connected to the controller 420 connected to the encoding and identification module 460 or to the host computer 410.

[0080] To facilitate understanding, the following detailed description of the operation process in Example 1 will be based on two controllers 420. The two controllers 420 can be defined as controller DSP#1 and controller DSP#2, respectively. Controller DSP#1 controls the DC / DC unit 120, the bidirectional DC / DC unit 140, and the relay group 160, while controller DSP#2 only controls the DC / AC unit 150 and does not participate in the control of the relay group 160. The host computer 410 communicates with controller DSP#1, and controller DSP#1 communicates with controller DSP#2, such as via I2C communication. Controller DSP#1 can control controller DSP#2 for upgrades via signal lines boot2 and reset2; conversely, controller DSP#2 can also directly communicate with the host computer 410 via signal lines boot2 and reset2, allowing the host computer 410 to directly control controller DSP#2 for upgrades. In this scenario, controller DSP#1 controls the relay group 160 through the hardware architecture described above, while controller DSP#2 does not participate in relay control.

[0081] Example 2: such as Figure 12As shown, there are multiple controllers 420, encoding and recognition modules 460, and latching units 470. Each controller 420 is connected to a corresponding encoding and recognition module 460 and latching unit 470 to form a control branch. The controllers 420, serving as inputs to each control branch, are interconnected, and one of the controllers 420 is also interconnected with a host computer 410. Each latching unit 470, serving as an output to each control branch, is connected to the input of the first AND gate unit 450; thus, the control of the relay group 160 is determined jointly by multiple controllers 420.

[0082] To facilitate understanding, the working process of Example 2 will be described in detail below using two controllers 420 as an example. The two controllers 420 can be defined as controller DSP#1 and controller DSP#2, respectively; where controller DSP#1 controls the DC / DC unit 120 and the bidirectional DC / DC unit 140, and controller DSP#2 controls the DC / AC unit 150; the relay group 160 is jointly controlled by controller DSP#1 and controller DSP#2.

[0083] Simultaneously, the host computer 410 communicates with controller DSP#1, and controller DSP#1 communicates with controller DSP#2, such as via I2C communication. Furthermore, controller DSP#1 can upgrade controller DSP#2 via signal lines boot2 and reset2. It is important to note that in this scenario, signal lines boot2 and reset2 need to be pulled up to prevent controller DSP#2 from being reset due to the upgrade of controller DSP#1.

[0084] In this architecture, the relay control signal relay_ctrl_1 output by controller DSP#1 is processed through the corresponding control branch to obtain the relay control signal relay_ctrl_1". Simultaneously, the relay control signal relay_ctrl_2 output by controller DSP#2 is processed through the corresponding control branch to obtain the relay control signal relay_ctrl_2". The relay control signals relay_ctrl_1" and relay_ctrl_2" together with the blocking signal relay_block output by protection unit 440 are processed through the first AND gate unit 450 to obtain the required relay drive signal relay_drv, thereby controlling the relay group 160. It is worth noting that the relationship between the relay control signals relay_ctrl_1" and relay_ctrl_2" can be more than just logical AND; other logical relationships can also be used, which can be selected according to actual application requirements.

[0085] Understandably, in this architecture, if controller DSP#1 is upgraded, its upgrade process is the same as that of the single controller 420 mentioned above, and therefore will not be repeated here. If controller DSP#2 is upgraded, then controller DSP#1 will act as the host computer 410, enabling controller DSP#2 to perform the same upgrade process as the single controller 420 mentioned above. It should be noted that this architecture cannot achieve simultaneous upgrades of multiple controllers 420.

[0086] Example 3: such as Figure 13 As shown, there are multiple controllers 420, encoding and recognition modules 460, and latching units 470. Controllers 420 are connected to corresponding encoding and recognition modules 460 and latching units 470 to form control branches. Controllers 420, which serve as input terminals of each control branch, are all connected to the host computer 410; latching units 470, which serve as output terminals of each control branch, are all connected to the input terminal of the first AND gate unit 450; thus, the control of the relay group 160 is jointly determined by multiple controllers 420.

[0087] For ease of understanding, the working process of Example 2 will be described in detail below using two controllers 420 as an example. The two controllers 420 can be defined as controller DSP#1 and controller DSP#2, respectively. Controller DSP#1 controls the DC / DC unit 120 and the bidirectional DC / DC unit 140, while controller DSP#2 controls the DC / AC unit 150. The relay group 160 is jointly controlled by controllers DSP#1 and DSP#2. Simultaneously, the host computer 410 communicates separately with controllers DSP#1 and DSP#2, such as through SCI communication. The host computer 410 can upgrade controller DSP#1 via signal lines boot1 and reset1, and upgrade controller DSP#2 via signal lines boot2 and reset2. The control process under this architecture is the same as in Example 2 above, and therefore will not be repeated here.

[0088] It is understandable that the program upgrades of controller DSP#1 and controller DSP#2 under this architecture are independent of each other, so they can be upgraded simultaneously. The specific upgrade process of controller DSP#1 and controller DSP#2 is the same as the upgrade process of the single controller 420 mentioned above, so it will not be repeated here.

[0089] Another aspect of this application provides an online inverter program upgrade method utilizing the aforementioned online inverter program upgrade architecture, such as... Figure 14 As shown, one preferred embodiment includes a preparation phase, an upgrade phase, and an upgrade completion phase; specifically, it includes the following processes:

[0090] (1) Upgrade preparation stage: When an online program upgrade is required, the host computer 410 can send a program upgrade preparation instruction to the controller 420; after receiving the instruction, the controller 420 controls the current working mode of the inverter.

[0091] If the inverter is in grid-connected mode, it will execute relay-maintained control mode through the aforementioned online inverter program upgrade architecture. If the inverter is in off-grid mode, it will further determine whether the inverter meets the grid-connected requirements; for inverters that meet the grid-connected requirements, it will switch to grid-connected mode and then execute relay-maintained control mode through the aforementioned online inverter program upgrade architecture; for inverters that do not meet the grid-connected requirements, it will remain in off-grid mode.

[0092] It should be noted that in the relay sustain control mode, the relay maintains its state from the previous moment, and the control command from the controller 420 at the next moment will no longer affect the relay's opening and closing. Specifically, when the controller 420 prepares to upgrade and pulls the relay control signal `relay_ctrl` low, the relay group 160 maintains a high-level enabled state under the latching state of the latching unit 470 to remain closed. The controller 420's signal level at the next moment, latched by the latching unit 470, will no longer control the relay group 160. In other words, when executing the relay sustain control mode, the output clock signal `clk` needs to be set low when the relay control signal `relay_ctrl` is high in the previous moment to achieve latching of the relay control signal `relay_ctrl` by the latching unit 470.

[0093] (2) Upgrade Phase: After the inverter switches to relay sustain control mode, the controller 420 can report to the host computer 410 that the preparation phase for program upgrade is complete. Subsequently, after receiving the upgrade preparation information from the controller 420, the host computer 410 begins the program upgrade. First, the host computer 410 pulls the signals output by the boot and reset signal lines low, causing the controller 420 to enter the program upgrade mode; then, the controller 420 can receive the upgrade program package transmitted by the host computer 410 through the SCI signal line to complete the upgrade.

[0094] (3) Upgrade completion stage: After the program upgrade of controller 420 is completed, the relay control signal relay_ctrl output by controller 420 needs to ensure that the clock signal clk is set to high level no later than the clock signal clk. Then controller 420 starts to perform normal control work.

[0095] It should be noted that in this embodiment, the relay sustaining mode is executed as follows: before the controller 420 executes the program upgrade preparation instruction, the relay control signal relay_ctrl uses one encoding method, such as a constant level encoding method; after executing the program upgrade preparation instruction, the relay control signal relay_ctrl uses another encoding method, such as a 50% duty cycle pulse encoding method. The external circuit performs relay sustaining control by recognizing the two different encodings.

[0096] To make it easier to understand, the following will focus on Figure 2 The scenario shown, where a high-level control relay group 160 is used in a single controller 420 scenario, provides a detailed description of the entire upgrade process for controller 420. The upgrade process for controller 420 can be divided into an upgrade preparation phase, an upgrade process phase, and an upgrade completion phase.

[0097] I. Upgrade Preparation Phase.

[0098] like Figure 15 As shown, the host computer 410 sends an upgrade preparation command to the controller 420 via communication. Upon receiving the program upgrade preparation command, the controller 420 converts the relay control signal relay_ctrl from a constant high level to a PWM signal; at this time, the duty cycle of the PWM signal is constant, and the intervention threshold v... th1 and v th2 Between. Then, after passing through the encoding and recognition module 460, the relay control signal relay_ctrl can output high-level signals EN1 and EN2. The level signal EN1 and the relay control signal relay_ctrl, after passing through the latch data generation unit 480, can output a high-level relay control signal relay_ctrl'. The level signal EN2 is delayed by the clock signal generation unit 490. The low-level clock signal clk at time t. The falling edge of the clock signal clk triggers the latching function of latch unit 470, causing latch unit 470 to latch the currently high-level relay control signal relay_ctrl´. After controller 420 completes preparation, controller 420 can send feedback information to host computer 410 indicating that preparation is complete, and begin the upgrade process. It should be noted that... Figure 4 Part A represents the upgrade preparation command sent by the host computer 410 to the controller 420, and Part C represents the preparation completion information fed back by the controller 420 to the host computer 410.

[0099] II. Upgrade Process Stage.

[0100] like Figure 15As shown, after receiving the preparation completion information from the controller 420, the host computer 410 can set the outputs of the boot and reset signal lines to low level, enabling the controller 420 to enter the upgrade state. Specifically, the boot signal line outputs a low level approximately 10ms before the reset signal line. At this time, due to the pull-down of the reset pull-down device 430, the relay control signal relay_ctrl is pulled down to a low level. Then, after passing through the encoding and recognition module 460, a low-level signal EN1 and a high-level signal EN2 can be output. The level signal EN1 and the relay control signal relay_ctrl, after passing through the latched data generation unit 480, can output a low-level relay control signal relay_ctrl'; the level signal EN2, after passing through the clock signal generation unit 49, still generates a delay. The low-level clock signal clk occurs at time t. During this time, latch unit 470 maintains the latched state of the upgrade preparation phase, meaning the relay control signal relay_ctrl" output by latch unit 470 remains high. After controller 420 enters the upgrade state and the reset is completed (at which point the reset signal line returns to high level), host computer 410 can send the upgrade package to controller 420 via communication and perform the upgrade. It should be noted that... Figure 15 Part b in the middle represents the process of the host computer 410 sending the upgrade program package to the controller 420.

[0101] III. Upgrade Completion Phase.

[0102] like Figure 15 As shown, after the upgrade package is sent, i.e., after the controller 420 completes the upgrade, the controller 420 begins executing the user program. At this time, the relay control signal relay_ctrl output by the controller 420 is reset to a high level. It should be noted that, due to the presence of the delay circuit 460, the relay control signal relay_ctrl can be set to a high level before or simultaneously with the clock signal clk, but the clock signal clk is not allowed to be set to a high level first. After the relay control signal relay_ctrl is reset to a high level, the encoding and recognition module 460 can output low-level signals EN1 and EN2. The level signals EN1 and relay control signal relay_ctrl, after passing through the latched data generation unit 480, can output a high-level relay control signal relay_ctrl'. The level signal EN2, after passing through the clock signal generation unit 490, can generate a delay. When the high-level clock signal clk at time t causes the latch unit 470 to release the latch state, the relay control signal relay_ctrl" output by the latch unit 470 is the current high-level relay control signal relay_ctrl, thereby ensuring that the relay group 160 continues to maintain the closed working state to continue to maintain the load 300 without power loss.

[0103] It should be understood that the above-described working process is the working process of controller 420 in the upgraded state. When controller 420 is upgraded and reset, it is necessary to maintain control over relay group 160. Controller 420 also includes working scenarios in the non-upgraded state, such as the power-on reset scenario of controller 420 and the normal on / off control scenario of relay group 160. For ease of understanding, the control of relay group 160 in the non-upgraded state scenario of controller 420 will be explained in detail below.

[0104] For the power-on reset scenario of controller 420, controller 420 does not need to maintain control of relay group 160; the specific control process of controller 420 over relay group 160 is as follows: Figure 16 As shown, when the controller 420 performs a power-on reset, its output relay control signal relay_ctrl is initially at a low level. After passing through the encoding and recognition module 460, it can output a low-level signal EN1 and a high-level signal EN2. The level signal EN1 and the relay control signal relay_ctrl, after passing through the latch data generation unit 480, output a low-level relay control signal relay_ctrl'. The level signal EN2, after passing through the clock signal generation unit 490, outputs a low-level clock signal clk, and the latch unit 470 latches the currently low-level relay control signal relay_ctrl'. Until the power-on reset of the controller 420 ends, the relay control signal relay_ctrl will be set to a high level, and then, after passing through the encoding and recognition module 460, it will output low-level signals EN1 and EN2. The level signal EN1 and the relay control signal relay_ctrl, after passing through the latch data generation unit 480, can output a high-level relay control signal relay_ctrl'. The level signal EN2, after passing through the clock signal generation unit 490, can generate a delay. When the high-level clock signal clk at time t causes the latch unit 470 to release from the latch state, the relay control signal relay_ctrl" output by the latch unit 470 is the current high-level relay control signal relay_ctrl.

[0105] For the normal on / off control scenario of relay group 160, the specific control process of controller 420 is as follows: Figure 17As shown, the controller 420 outputs a low-level relay control signal relay_ctrl. After passing through the encoding and recognition module 460, it outputs a low-level signal EN1 and a high-level signal EN2. The signal EN1 and the relay control signal relay_ctrl pass through the latch data generation unit 480 to output a low-level relay control signal relay_ctrl'. The signal EN2 passes through the clock signal generation unit 490 to obtain a low-level clock signal clk; at this time, the latch unit 470 latches the currently low-level relay control signal relay_ctrl'.

[0106] When the relay control signal relay_ctrl output by controller 420 is reset to high level, the encoding and recognition module 460 outputs low-level signals EN1 and EN2 after a recognition delay. After passing through the latch data generation unit 480, the level signal EN1 and the relay control signal relay_ctrl can output a high-level relay control signal relay_ctrl'. The level signal EN2 can be delayed after passing through the clock signal generation unit 490. When the high-level clock signal clk at time t causes the latch unit 470 to release from the latch state, the relay control signal relay_ctrl" output by the latch unit 470 is the current high-level relay control signal relay_ctrl.

[0107] The basic principles, main features, and advantages of this application have been described above. Those skilled in the art should understand that this application is not limited to the above embodiments. The embodiments and descriptions in the specification are merely the principles of this application. Various changes and modifications can be made to this application without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claims. The scope of protection claimed by this application is defined by the appended claims and their equivalents.

Claims

1. An online upgrade architecture for inverter programs, characterized in that, include: Host computer; the host computer is adapted to issue upgrade commands; The controller is connected to the host computer and is adapted to control the relay group through a control signal, which is an coded signal. An encoding and recognition module; the controller is communicatively connected to the encoding and recognition module, and the encoding and recognition module is adapted to convert the control signals issued by the controller into corresponding logic level signals; as well as A latching unit; the latching unit is communicatively connected to the output terminal of the encoding and recognition module, and the latching unit is adapted to output a level signal to the control signal issued by the controller according to the received logic level signal, or to latch the high level signal of the controller before the upgrade; The encoding and recognition module includes two output terminals, and the latching unit adopts a D latch. The online upgrade architecture for the inverter program also includes: A latched data generation unit; the output terminal of the latched data generation unit is communicatively connected to the D port of the latching unit, and one output terminal of the encoding and recognition module and the control signal output by the controller are communicatively connected to the input terminal of the latched data generation unit; and A clock signal generation unit; the output terminal of the clock signal generation unit is communicatively connected to the EN port of the latch unit; another output terminal of the encoding and recognition module is communicatively connected to the input terminal of the clock signal generation unit; The encoding and recognition module includes a duty cycle conversion unit, a voltage range recognition unit, and an output signal generation unit that are connected in sequence via communication. The duty cycle conversion unit is adapted to convert the duty cycle information of the control signal issued by the controller into voltage information; The voltage range identification unit is adapted to compare voltage information with a set threshold. The output signal generation unit is adapted to output a corresponding level signal based on the comparison result.

2. The inverter program online upgrade architecture as described in claim 1, characterized in that, The output signal generation unit sends level signals EN1 and EN2 to the latch data generation unit and the clock signal generation unit, respectively; The voltage range identification unit includes two comparators. One input of each comparator receives voltage information v sent by the duty cycle conversion unit, and the other input of each comparator receives a set threshold v. th1 and v th2 And v th1 <v th2 ; If the controller sends a high level to control the relay group during normal operation; when v > v th2 When v < v, both level signals EN1 and EN2 are 0; when v < v th1 When v is at that time, the level signal EN1 is 0 and the level signal EN2 is 1; when v th1 <v<v th2 At that time, both level signals EN1 and EN2 are 1; If the controller sends a low duty cycle signal to control the relay group during normal operation; when v > v th2 When v < v, the level signal EN1 is 1 and the level signal EN2 is 0; th1 When v is at that time, both level signals EN1 and EN2 are 0; when v th1 <v<v th2 At that time, the level signal EN1 is 0 and the level signal EN2 is 1.

3. The inverter program online upgrade architecture as described in claim 2, characterized in that, If the controller sends a high-level signal to control the relay group during normal operation; the corresponding threshold v th2 The output of the comparator is directly used as the output level signal EN2 of the output signal generation unit; The output signal generation unit further includes a second AND gate unit, the two input terminals of which are respectively communicatively connected to the output terminals of the two comparators, and the second AND gate unit outputs a level signal EN1.

4. The inverter program online upgrade architecture as described in claim 2, characterized in that, If the controller sends a low duty cycle signal to control the relay group during normal operation; the corresponding threshold v th2 The output of the comparator is directly used as the output level signal EN1 of the output signal generation unit; The output signal generation unit further includes a NOT gate unit and a second AND gate unit. The input terminal of the NOT gate unit is communicatively connected to the level signal EN1. The output terminal of the NOT gate unit and the output terminal of another comparator are connected to the input terminal of the second AND gate unit. The AND gate unit outputs the level signal EN2.

5. The inverter program online upgrade architecture as described in any one of claims 2-4, characterized in that, If the controller sends a high level to control the relay group during normal operation; the clock signal generation unit includes an inverter and a delay unit connected in sequence; the inverter is adapted to receive the level signal EN2 and send it to the delay unit after flipping the level state; the delay unit is adapted to send the flipped level signal to the EN port of the latch unit after delaying it by a set time; If the controller sends a low duty cycle signal to control the relay group during normal operation; the clock signal generation unit includes a delay unit, which is adapted to receive the level signal EN2 and send it to the EN port of the latch unit after a set delay.

6. The inverter program online upgrade architecture as described in claim 1, characterized in that, There are multiple controllers, one of which participates in the control of the relay group, while the other controllers do not participate in the control of the relay group; The controller participating in the control of the relay group is communicatively connected to the encoding and identification module, and the other controllers are communicatively connected to the controller connected to the encoding and identification module or the host computer.

7. The inverter program online upgrade architecture as described in claim 1, characterized in that, There are multiple controllers, encoding and recognition modules, and latching units. The controller is connected to the corresponding encoding and recognition module and latching unit to form a control branch. The controllers, which serve as input terminals of each of the control branches, are interconnected or all are interconnected with the host computer; the latching units, which serve as output terminals of each of the control branches, simultaneously output level control signals to control the relay group.

8. A method for online inverter program upgrade using the online inverter program upgrade architecture according to any one of claims 1-7, characterized in that, Includes the following steps: The host computer sends a program upgrade preparation command to the controller; After receiving the instruction, the controller controls the current operating mode of the inverter, enabling the inverter to operate in grid-connected mode and execute relay maintenance control mode. After the inverter completes the switch to relay sustain mode, the controller sends feedback to the host computer that the program upgrade preparation is complete. After receiving the preparation completion information, the host computer sends an upgrade package to the controller and performs the upgrade. After the controller upgrade is completed, a high level is sent to the latch unit to enable normal operation.

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