A reconfigurable FFT operation processor module

Abstract

This invention belongs to the field of FFT computation technology, specifically relating to a reconfigurable FFT operation processor module. It includes an address generation module, a data rearrangement unit, a twiddle factor storage module, an FFT computation module, and a control module; the FFT computation module includes multiple rows of radix-2 arrays arranged side-by-side. 4 The MDC module includes a data rearrangement unit comprising a read / write data storage module and a data preprocessing module. The read / write data storage module consists of multiple memories used to store data input to the MDC module according to a set configuration. The data preprocessing module receives intermediate computation data from the read / write data storage module and further adjusts the arrangement of the data to conform to the input data layout of the next-level MDC module. The twitch factor storage module stores the constant twitch factor required by the MDC module when calculating FFTs with different point counts. The address generation module generates address sequences for data reading / writing. This allows the module to adapt to FFT computation needs of different scales and improves the utilization rate of the butterfly operation unit.

Description

Technical Field

[0001] This invention belongs to the field of FFT computing technology, specifically relating to a reconfigurable FFT operation processor module that supports high-speed processing of large amounts of data. Technical Background

[0002] The Discrete Fourier Transform (DFT) is one of the core algorithms in the field of digital signal processing, mainly used to achieve the conversion between time-domain and frequency-domain signals. The Fast Fourier Transform (FFT) optimizes the calculation process of the DFT by utilizing the periodicity and symmetry of the rotation factor in the DFT to reduce time complexity. This technique has been widely used in many important fields such as image processing, telecommunications and wireless communication systems.

[0003] In recent decades, the hardware implementation technology of FFT has been extensively studied and has mainly developed into two categories. One is the pipelined architecture characterized by high throughput; the other is the storage architecture, which has advantages in hardware area and resource utilization.

[0004] Traditional multi-path delay commutator (MDC) architectures, such as Figure 1 As shown, this architecture allows data to be input into the butterfly unit in parallel, making it suitable for high-throughput scenarios. Each butterfly unit is connected by shuffling units of different depths. However, this architecture suffers from the problem that the internal buffer expands as the number of data points increases, requiring more hardware FIFO resources. Traditional MDC architectures use a radix-2 algorithm, thus necessitating more ordinary complex multiplication units (ordinary multiplication units are indicated by the symbols in the diagram). In other existing technologies, such as reference [2], a single-port memory is used to implement radix-2. k The FFT processor reduces the number of ordinary complex multiplication units, but this architecture still relies on a fixed number of butterfly operation units. This directly limits the range of data points that can be processed (the number of points refers to the number of samples of the input signal during the FFT transformation). In a specific implementation, if the number of butterfly operation units (each butterfly operation unit consists of a subtraction and an addition operation unit) is m, then the range of processed points is 2^m to 2^m. m This means that when the actual number of points to be processed, N << 2, the time frame is within the specified range. m This results in the inability to fully utilize all butterfly operation units, leaving log2N-m butterfly operation units idle. Therefore, this reflects a problem of low resource utilization in pipeline architectures designed for large point counts when performing small-point FFT calculations.

[0005] To address the aforementioned issues, existing technologies have proposed a storage-based FFT structure, comprising a set of memories and multiple processing elements (PEs). The memories and processing elements are interconnected via a multiplexer. This architecture performs FFT calculations by repeatedly transferring data from the storage units to the PEs for processing and writing the processing results back to the storage units. Although this design allows for the reuse of PE units, reducing the circuit footprint, the repeated data iteration process increases the overall computation time. Summary of the Invention

[0006] In view of the problems existing in the prior art, the technical problem to be solved by the present invention is to provide a reconfigurable FFT operation processor module that can adapt to FFT calculation needs of different scales and improve the utilization rate of butterfly operation units.

[0007] The technical problem to be solved by the present invention is achieved through the following technical solution:

[0008] A reconfigurable FFT operation processor module includes an address generation module, a data rearrangement unit, a twitch factor storage module, an FFT calculation module, and a control module;

[0009] The FFT calculation module includes multiple rows of radix-2 arranged side by side. 4 MDC module;

[0010] The data rearrangement unit includes a read / write data storage module and a data preprocessing module;

[0011] The read / write data storage module consists of multiple memories. Each MDC module corresponds to a specific memory, which is used to store the data input to that MDC module according to the settings.

[0012] The data preprocessing module consists of multiple shuffling units of different depths, which are used to receive intermediate computational data from the read and write data storage module and further adjust the arrangement of the data to conform to the input data layout of the next-level MDC module.

[0013] The twist factor storage module is used to store the constant twist factors required by the MDC module when calculating FFTs with different numbers of points;

[0014] The address generation module is used to generate address sequences for data reading / writing using the program counter;

[0015] The control module is used to control the above modules / units to perform FFT calculations according to the following strategy:

[0016] Based on the number of FFT points to be processed, multiple MDC modules are cascaded through data rearrangement units by writing the input data or the calculation output of the previous MDC module into the memory corresponding to the next MDC module.

[0017] Furthermore, the control module is configured to control the memory to perform read / write operations using the following strategy:

[0018] If the memory is full of intermediate data, it needs to be loaded into the next row of MDC cells. The read address pointer RD loads data from the memory according to the position pointed to by the value of the reversed specified bit at the end of each address; at the same time, the write address pointer WT stores new data at the same position until the original data in the memory is completely replaced by the new data.

[0019] In the next round of data updates, the read / write operations at the same address location must be performed in a progressively increasing manner according to the original address.

[0020] In subsequent rounds of data reading / writing, read / write operations at the same address are performed alternately based on the address after bit reversal or the original address;

[0021] Where N is the number of points to be processed in the FFT, and A is a one-dimensional vector. M×1 This indicates the number of bits that vary in the latter part of the address at a fixed number of points, where M is the cascaded radix-2. 4 The number of MDC modules is:

[0022] A M×1 =(a 11 ,a 21 ,a 31 ,…,a M1 ) T

[0023] Where a 11 ,a 21 ,……a M1 These represent the specific values ​​of the bits that need to be reversed in the latter part of the address segment each time the memory is read:

[0024]

[0025] Furthermore, the data rearrangement unit also includes a read / write address bit reversal module, which is used to reverse a specified number of bits in the latter part of the read / write address given by the address generation module for the memory, according to a setting.

[0026] Furthermore, a shuffle unit contains two multiplexers and two cache units of the same depth.

[0027] Furthermore, the control module is also used to select the optimal MDC module cascading method and execution mode based on the required number of FFT calculation points, including:

[0028] Lingji-2 4 The MDC module has n rows, where N is the number of points to be processed in the FFT.

[0029] when At that time, no cascaded base-2 is required. 4 The MDC module, employing a multi-channel parallel execution mode, accepts multiple sequences and... Parallel computation on multiple channels;

[0030] when At that time, the base-2 required for cascading 4 The MDC module adopts a single-channel serial pipeline execution mode;

[0031] when At that time, no cascaded base-2 is required. 4 The MDC module adopts a storage-based FFT execution mode, which completes the FFT operation through multiple iterations.

[0032] Furthermore, it also includes an output data buffer module, which is used to output the results generated by the FFT calculation module to an external cache unit.

[0033] The advantage of this invention is that it proposes a reconfigurable FFT processing module with configurable computing channels, which offers greater flexibility and scalability.

[0034] This invention employs a segmented rearranged MDC unit design. To meet the computational requirements of the Fast Fourier Transform (FFT), a data rearrangement unit is added between each isomorphic MDC unit. These data rearrangement units, suitable for any number of data points, are responsible for consolidating the scattered data points in the storage unit. After preprocessing, the data is then ordered and fed into each MDC unit for processing according to the correct interval sequence of the FFT operation. This significantly reduces the FIFO buffer depth within the traditional MDC pipeline when processing large numbers of data points. This not only improves the flexibility of the system architecture but also ensures efficient reuse of all resources when performing small-number calculations. Simultaneously, the data sorting task, originally handled by the internal buffer of the MDC, is now performed by an external data preprocessing module. The segmented rearranged MDC architecture allows for flexible reconstruction of different computational modes, fully utilizing idle MDC units and achieving multi-channel parallelism within the pipeline architecture.

[0035] This invention combines the data rearrangement idea with the high cardinality FFT processor in reference [2], and uses the data rearrangement unit to form a reconfigurable and flexible reconfigurable processor. It can dynamically adjust its hardware configuration according to changes in the operating environment. This feature makes the reconfigurable processor have strong scalability and hardware resource reuse.

[0036] In some embodiments of this invention, a conflict-free access mechanism is proposed. The data rearrangement unit contains a complete set of address generation rules for memory read and write operations, enabling the next MDC unit to read data from the memory unit while the previous MDC unit writes data to the memory unit. This allows for simultaneous read and write operations within the same memory region, and under the condition of satisfying minimum external storage resource constraints, from the perspective of the same batch of data (the writing and reading order is reversed), and from the perspective of the same point in time, the read and write pointer transformation mechanism is the same. This ensures a conflict-free read and write address access mechanism within the same register. Correspondingly, a set of address bit change models is proposed, aiming to accurately calculate the number of address bit changes in each row of memory units under different Fast Fourier Transform input point conditions. This enables in-situ transformation, reducing memory unit consumption. Furthermore, a set of shuffling units with different depths is designed to ensure correct data sorting, so that data generated by each MDC unit can be reordered by the data rearrangement unit and accepted by the next MDC unit in the correct interval order.

[0037] In some embodiments of the present invention, a data rearrangement model is proposed, which assumes that the number of input points for the FFT is N, and that the data is radix-2. 4 The MDC module serves as the core of the processing. In this model, the number of MDC units required to complete the FFT calculation depends on the number of input points N. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of a traditional MDC pipeline in the background art of this invention;

[0039] Figure 2 This is a schematic diagram of the overall architecture of the FFT processor module in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the segmented rearrangement MDC pipeline architecture used in an embodiment of the present invention;

[0041] Figure 4 Base-2 in the embodiments of the present invention 4 MDC pipeline architecture diagram;

[0042] Figure 5 This is a schematic diagram of a conflict-free read / write address translation read / write scheme in an embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram illustrating various computing modes in embodiments of the present invention;

[0044] Figure 7 This is a schematic diagram illustrating the changes in the 1024-point computational data stream in an embodiment of the present invention. Detailed Implementation

[0045] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0046] The basic structure of the reconfigurable FFT processing module in this example is as follows: Figure 2 As shown, it includes an address generation module, a data rearrangement unit, a twitch factor storage module, an FFT calculation module, an output data buffer module, and a control module.

[0047] This processor module uses, for example Figure 3 The segmented rearrangement pipeline architecture shown, in its core module—the FFT calculation module—divides the traditional serial MDC structure into multiple identical MDC modules. All MDC modules are interconnected through data rearrangement units. Each data rearrangement unit provides data to each MDC module and is responsible for processing the data generated by the previous MDC module according to a pre-defined rearrangement setting, ensuring that intermediate results are passed to the next MDC module in the correct index order. In this process, the data rearrangement unit acts as a transfer mechanism, enabling the expansion of MDC modules within the pipeline structure based on different numbers of points.

[0048] The MDC module in this example uses, for example... Figure 4 The high-cardinality MDC architecture shown enables the use of radix-2. k The algorithm utilizes k-dimensional linear indices for construction, thus reducing the number of units required for ordinary complex number multiplication. Figure 2 Used literature [1] The proposed application to base-2 4 The algorithm's MDC FFT architecture can process 16-point FFTs simultaneously. The high-radix MDC architecture adds multiplication units with different attributes, namely constant multiplication units (corresponding to the markings in the diagram). ) and trivial multiplication units (corresponding to the markings in the diagram) In this context, the trivial multiplication unit can realize the function of imaginary multiplication through circuit transformation.

[0049] Figure 5 The figure exemplifies possible rearrangements of the MDC module in the FFT calculation module. The FFT calculation module in the figure consists of four rows of radix-2. 4The FFT processor, composed of MDC modules, has one square corresponding to one butterfly operation unit. The black unidirectional arrows indicate the direction of data flow, and the black curved arrows indicate that the intermediate calculation results of one row of MDC need to be processed by the data rearrangement unit before being input into the next row of MDC. Figure 5 The rearrangement method in (a) enables the four-row MDC modules to process consecutive 16-point sample sequences in parallel. Each row of MDC modules processes a set of 16-point sequences independently. Figure 5 The rearrangement in (b) is that the first and second rows of MDC modules are cascaded, and the third and fourth rows of MDC modules are cascaded. The first two rows and the last two rows are independent of each other, so two completely different sets of 256-point sampling sequences can be processed in parallel. Figure 5 (c) indicates that the four MDC modules are cascaded in sequence, and can only process one set of sampling sequences with an upper limit of 64K at a time. Figure 5 (d) illustrates that when the number of input data points exceeds the processing capacity limit of the four MDC modules cascaded sequentially, a four-channel execution mode based on the storage architecture will be adopted. In this mode, the data will be processed repeatedly in each MDC module.

[0050] To ensure that intermediate results can be passed to the next row of MDC modules in the correct index order, the data rearrangement unit includes a read / write data storage module, a data preprocessing module, and a read / write address bit reversal module.

[0051] The read / write data storage module consists of multiple memory units. In this example, each MDC module corresponds to two memory units. The data result calculated by the previous MDC module will be stored in the memory unit corresponding to the next MDC module according to the rearranged settings.

[0052] The data preprocessing module consists of multiple shuffling units of different depths. Each shuffling unit contains two multiplexers and two cache units of the same depth. The function of the data preprocessing module is to receive intermediate computation data from the read / write data storage module and further adjust the arrangement of the data to conform to the input data layout of the next-level MDC module.

[0053] When N sampled sequences are input into each row of MDC cells, the following correct layout should be satisfied:

[0054] Assume the MDC cardinality is 2. k When the MDC unit receives two lines of data input, the data is arranged into multiple 2×1 matrices. As shown in formula (1):

[0055]

[0056] Two-dimensional matrix This represents the correct data arrangement that the i-th row of MDC should accept, element a. r,c The subscripts r and c represent the row and column indices of the data to be processed, respectively. Let a 0,0 =x(s), then we need to The values ​​of other elements in the matrix and their indices s must satisfy the constraints defined in formula (5). The detailed intermediate steps of formulas (2) to (4) for deriving formula (5) are as follows:

[0057] i represents the number of MDC cells required to complete the N-point FFT calculation.

[0058]

[0059] The matrix input in each line of MDC is The value of l is shown in formula (3):

[0060]

[0061] At this time, the two-dimensional matrix middle element a r,c The range of row and column index values ​​is shown in equation (4):

[0062]

[0063] exist In the matrix, any element a r,c Must be with the first element a 0,0 = There exists a definite data relationship between x(s), such that a r,c =x(s+d), the relationship between the interval parameter d and the subscripts r and c is defined as in formula (5).

[0064]

[0065] To more efficiently complete each adjustment of data arrangement, this example proposes a conflict-free read / write address access scheme in the read / write data storage module. Figure 6 The following example uses a 3-bit address to illustrate this scheme:

[0066] Assuming the memory is currently full of intermediate data and needs to be loaded into the next row of MDC cells, the address generation module first sends an incrementing address sequence (exemplary addresses 0b000-0b111 in the diagram) to the read / write address bit inversion module. Figure 6As shown on the left, the read address pointer RD loads data from the memory (bank) according to the value pointed to by the reversed last 3 bits of each address; simultaneously, when new data needs to be stored, the write address pointer WT also stores the new data in the same reversed 3-bit manner. That is, the order of new data being written to / old data being read from the address is 0b000→0b100→0b010→0b110…; continuously following… Figure 6 The reverse read and reverse write process shown on the left is executed until the original data in the memory is completely replaced by the new data. The new data is stored in the Bank by reversing the address bits.

[0067] In the next round of data updates, it is necessary to follow Figure 6 The read / write operations are performed using a progressively increasing address method, as shown on the right. That is, the order of new data writing / old data reading is 0b000→0b001→0b010→0b011…; in each subsequent round of data reading / writing… Figure 6 Left side and Figure 6 The operations on the right are performed alternately, which ensures that the writing and reading order is reversed for the same batch of data, thus effectively achieving the aggregation of the same group of data. To achieve the above process, the data rearrangement unit is equipped with a read / write address bit inversion module, which is used to generate inverted memory access and memory write addresses.

[0068] By employing a bit-inverted address reading method for data access in memory, data in memory can be accessed at specific intervals, allowing scattered data points in memory to be regrouped. Then, a shuffling unit is used to perform subtle local transformations on the already grouped data. These two steps ensure that the data reaches a desired arrangement state before entering the MDC unit, satisfying the calculation rules of the next-level butterfly arithmetic unit. Furthermore, by pre-emptively changing the read / write order, the depth requirement of the shuffling unit is reduced, and there are no conflicts between reads and writes. While the previous MDC module is writing data to the storage unit, the next MDC module can read data from the bank, enabling simultaneous read and write operations in the same memory area, reducing storage unit consumption, thereby improving overall efficiency and reducing resource overhead.

[0069] Figure 7 The example demonstrates each detailed processing step of a 1024-point data sequence x in the data storage module and the data preprocessing module. Initially, the 1024 data points are stored in the data storage module according to the layout in block 7.1. Through reading from the data storage module and shuffling in the data preprocessing module, the data input into the MDC unit each time conforms to the FFT radix-2. 4 Data computation layout.

[0070] 1024 points of data at base-2 4 The FFT calculation in the MDC unit requires a total of 3 MDC modules, so i∈{1,2,3}. According to formula (4), when i=1, the value of l is 2. With a 0,0 Taking data starting with x(0) as an example, we have:

[0071] a 0,1 =x(s+d)=x(s+256×(0×1+1))=x(256)

[0072] a 1,0 =x(s+d)=x(s+256×(1×2+0))=x(512)

[0073] a 1,1 =x(s+d)=x(s+256×(1×2+1))=x(768)

[0074] At this point, the first input matrix of the first row of MDC is:

[0075]

[0076] Corresponding Appendix Figure 7 The data marked with a dashed box in block 7.4 of the Chinese map.

[0077] When i = 2, the value of l is 8. With a 0,0 Taking data starting with x(0) as an example, we have:

[0078] a 0,1 =x(s+d)=x(s+16×(0×16+1))=x(16)

[0079] a 0,2 =x(s+d)=x(s+16×(0×16+2))=x(32)

[0080] a 0,3 =x(s+d)=x(s+16×(0×16+3))=x(32) ...

[0082] a 0,15 =x(s+d)=x(s+16×(0×16+15))=x(112)

[0083] a 1,1 =x(s+d)=x(s+16×(1×16+1))=x(128)

[0084] a 1,2=x(s+d)=x(s+16×(1×16+2))=x(144)

[0085] a 1,3 =x(s+d)=x(s+16×(1×16+2))=x(160) ...

[0087] a 1,15 =x(s+d)=x(s+16×(1×16+2))=x(160)

[0088] At this point, the first input matrix of the second row of MDC is:

[0089]

[0090] Corresponding Appendix Figure 7 The data marked with a dashed box in block 7.7 of the Chinese map.

[0091] Following this logic, when i = 3, the first input matrix of the third row of MDC is:

[0092]

[0093] Corresponding Appendix Figure 7 The data marked with a dashed box in block 7.13 of the Chinese map.

[0094] It is not difficult to find that the appendix Figure 7 The 1024 input data points saved to the input buffer of the data storage module, represented by blocks 7.1, 7.5, and 7.8 in the middle diagram, do not meet the requirements for the next step of inputting MDC. Therefore, the aforementioned address reversal reading scheme is used in conjunction with an external shuffling unit to adjust the order of the input data.

[0095] Assuming N is the number of FFT input points, the number of FFT changes is closely related to the number of input points N, and the calculation period changes successively as the number of FFT points increases. In formula (6), A M×1 This represents a one-dimensional vector showing the change in the number of bits in the latter part of an address, given a fixed number of points. Where a... 11 ,a 21 ,a M1 These represent the specific values ​​of the address bits being reversed each time the on-chip memory is read. Formulas (6) and (7) summarize matrix A. M1 The mathematical relationship between the dimension and the number of input points, A M×1 The dimension represents the radix 2 that needs to be used. 4 The number of MDC modules. Formulas (8)-(11) define A in detail. M×1 The exact values ​​of each element:

[0096] A M×1 =(a11 ,a 21 ,a 31 ,…,a M1 ) T (6)

[0097] K = log₂N (7)

[0098]

[0099] Using 1024 points as the input points for the FFT, N is 1024 points. Substituting into formulas (7) and (8), we know that M = 3 MDC units are needed to complete the calculation of 1024 points. At this time, A M×1 =(a 11 ,a 21 ,a 31 ,) T Substituting into formulas (9), (10), and (11), we can find that the specific value of each element is a. 11 =9, a 21 =6, a 31 =9, indicating that the last 9 bits of the address need to be reversed before data is sent from the input buffer to the first row of MDC cells. (See attached diagram.) Figure 7 The four data points marked with dashed boxes in block 7.2 in the middle of the graph include the 0th, 256th, 512th, and 768th data points in the input sequence.

[0100] Therefore, by performing the aforementioned address bit reversal data read / write, it can be ensured that data meeting the operational requirements of a single butterfly unit is effectively concentrated in the same area. However, even after this operation, the data still does not meet the requirements. The input arrangement is such that, therefore, this example also utilizes an additional external shuffling unit to adjust the local ordering of the data. As shown in the appendix... Figure 7 As shown in plots 7.3 to 7.4, the data points are rearranged after passing through two delay-reversing shuffling units with buffer depths of 2 and 1 respectively.

[0101] The data distribution obtained after calculation by the first row of MDC units is shown in the attached figure. Figure 7 As shown in patch 7.5, it does not conform to the second row. The input arrangement requires a second data rearrangement module. The second time data is read from the storage unit, the address needs to be read according to a... 21 =6-bit reversal, as shown in the appendix Figure 7 As shown in Figure 7.6, similarly, it also needs to go through a shuffling unit with a depth of 8 to obtain the result that conforms to the second row. Input data. (Attached) Figure 7The data transformation rules in blocks 7.8-7.14 all follow the above process. In summary, the data rearrangement unit uses the method of reversing the bits of the address segment to read the memory and the function of multi-level shuffling, so that unordered data pairs can be sent into the MDC unit at specific intervals.

[0102] The main function of the control module is to generate control signals, selectively activate the MDC unit inside the FFT calculation module, activate the data rearrangement unit, generate the correct memory read and write addresses, and ensure that the data can be correctly loaded and processed and the results can be correctly calculated during the entire program operation.

[0103] In this example, the rotation factor storage module consists of three storage units, one of which stores the constant rotation factor required by an MDC unit. Due to the reusability of the rotation factor, the three storage units store the rotation factors required for calculations of 256 points, 4096 points, and 64K points respectively, which can support calculations of any 32 points to 64K points.

[0104] The address generation module is used to generate addresses for the data rearrangement unit, the rotation factor storage module, and the output data buffer module using a program counter.

[0105] The output buffer module is responsible for outputting the results generated by the FFT calculation module to the external buffer unit.

[0106] With all computing resources consisting of 16 butterfly units, an equivalent comparison reveals that the literature... [1] The base-2 proposed in China 4 Single-channel pipelined FFT processor architecture and base-2 4 Dual-channel pipelined FFT processors differ in their applicable number of points and throughput. While single-channel pipelined FFT processors support FFT operations from 16 to 64K points, their throughput is only 2 sampling points per cycle, making them suitable for scenarios requiring large amounts of data. Dual-channel pipelined FFT processors, on the other hand, offer a throughput of up to 4 sampling points per cycle, but can only handle operations from 16 to 256 points, making them suitable for applications requiring high-speed processing. The solution in this example supports operations with any number of points from 16 to 64K, while maintaining the high throughput advantage of dual-channel pipelined FFT processors. Compared to single-channel pipelined FFT processors, resource utilization is improved by 29.23%, and the range of points processed is expanded by 61.53% compared to dual-channel pipelined FFT processors. This demonstrates that the solution in this example has significant advantages in improving processing efficiency and expanding application scope, making it suitable for a wider range of application needs.

[0107] References:

[0108] [1]Pipelined radix-2 kFeedforward FFT architectures, Garrido M, Grajal J, Sanchez M, et al., IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 1, pp. 23-32, January 2011.

[0109] [2]Scheduling of Data Access for the Radix-2 k Processor Using Single-Port Memory, Jian Wang, Songting Li, Xianbin Li, etc., "IEEE Transactions on VeryLarge Scale Integration (VLSI)

[0110] Systems, Vol. 28, No. 7, pp. 1676-1689, August 2020.

Claims

1. A reconfigurable FFT operation processor module, characterized in that, It includes an address generation module, a data rearrangement unit, a twitch factor storage module, an FFT calculation module, and a control module; The FFT computation module includes multiple rows of base-2 4 MDC module; The data rearrangement unit includes a read / write data storage module and a data preprocessing module; The read / write data storage module consists of multiple memories. Each MDC module corresponds to a specific memory, which is used to store the data to be input to that MDC module according to the settings. The data preprocessing module consists of multiple shuffling units of different depths, which are used to receive intermediate computational data from the read and write data storage module and further adjust the arrangement of the data to conform to the input data layout of the next-level MDC module. The twiddle factor storage module stores the constant twiddle factors required by the MDC module when calculating FFTs with different numbers of points; the address generation module uses the program counter to generate the address sequence for data reading / writing. The control module is used to control the above modules / units to perform FFT calculations according to the following strategy: Based on the number of FFT points to be processed, multiple MDC modules are cascaded through data rearrangement units by writing the input data or the calculation output of the previous MDC module into the memory corresponding to the next MDC module. The control module is also used to select the optimal MDC module cascading method and execution mode based on the required number of FFT calculation points, including: Lingji-2 4 The MDC module has n rows, where N is the number of points to be processed by the FFT; At that time, no cascaded base-2 is required. 4 The MDC module, employing a multi-channel parallel execution mode, accepts multiple sequences and... Parallel computation on multiple channels; At that time, the base-2 required for cascading 4 The MDC module employs a single-channel serial pipelined execution mode; when At that time, no cascaded base-2 is required. 4 The MDC module employs a storage-based FFT execution mode. The FFT operation is completed through multiple iterations.

2. The FFT operation processor module according to claim 1, characterized in that, The control module is configured to control the memory to perform read / write operations using the following strategy: If the memory is full of intermediate data, it needs to be loaded into the next row of MDC cells. The read address pointer RD loads data from the memory according to the position pointed to by the value of the reversed specified bit at the end of each address; at the same time, the write address pointer WT stores new data at the same position until the original data in the memory is completely replaced by the new data. In the next round of data updates, the read / write operations at the same address location must be performed in a progressively increasing manner according to the original address. In subsequent rounds of data reading / writing, read / write operations at the same address are performed alternately based on the address after bit reversal or the original address; Here, let N be the number of points to be processed in the FFT, the one-dimensional vector AM×1 represents the number of bits that change in the address segment with a fixed number of points, and M be the concatenated radix-2. 4 The number of MDC modules is: AM×1=(a11,a21,Q31,…,aM1)T Where a11, a21...am1 represent the specific values ​​of the bits that need to be reversed in the latter part of the address segment each time the memory is read, and are: K = log₂N; ； ； ； an1 = a 21 + 4 × (n - 2); st 2≤n <M; st M>2.

3. The FFT operation processor module according to claim 2, characterized in that, The data rearrangement unit also includes a read / write address bit reversal module, which is used to reverse a specified number of bits in the latter part of the read / write address given by the address generation module for the memory, according to a setting.

4. The FFT operation processor module according to claim 1, characterized in that, A shuffle unit contains two multiplexers and two cache units of the same depth.

5. The FFT operation processor module according to claim 1, characterized in that, It also includes an output data buffer module, which is used to output the results generated by the FFT calculation module to an external cache unit.

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