A hardware acceleration circuit for mixed-precision deep neural networks based on probabilistic computation

Abstract

This invention relates to the fields of integrated circuits and artificial intelligence, specifically to a hardware acceleration circuit for mixed-precision deep neural networks based on probabilistic computation. This invention accelerates the computation of deep neural networks at the hardware circuit level by compensating for errors in existing fine-grained spatial parallel probabilistic multipliers. An error-compensated probabilistic multiplier is designed to overcome the large computational errors of existing fine-grained spatial parallel probabilistic multipliers. This multiplier serves as the basic computational unit of the hardware acceleration circuit for mixed-precision deep neural networks based on probabilistic computation. The 3-bit multiplier used in existing mixed-precision computation units is reduced to a 2-bit granularity, improving upon the shortcomings of existing mixed-precision computation units, such as large area, high latency, and high power consumption, thereby accelerating the probabilistic computation of deep neural network models.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuits and artificial intelligence, and in particular to a hardware acceleration circuit for mixed-precision deep neural networks based on probabilistic computation. Background Technology

[0002] With the rapid development of neural network technology in various fields, its computational requirements are increasing. Currently, various computing architectures are used to accelerate the computation of neural networks. Traditional computing architectures have high hardware complexity and large functional overhead in order to ensure computing power.

[0003] A current probability computation system reduces the computational cost of neural networks by using a traditional probability multiplier as the basic computational unit. A traditional probability multiplier, such as... Figure 1 As shown, the system capable of probabilistic computation actually consists of three parts: a forward conversion module, a probabilistic computation module, and a backward conversion module. The forward conversion module mainly consists of a random number generator, used to generate a random bit stream and encode numbers into sequences of "1"s and "0". The probabilistic computation module performs basic bit operations through simple logic circuits. Probabilistic computation systems have low hardware implementation costs and strong fault tolerance, making them suitable for implementing complex computations or iterative algorithms. However, the dense multiplication and accumulation iteration operations in neural networks hinder their hardware implementation. This makes probabilistic computation systems suitable for computations on neural networks, reducing the computational cost of neural networks. However, while simplifying the size of basic operation units, it sacrifices computational accuracy. The randomness of the bit stream also reduces the degree of overfitting. Therefore, the application of probabilistic computation systems in accelerating neural network computation architectures is limited.

[0004] In existing research on computational architectures, low-bit quantization is a crucial component of transformer network compression. By converting floating-point weights and activations into low-bit fixed-point numbers, the size of the parameters can be significantly reduced. Existing schemes have proposed various post-training methods to quantize activations and weights into INT8 / INT6 formats. However, applying uniform precision to all network layers ignores the sensitivity of different parts of the underlying neural network system to the varying local performance of quantization errors.

[0005] Another approach is precision-scalable quantization, which utilizes the varying degrees of robustness and fault tolerance of neural network layers. Based on this quantization method, various precision-scalable structures can be designed to quantize deep neural network models on mobile devices. To adapt low-bit quantization to hardware, the authors of reference [1] proposed a bit-flexible DNN accelerator called BitFusion, which minimizes bit-granular computation and communication without sacrificing precision. Subsequent researchers developed the SumTogether mode based on the idea of ​​bit fusion and set 2 / 4 / 8 / 16-bit precision to implement DNN processing. They also proposed a precision-scalable 2 / 4 / 8 / bit vector system accelerator based on bit segmentation and combination, namely BSC.

[0006] [1]H.Sharma et al., "Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network," 2018ACM / IEEE 45th AnnualInternational Symposium onComputer Architecture(ISCA), Los Angeles, CA, USA, 2018, pp.764-775, doi:10.1109 / ISCA.2018.00069.

[0007] Traditional probability calculations suffer from long conversion times and high encoder overhead. For binary input data, a number field conversion is first required. Traditional sequence conversions typically result in a length of 2^66. n With bit growth, there is room for optimization in terms of both time and hardware complexity for this part of the circuit.

[0008] In existing mixed-precision architecture designs, each sub-unit is extended by 1 sign bit, meaning that each sub-unit uses a 3-bit multiplier. As the bit width increases, the number of 3-bit multipliers required also increases exponentially, which leads to larger processing area, higher latency, and higher power consumption in mixed-precision operations. Summary of the Invention

[0009] The purpose of this invention is to provide a hardware acceleration circuit for mixed-precision deep neural networks based on probability calculation, which improves the shortcomings of existing mixed-precision arithmetic processing units, such as large area, high latency, and high power consumption, and also improves the shortcomings of existing fine-grained spatial parallel probability multipliers, such as multiple error and sign error in probability calculation, thereby accelerating the probability calculation of deep neural network models.

[0010] This invention provides a hardware acceleration circuit for mixed precision deep neural networks based on probability calculation. The circuit is characterized by using an error-compensated probability multiplier as the basic operation unit. Four of the error-compensated probability multipliers are combined with a shift circuit and an adder to form a 4-bit mixed precision processing unit.

[0011] Preferably, the error-compensated probabilistic multiplier consists of two parts: a fine-grained spatially parallel probabilistic multiplier and an error compensation mechanism.

[0012] The fine-grained spatial parallel probabilistic multiplier includes a forward conversion module, an arithmetic module, and a backward conversion module. The forward conversion module uses weighted extended coding and uniform coding to convert a binary bitstream sequence into an equally weighted bitstream sequence. The arithmetic module performs probabilistic operations. The backward conversion module converts the equally weighted bitstream sequence back into a binary sequence. Let the two 2-bit multipliers be denoted as A and W, respectively. A uses weighted extended coding, and W uses uniform coding. The encoded sequence is expressed by the formula:

[0013] A = (a1a0) bin =(a1a1a0) sto

[0014] W = (w1w0) bin =(w1w0w1) sto

[0015] Where A and W are two 2-bit multipliers, a0 and a1 are the two bits of multiplier A, and w0 and w1 are the two bits of multiplier W. bin Represents the value of the binary field, (·) sto Represents the numerical value of the probability domain, (a1a0) bin This is the two's complement representation of the multiplier A, (a1a1a0) sto It is a probability sequence representation after weighted expansion encoding, (w1w0) bin It is the two's complement representation of the multiplier W, (w1w0w1) sto It is a probability sequence representation after uniform encoding.

[0016] The result of multiplying the probabilities of A and W is expressed by the formula:

[0017] A·W=a1w1+a1w0+a0w1

[0018] The error compensation mechanism uses a shift module to compensate for the error of the operation result of the fine-grained spatial parallel probability multiplier by a factor of 1. A gating mechanism is designed to separate the outputs of signed and unsigned numbers and to compensate for the error of the operation sign.

[0019] Preferably, in the error compensation probability multiplier, such as Figure 2 As shown, the port connection relationship between the fine-grained spatial parallel probability multiplier and the error compensation mechanism is as follows: the input of the error compensation probability multiplier consists of two 2-bit data A and W, split into bits a0, a1, w0, and w1, and a circuit input selection signal C. in Where A has two bits a0 and a1, and W has two bits w0 and w1, the fine-grained spatial parallel probability multiplier produces outputs a1w1, a1w0, and a0w1. These three outputs are connected to the error compensation mechanism. The output a1w1 is connected to a 2-bit shift circuit in the error compensation mechanism, and the outputs a0w1 and a1w0 are each connected to a 1-bit shift circuit in the error compensation mechanism, resulting in a shifted output 2. 2 a1w1、2 1 a1w0、2 1 a0w1, the three shifted outputs are connected to the adder and subtractor, and the outputs are the probabilistic results (A·W) of the unsigned and signed numbers. s_sto and (A·W) u_sto The probability calculation result and C in In the common input gating, (A·W) s_sto Or (A·W) u_sto Output.

[0020] Preferably, the error compensation mechanism utilizes a shift module to compensate for errors in the operation results of the fine-grained spatial parallel probabilistic multiplier by a factor of 1. In a traditional fine-grained spatial parallel probabilistic multiplier, the backward conversion module converts the equally weighted bitstream sequence into a binary sequence. The traditional 2-bit unsigned multiplication operation is expressed by the formula:

[0021] (A·W) u_bin =2 2 a1w1+2 1 a1w0+2 1 a0w1+a0w0

[0022] in,(·) u_bin To represent the result of an unsigned binary operation, the traditional 2-bit signed multiplication operation is expressed by the formula:

[0023] (A·W) s_bin =2 2 a1w1-2 1 a1w0-2 1 a0w1+a0w0

[0024] in,(·) s_bin This represents the result of a signed number binary operation.

[0025] Theoretically, the result of multiplying the probabilities of A and W can be expressed by the formula:

[0026] A·W=a1w1+a1w0+a0w1

[0027] It is evident that without error compensation, the coefficients of probability multiplication are multiples of the theoretical coefficients. Directly using the probability calculation results will result in errors of multiples. Therefore, the aforementioned error compensation mechanism is designed to ensure the characteristics of the original data.

[0028] In digital circuits, shifting a bit to the left by 1 bit achieves a binary multiplication by 2. The shift module consists of a 2-bit shifter connected after the output of a1w1, and 1-bit shifters connected after the outputs of a0w1 and a1w0 respectively. The outputs are then fed into adders and subtractors to obtain the probabilistic multiplication results for unsigned and signed numbers. The compensated probability multiplication result is expressed by the formula:

[0029] (A·W) s_sto =2 2 a1w1-2 1 a1w0-2 1 a0w1

[0030] (A·W) u_sto =2 2 a1w1+2 1 a1w0+2 1 a0w1

[0031] in,(·) s_sto Represents the result of probability operations on signed numbers, (·) u_sto This represents the result of probability operations on unsigned numbers. The corrected probability multiplication will only have an error in the case of a0=1 and w0=1, with a maximum error of 1.

[0032] Preferably, the error compensation mechanism addresses the issue of sign errors in traditional fine-grained spatial parallel probabilistic multipliers. The error-compensated probabilistic multiplier incorporates a gating mechanism that selectively outputs signed and unsigned numbers, thereby compensating for sign errors. This mechanism uses the selection signal C input to the circuit. in , and the probability multiplication result (A·W) after compensation by the shift module. s_sto and (A·W) u_sto The input gating selects whether the output is a signed or unsigned number. The selected number is used as the output of the error compensation probability multiplier, and then the selected number is input into the overall mixed precision calculation unit for calculation.

[0033] Preferably, the four error-compensated probability multipliers combined with shift circuits and adders to form a 4-bit mixed-precision processing unit means that two 4-bit signed numbers are split into four 2-bit numbers, as expressed by the formula:

[0034] M = (M1M0) bin =2 2 M1+M0

[0035] N = (N1N0) bin =2 2 N1+N0

[0036] Where M and N are two 4-bit signed numbers from the input, M0 and M1 are two 2-bit numbers split from M, and N0 and N1 are two 2-bit numbers split from N, (·) bin Represents the value of the binary field, (M1M0) bin The two's complement representation of the multiplier M is (N1N0). bin The binary two's complement representation of the multiplier N is achieved through shift circuits for each coefficient.

[0037] like Figure 3 As shown, the four 2-bit numbers M1, M0, N1, and N0 are respectively input into four error-compensated probability multipliers. The outputs of the four error-compensated probability multipliers are input into a shift circuit, and the sums are obtained using an adder to form a 4-bit mixed-precision processing unit. The output of the product of M and N is denoted as K. The 4-bit mixed-precision processing unit is expressed by the formula:

[0038] K = M·N = 2 4 (M1·N1) s_sto +2 2 (M1·N0) s_sto +2 2 (M0·N1) s_sto +(M0·N0) u_sto

[0039] Where K is the result of multiplying M and N, (M1·N1) s_sto (M1·N0) s_sto (M0·N1) s_sto (M0·N0) u_sto All are implemented through the error compensation probability multiplier, which is the output of the four error compensation probability multipliers. The coefficients of each item are implemented through a shift circuit.

[0040] Preferably, the four 4-bit mixed-precision processing units, combined with a shift circuit and an adder, form an 8-bit mixed-precision processing unit. The two 8-bit signed numbers are denoted as P and Q, respectively. The 8-bit number P is decomposed into two 4-bit numbers P1 and P0, and the 8-bit number Q is decomposed into two 4-bit numbers Q1 and Q0, as expressed by the formula:

[0041] P = (P1P0) bin

[0042] Q = (Q1Q0) bin

[0043] Where P and Q are two 8-bit signed multipliers, P1 and P0 are two 4-bit numbers decomposed from multiplier P, and Q1 and Q0 are two 4-bit numbers decomposed from multiplier Q, (P1P0) bin Let (Q1Q0) be the two's complement of the multiplier P. bin This is the two's complement of the multiplier Q.

[0044] P1 can be further decomposed into two 2-bit numbers P 11 P 10 P0 can be further decomposed into two 2-bit numbers P 01 P 00 Q1 can be further decomposed into two 2-bit numbers Q. 11 Q 10 Q0 can be further decomposed into two 2-bit numbers Q. 01 Q 00 This can be expressed as a formula:

[0045] P1=(P 11 P 10 ) bin =2 2 P 11 +P 10

[0046] P0=(P 01 P 00 ) bin =2 2 P 01 +P 00

[0047] Q1=(Q 11 Q 10 ) bin =2 2 Q 11 +Q 10

[0048] Q0=(Q 01 Q 00 ) bin =22 Q 01 +Q 00

[0049] Among them, (P) 11 P 10 ) bin This is the two's complement of P1, (P 01 P 00 ) bin For the two's complement of P0, (Q 11 Q 10 ) bin This is the two's complement of Q1, (Q 01 Q 00 ) bin This is the two's complement of Q0, with each coefficient implemented using a shift circuit.

[0050] like Figure 4 As shown, the split 2-bit data P 01 P 00 Q 01 Q 00 The inputs are fed into the four 4-bit mixed-precision processing units, and the outputs are P1Q1, P1Q0, P0Q1, and P0Q0, respectively, which can be expressed by the following formula:

[0051] P1Q1=2 4 (P 11 Q 11 ) s_sto +2 2 (P 11 Q 10 ) s_sto +2 2 (P 10 Q 11 ) s_sto +2 0 (P 10 Q 10 ) u_sto

[0052] P1Q0=2 4 (P 11 Q 01 ) s_sto +2 2 (P 11 Q 00 ) s_sto +2 2 (P 10 Q 01 ) u_sto +2 0 (P 10 Q 00 ) u_sto

[0053] P0Q1=2 4 (P 01 Q 11 ) s_sto +2 2 (P 01 Q 10 ) u_sto +2 2 (P 00 Q 11 ) s_sto +2 0 (P 00 Q 10 ) u_sto

[0054] P0Q0=2 4 (P 01 Q 01 ) u_sto +2 2 (P 01 Q 00 ) u_sto +2 2 (P 00 Q 01 ) u_sto +2 0 (P 00 Q 00 ) u_sto

[0055] Wherein, P1Q1, P1Q0, P0Q1, and P0Q0 are the outputs of the four 4-bit mixed-precision processing units, (·) s_sto Represents the result of probability operations on signed numbers, (·) u_sto This represents the result of a probability operation on unsigned numbers. The terms on the right-hand side of the equals sign are the outputs of the error-compensated probability multiplier in the 4-bit precision mixed-signal unit after passing through a shift circuit. The coefficients of each term are implemented using the shift circuit.

[0056] The calculation results P1Q1, P1Q0, P0Q1, and P0Q0 from the four 4-bit mixed-precision processing units are input into the adder via a shift circuit, outputting the operation result of 8-bit numbers P and Q, which can be expressed by the formula:

[0057] P·Q=2 8 P1Q1+2 4 P1Q0+2 4 P0Q1+P0Q0

[0058] The coefficients are implemented using a shift circuit.

[0059] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0060] 1. This invention provides a hardware acceleration circuit for mixed precision deep neural networks based on probability calculation. It uses an error-compensated probability multiplier as the basic operation unit, so that the maximum error of probability calculation is 1. It selectively outputs signed and unsigned numbers, which can improve the shortcomings of multiple error and sign error in existing fine-grained spatial parallel probability multipliers.

[0061] 2. This invention provides a hardware acceleration circuit for mixed-precision deep neural networks based on probabilistic computation. It uses an error-compensated probabilistic multiplier as the basic operation unit. Four of the error-compensated probabilistic multipliers, combined with a shift circuit and an adder, form a 4-bit mixed-precision processing unit. Compared with existing mixed-precision operation processing units, it saves 32.9% of the area overhead, reduces latency by 18.8%, and reduces power consumption by 59.2%. It can improve the shortcomings of existing mixed-precision operation processing units, such as large area, high latency, and high power consumption.

[0062] 3. This invention provides a hardware acceleration circuit for mixed precision deep neural networks based on probability calculation. It uses an error-compensated probability multiplier as the basic operation unit. Four of the error-compensated probability multipliers are combined with a shift circuit and an adder to form a 4-bit mixed precision processing unit to perform probability calculations on bitstream sequences. This simplifies the structure of existing mixed precision operation processing units and can achieve the beneficial effect of accelerating the probability calculations of deep neural network models. Attached image description:

[0063] Figure 1 This is a schematic diagram of a traditional probability multiplier.

[0064] Figure 2 This is a schematic diagram of an error-compensated probability multiplier.

[0065] Figure 3 This is a structural diagram of a 4-bit mixed-precision processing unit.

[0066] Figure 4 This is a block diagram of a hybrid precision acceleration circuit for deep neural networks based on probability calculation. Detailed Implementation

[0067] The present invention will be further described in detail below with reference to experimental examples and specific embodiments. However, this should not be construed as limiting the scope of the above-mentioned subject matter of the present invention to the following embodiments; all technologies implemented based on the content of the present invention fall within the scope of the present invention.

[0068] Example 1

[0069] This embodiment proposes a hardware acceleration circuit for mixed precision deep neural networks based on probability calculation, including 16 error-compensated probability multipliers, 4 of which are combined with a shift circuit to form a 4-bit mixed precision processing unit, and 4 of which are combined with a shift circuit to form an 8-bit mixed precision processing unit.

[0070] To perform 2-bit precision operations, the binary bitstream is input into the hybrid precision hardware acceleration circuit of the deep neural network based on probability calculation. First, the forward conversion module of the fine-grained spatial parallel probabilistic multiplier converts the binary bitstream sequence into an equally weighted bitstream sequence. The two 2-bit multipliers are denoted as A and W, respectively. A is weighted and extended, and the encoded sequence is represented as follows:

[0071] A = (a1a0) bin =(a1a1a0) sto

[0072] Where a1 and a0 are the two bits of the multiplier A, (·) bin Represents the value of the binary field, (·) sto Represents the numerical value of the probability domain, (a1a0) bin This is the two's complement representation of the multiplier A, (a1a1a0) sto It is a probability sequence representation after weighted expansion encoding.

[0073] W uses uniform encoding, and the encoded sequence is expressed by the formula:

[0074] W = (w1w0) bin =(w1w0w1) sto

[0075] Where w1 and w0 are the two bits of the multiplier W, (w1w0) bin It is the two's complement representation of the multiplier W, (w1w0w1) sto It is a probability sequence representation after uniform encoding. The result of probability multiplication of A and W by the computation module is expressed by the formula:

[0076] A·W=a1w1+a1w0+a0w1

[0077] The calculated equal-weighted bitstream sequence is fed into the backward conversion module to be converted back into a binary bitstream sequence. Then, through the error compensation mechanism, the bitstream sequence is shifted, and the output results are fed into the adder and subtractor respectively to obtain the unsigned and signed number operation results. The compensated probability multiplication result is expressed by the formula:

[0078] (A·W) s_sto =22 a1w1-2 1 a1w0-2 1 a0w1

[0079] (A·W) u_sto =2 2 a1w1+2 1 a1w0+2 1 a0w1

[0080] in,(·) s_sto This represents the result of a signed number probability operation, (·). u_sto This represents the result of an unsigned number probability operation.

[0081] To perform 4-bit precision operations, let M and N be two 4-bit signed input numbers. Then M is split into two 2-bit numbers M1 and M0, and N is split into two 2-bit numbers N1 and N0, as expressed by the formula:

[0082] M = (M1M0) bin =2 2 M1+M0

[0083] N = (N1N0) bin =2 2 N1+N0

[0084] These four 2-bit numbers are input into the four error-compensated probability multipliers, respectively. The output calculation results are input into a shift circuit, and summed using an adder to form a 4-bit mixed-precision coarse-grained processing unit. The result of multiplying M and N can be denoted as K. The probability calculation result of the 4-bit mixed-precision processing unit is expressed by the formula:

[0085] K = M·N = 2 4 (M1·N1) s_sto +2 2 (M1·N0) s_sto +2 2 (M0·N1) s_sto +(M0·N0) u_sto

[0086] Among them, (M1·N1) s_sto (M1·N0) s_sto (M0·N1) s_sto (M0·N0) u_sto All of these are achieved through the error compensation probability multiplier, and the coefficients are achieved through a shift circuit.

[0087] For 8-bit precision arithmetic, the two 8-bit signed input numbers are denoted as P and Q. The 8-bit input P is decomposed into two 4-bit numbers P1 and P0, and the 8-bit input Q is decomposed into two 4-bit numbers Q1 and Q0, as expressed by the formula:

[0088] P = (P1P0) bin

[0089] Q = (Q1Q0) bin

[0090] P1 is further decomposed into two 2-bit numbers P 11 P 10 P0 can be further decomposed into two 2-bit numbers P 01 P 00 Q1 can be further decomposed into two 2-bit numbers Q. 11 Q 10 Q0 can be further decomposed into two 2-bit numbers Q. 01 Q 00 This can be expressed as a formula:

[0091] P1=(P 11 P 10 ) bin =2 2 P 11 +P 10

[0092] P0=(P 01 P 00 ) bin =2 2 P 01 +P 00

[0093] Q1=(Q 11 Q 10 ) bin =2 2 Q 11 +Q 10

[0094] Q0=(Q 01 Q 00 ) bin =2 2 Q 01 +Q 00

[0095] like Figure 3 As shown, the split 2-bit data P 01 P 00 Q 01 Q 00Taking the inputs into the four error-compensated probability multipliers as an example, the outputs are shifted and then input into the adder to form a 4-bit mixed-precision processing unit. Figure 3 The circuits within the four dashed boxes are the four 4-bit mixed-precision processing units, which can be represented by the following formula:

[0096] P1Q1=2 4 (P 11 Q 11 ) s_sto +2 2 (P 11 Q 10 ) s_sto +2 2 (P 10 Q 11 ) s_sto +2 0 (P 10 Q 10 ) u_sto

[0097] P1Q0=2 4 (P 11 Q 01 ) s_sto +2 2 (P 11 Q 00 ) s_sto +2 2 (P 10 Q 01 ) u_sto +2 0 (P 10 Q 00 ) u_sto

[0098] P0Q1=2 4 (P 01 Q 11 ) s_sto +2 2 (P 01 Q 10 ) u_sto +2 2 (P 00 Q 11 ) s_sto +2 0 (P 00 Q 10 ) u_sto

[0099] P0Q0=2 4 (P 01 Q 01 ) u_sto +2 2(P 01 Q 00 ) u_sto +2 2 (P 00 Q 01 ) u_sto +2 0 (P 00 Q 00 ) u_sto

[0100] The calculation results of these four 4-bit mixed-precision processing units are input to the adder via a shift circuit to form one 8-bit mixed-precision processing unit. The probability calculation result is expressed by the formula:

[0101] P·Q=2 8 P1Q1+2 4 P1Q0+2 4 P0Q1+P0Q0

[0102] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A hardware acceleration circuit for mixed-precision deep neural networks based on probabilistic computation, characterized in that, Using an error-compensated probability multiplier as the basic operation unit, four such error-compensated probability multipliers, combined with a shift circuit and an adder, form a 4-bit mixed-precision processing unit. The error-compensated probabilistic multiplier consists of two parts: fine-grained spatial parallel probabilistic multiplication and an error compensation mechanism. The fine-grained spatial parallel probabilistic multiplier includes a forward conversion module, an arithmetic module, and a backward conversion module. It uses weighted extended coding and uniform coding to convert a binary bitstream sequence into an equally weighted bitstream sequence. The error compensation mechanism uses a shift module to compensate for the error of the operation result of the fine-grained spatial parallel probability multiplier by a factor of 1, and designs a gating mechanism to selectively output signed and unsigned numbers to compensate for the error of the operation sign.

2. The hardware acceleration circuit for mixed-precision deep neural networks based on probabilistic computation according to claim 1, characterized in that, The port connection relationship between the fine-grained spatial parallel probabilistic multiplier and the error compensation mechanism. The input to the error compensation probability multiplier is the bits derived from two 2-bit data points, A and W. , , , and a circuit input selection signal The two bits of A are respectively , The two bits of W are , The output is obtained after passing through the fine-grained spatial parallel probability multiplier. , , These three outputs are connected to the error compensation mechanism. The output is then connected to the 2-bit shift circuit in the error compensation mechanism. and The output is then connected to the shift-by-1 circuit in the error compensation mechanism described above to obtain the shifted output. , , The three shifted outputs are connected to adders and subtractors, and the outputs are the probabilistic results of unsigned and signed numbers. and The probability calculation result and In the common input strobe, or Output.

3. The hardware acceleration circuit for mixed-precision deep neural networks based on probabilistic computation according to claim 1, characterized in that, The error compensation mechanism utilizes a shift module to compensate for errors in the computation results of the fine-grained spatial parallel probability multiplier by a factor of 1. The output is then connected to a 2-bit shifter circuit. and Each output is connected to a 1-bit shifter circuit, which feeds the output results into an adder and a subtractor respectively, to obtain the probability calculation results for unsigned and signed numbers. The probability multiplication result after compensation by the shift module is expressed by the following formula: Where A and W are two 2-bit multipliers, , These are the two bits of the multiplier A. , These are the two bits of the multiplier W. This represents the result of probability operations on signed numbers. This represents the result of a probability operation on an unsigned number. , , The output after passing through the shift module is achieved through a shift circuit.

4. The hardware acceleration circuit for mixed-precision deep neural networks based on probabilistic computation according to claim 1, characterized in that, The aforementioned error compensation mechanism incorporates a gating mechanism within the error compensation probability multiplier to selectively output signed and unsigned numbers, compensating for operator errors by selecting the circuit input selection signal. And the probability multiplication result after compensation by the shift module. and The input gating selects whether the output is a signed or unsigned number, and the selected number is used as the output of the error-compensated probability multiplier.

5. The hardware acceleration circuit for mixed-precision deep neural networks based on probabilistic computation according to claim 1, characterized in that, The four error-compensated probability multipliers combined with shift circuits and adders to form a 4-bit mixed-precision processing unit means that two 4-bit signed numbers are split into four 2-bit numbers, as expressed by the formula: Where M and N are two 4-bit signed numbers from the input. and M is split into two 2-bit numbers. and The two 2-bit numbers that split N. Represents the value of the binary field. Represents the multiplier The two's complement of the binary symbol. The binary two's complement representation of the multiplier N is achieved through shift circuits for each coefficient. Will These four 2-bit numbers are respectively input into the four error-compensated probability multipliers. The outputs of the four error-compensated probability multipliers are input into a shift circuit, and summed using an adder to form a 4-bit mixed-precision processing unit. The output of the product of M and N is denoted as K. The 4-bit mixed-precision processing unit is expressed by the formula: Where K is the result of multiplying M and N. , , , All are implemented through the error compensation probability multiplier, which is the output of four error compensation probability multipliers. The coefficients of each item are implemented through a shift circuit.

6. The hardware acceleration circuit for mixed-precision deep neural networks based on probabilistic computation according to claim 1, characterized in that, The four 4-bit mixed-precision processing units, combined with shift circuits and adders, form an 8-bit mixed-precision processing unit. Two 8-bit signed numbers are denoted as P and Q, respectively. The 8-bit number P is decomposed into two 4-bit numbers. , The 8-bit number Q is decomposed into two 4-bit numbers. This can be expressed as a formula: Where P and Q are the two 8-bit signed multipliers of the input. , These are the two 4-bit numbers that the multiplier P is decomposed into. , These are the two 4-bit numbers that the multiplier Q is decomposed into. This is the two's complement of the multiplier P. This is the two's complement of the multiplier Q. in, It can be further decomposed into two 2-bit numbers. It can be further decomposed into two 2-bit numbers. It can be further decomposed into two 2-bit numbers. It can be further decomposed into two 2-bit numbers. This can be expressed as a formula: in, for The two's complement of the binary symbol. for The two's complement of the binary symbol. for The two's complement of the binary symbol. for The binary two's complement is obtained by shifting the coefficients using a shift circuit. The split 2-bit data , , , The inputs are fed into the four 4-bit mixed-precision processing units, and the outputs are respectively Its formula is as follows: in, , , , For the four mentioned The output of the mixed precision processing unit, This represents the result of probability operations on signed numbers. This represents the result of a probability operation on unsigned numbers, with the terms on the right-hand side of the equation being... The output of the error-compensated probability multiplier in the mixed-precision processing unit is the output after passing through a shift circuit, where the coefficients of each term are implemented using the shift circuit. The calculation results of the four 4-bit mixed precision processing units , , , The input is shifted to the adder, and the result of the operation between the 8-bit numbers P and Q is output, which can be expressed by the formula: The coefficients are implemented using a shift circuit.

Images