An enhanced SiC substrate GaN power electronic device

Abstract

This invention discloses an enhanced SiC substrate GaN power electronic device, comprising: a substrate and a buffer layer, the buffer layer including an isolation trench, the buffer layer being divided into a first region and a second region by the isolation trench; in the first region, a first channel layer, a first barrier layer, a first passivation layer, a first isolation layer and an active layer are disposed on the buffer layer, the active layer comprising a drift region, a lead-out region and a source region, a drain region comprising the drift region, a first source electrode comprising the upper surface of the lead-out region and the source region, a first drain electrode comprising the upper surface of the drain region, and a first gate electrode comprising the two; in the second region, a second channel layer, a second barrier layer, a second passivation layer and a second isolation layer are sequentially disposed on the buffer layer, a second source electrode and a second drain electrode comprising the second isolation layer, and a second gate electrode comprising the two; the first drain electrode and the second source electrode are electrically connected by a first metal interconnect, and the first source electrode and the second gate electrode are electrically connected by a second metal interconnect. This invention can improve device performance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to an enhanced SiC substrate GaN power electronic device. Background Technology

[0002] To meet the demands of future power electronic systems, wide-bandgap semiconductor materials, represented by gallium nitride (GaN), are receiving increasing attention, bringing new opportunities for the development of power electronic devices. Compared with Si, GaN exhibits comprehensive advantages, with a bandgap of 3.4 eV, three times that of Si, and better voltage withstand characteristics and higher current density. In addition, GaN materials show better properties in terms of electron mobility, saturation drift velocity, and dielectric constant. These advantages make GaN-based high electron mobility transistors (HEMTs) a mainstay in future high-voltage and high-frequency applications.

[0003] Furthermore, research on the fabrication of enhancement-mode GaN power electronic devices is essential for practical applications. A commonly used method involves employing a Cascode structure composed of a low-voltage enhancement-mode Si MOS field-effect transistor and a high-voltage depletion-mode GaN power electronic device, such as... Figure 1 As shown; however, current mainstream chip-level integration technologies for GaN power electronic devices based on Cascode structures have low integration density and large area, which cannot meet the miniaturization and high integration requirements of today's electronic systems. There is a need to move from chip-level integration to system integration with higher integration density and complexity. Monolithic integration integrates various functional devices on a single chip, eliminating the need for chip packaging and effectively solving the problem of significant parasitic effects caused by long interconnect distances. Currently, among the methods for achieving monolithic heterogeneous integration of Si and GaN materials, transfer printing technology has relatively low wafer surface flatness and low matching degree of thermodynamic and lattice parameters between the substrate and epitaxial layer materials, reducing the process difficulty and cost of monolithic integration. Since performance optimization of high-voltage depletion-type GaN power electronic devices is crucial to improving the overall performance of Cascode devices, a solution is urgently needed to address some of the remaining problems of high-voltage depletion-type GaN power electronic devices, such as low breakdown field strength, performance degradation at high power density, and dynamic on-resistance degradation under high voltage. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides an enhanced SiC substrate GaN power electronic device. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] In a first aspect, the present invention provides an enhanced SiC substrate GaN power electronic device, comprising:

[0006] A substrate and a buffer layer located on the substrate, the buffer layer including an isolation trench, the buffer layer being divided into a first region and a second region by the isolation trench along a direction perpendicular to the substrate;

[0007] In the first region, a first channel layer, a first barrier layer, a first passivation layer, a first isolation layer, and an active layer are sequentially disposed on the buffer layer. A drift region, a lead-out region, and a source region are disposed on the upper surface of the active layer. The lead-out region and the source region are arranged adjacent to each other, and the drift region and the source region are arranged alternately. A drain region is disposed on the upper surface of the drift region. A first source electrode is disposed on the upper surface of the lead-out region and the source region, and a first drain electrode is disposed on the upper surface of the drain region. A gate dielectric layer is disposed between the first source electrode and the first drain electrode, and a first gate electrode is disposed on the gate dielectric layer.

[0008] In the second region, a second channel layer, a second barrier layer, a second passivation layer and a second isolation layer are sequentially disposed on the buffer layer. A second source and a second drain are disposed on the second isolation layer. The second source and the second drain extend to the upper surface of the second barrier layer. A second gate is disposed between the second source and the second drain. The second gate extends to the upper surface of the second passivation layer.

[0009] The first drain and the second source are electrically connected through a first metal interconnect line, and the first source and the second gate are electrically connected through a second metal interconnect line.

[0010] The beneficial effects of this invention are:

[0011] This invention provides an enhanced SiC substrate GaN power electronic device. On one hand, it utilizes an AlN / SiC substrate epitaxial material, which, compared to traditional GaN buffer layers, has a larger bandgap and higher breakdown voltage; fewer traps affecting dynamic on-resistance degradation, resulting in less dynamic resistance degradation under high voltage; better heat dissipation and high thermal stability; and compared to traditional silicon substrates, it can share the breakdown voltage of the epitaxial layer, improving the device's breakdown voltage, and its thermal conductivity is also superior. On the other hand, it achieves monolithic heterogeneous integration of Si MOS field-effect transistors and SiN / AlGaN / GaN / AlN on SiC HEMT through transfer printing, realizing a Cascode structure enhanced power electronic device with lower parasitic parameters, which is beneficial for improving the device's operating frequency and efficiency.

[0012] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0013] Figure 1This is a schematic diagram of a conventional Cascode structure composed of a low-voltage enhancement-mode Si MOS field-effect transistor and a high-voltage depletion-mode GaN power electronic device, provided by an embodiment of the present invention.

[0014] Figure 2 This is a schematic diagram of an enhanced SiC substrate GaN power electronic device provided in an embodiment of the present invention;

[0015] Figure 3 This is a top view of an enhanced SiC substrate GaN power electronic device provided in an embodiment of the present invention;

[0016] Figure 4 This is a schematic diagram of a method for fabricating an enhanced SiC substrate GaN power electronic device according to an embodiment of the present invention;

[0017] Figure 5 This is a schematic diagram comparing the breakdown characteristics of a device with an AlN buffer layer and a device with a conventional iron-doped GaN buffer layer, provided in an embodiment of the present invention.

[0018] Figure 6 This is a schematic diagram comparing the dynamic resistance degradation of a device with an AlN buffer layer and a device with a conventional iron-doped GaN buffer layer under off-state high-voltage stress conditions, as provided in an embodiment of the present invention.

[0019] Figure 7 This is a schematic diagram comparing the output current dependence on temperature between a device with an AlN buffer layer and a device with a traditional iron-doped GaN buffer layer provided in this embodiment of the invention. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0021] To address the shortcomings of existing technologies, this invention provides an enhanced SiC substrate GaN power electronic device. The high-resistivity SiC substrate has a small lattice mismatch with GaN, resulting in better epitaxial GaN quality and improved voltage withstand and heat dissipation characteristics. Compared with traditional GaN buffer layers, the AlN buffer layer has a larger bandgap, fewer traps affecting dynamic on-resistance degradation, and better heat dissipation, enabling the device to achieve high breakdown voltage, high thermal stability, and low dynamic resistance degradation.

[0022] Please see Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of an enhanced SiC substrate GaN power electronic device provided in an embodiment of the present invention. Figure 3This is a top view of an enhanced SiC substrate GaN power electronic device provided in an embodiment of the present invention. The enhanced SiC substrate GaN power electronic device provided by the present invention includes:

[0023] A substrate and a buffer layer located on the substrate, the buffer layer including an isolation trench, the buffer layer being divided into a first region and a second region by the isolation trench along a direction perpendicular to the substrate;

[0024] In the first region, a first channel layer, a first barrier layer, a first passivation layer, a first isolation layer, and an active layer are sequentially disposed on the buffer layer. A drift region, a lead-out region, and a source region are disposed on the upper surface of the active layer. The lead-out region and the source region are arranged adjacent to each other, and the drift region and the source region are arranged alternately. A drain region is disposed on the upper surface of the drift region. A first source electrode is disposed on the upper surface of the lead-out region and the source region, and a first drain electrode is disposed on the upper surface of the drain region. A gate dielectric layer is disposed between the first source electrode and the first drain electrode, and a first gate electrode is disposed on the gate dielectric layer.

[0025] In the second region, a second channel layer, a second barrier layer, a second passivation layer and a second isolation layer are sequentially disposed on the buffer layer. A second source and a second drain are disposed on the second isolation layer. The second source and the second drain extend to the upper surface of the second barrier layer. A second gate is disposed between the second source and the second drain. The second gate extends to the upper surface of the second passivation layer.

[0026] The first drain and the second source are electrically connected through a first metal interconnect line, and the first source and the second gate are electrically connected through a second metal interconnect line.

[0027] For details, please continue to see Figure 2 and Figure 3 As shown, the enhanced SiC substrate GaN power electronic device provided in this embodiment includes a substrate, an AlN buffer layer on the substrate, a first i-GaN channel layer and a second i-GaN channel layer on the AlN buffer layer, and an isolation trench between the first i-GaN channel layer and the second i-GaN channel layer, extending into the AlN buffer layer; wherein...

[0028] The first i-GaN channel layer is provided with a first AlGaN barrier layer, a first SiN passivation layer, a first SiN isolation layer, and a Si active layer from bottom to top. The Si active layer is provided with an N- drift region, an N+ source region, and a P+ body lead-out region. The N- drift region is provided with an N+ drain region. The Si active layer is covered with a gate dielectric layer.

[0029] A first source, a first gate, and a first drain are sequentially arranged laterally on the gate dielectric layer; the first source extends through the gate dielectric layer to the Si active layer and is located on the N+ source region and the P+ body lead-out region; the first drain extends through the gate dielectric layer to the Si active layer and is located on the N+ drain region; the above structure located on this side of the first i-GaN channel layer forms a silicon n-channel enhancement-mode laterally diffused metal-oxide-semiconductor field-effect transistor.

[0030] From bottom to top, a second AlGaN barrier layer, a second SiN passivation layer, and a second SiN isolation layer are sequentially arranged on the second i-GaN channel layer. A second source, a second gate, and a second drain are sequentially arranged laterally on the second SiN isolation layer. The second source and the second drain extend through the second SiN isolation layer and the second SiN passivation layer to the second AlGaN barrier layer, and the second gate extends through the second SiN isolation layer to the second SiN passivation layer. The above structure on this side of the second i-GaN channel layer forms an n-channel depletion-type SiC-based GaN high electron mobility transistor.

[0031] An isolation trench is covered with a gate dielectric layer. A second SiN passivation layer, a second source, a second gate, and a second drain are also covered with gate dielectric layers, and vias are formed in the gate dielectric layers on the second source, second gate, and second drain. Alternatively, the gate dielectric layer can be understood as covering the exposed stepped structure of the device, the side surface of the first trench layer, the side surface of the first barrier layer, the side surface of the first isolation layer, the side surface of the active layer and its upper surface, the isolation trench, the side surface of the second channel layer, the side surface of the second barrier layer, the side surface of the second passivation layer, the side surface of the second isolation layer and its upper surface, and the upper surfaces of the second source, second gate, and second drain portions.

[0032] The first drain and the second source are electrically connected via a first metal interconnect, and the first source and the second gate are electrically connected via a second metal interconnect. The edge of the Cascode device has a stepped structure that extends from the surface of the Cascode device into the AlN buffer layer. This completes the fabrication of the Cascode structure enhancement-type power electronic device based on the monolithic heterogeneous integration of Si MOS field-effect transistors and SiN / AlGaN / GaN / AlN on SiC HEMT.

[0033] The device of this invention grows an AlGaN / GaN heterojunction material by epitaxially growing AlN material on a high-resistivity SiC substrate as a buffer layer, and realizes an enhancement-mode power electronic device by monolithically heterogeneously integrating a Si MOS field-effect transistor with a SiN / AlGaN / GaN / AlN on SiC HEMT. Therefore, it has the following advantages compared with the prior art:

[0034] 1. Using AlN / SiC substrate epitaxial material, it has a larger bandgap and higher breakdown voltage compared to traditional GaN buffer layers; fewer traps affecting dynamic on-resistance degradation, and less dynamic resistance degradation under high voltage; better heat dissipation and high thermal stability; compared to traditional silicon substrates, it can share the breakdown voltage of the epitaxial layer, improve the breakdown voltage of the device, and its thermal conductivity is also better.

[0035] 2. By transferring Si MOS field-effect transistors and SiN / AlGaN / GaN / AlN on SiC HEMT monolithic heterogeneous integration, and realizing Cascode structure enhancement power electronic devices, which have lower parasitic parameters, it is beneficial to improve the operating frequency and efficiency of the devices.

[0036] It should be noted that, Figure 2 The embodiments shown are only schematic representations of the positional relationships of the various film layers in the device and do not represent their actual dimensions; Figure 3 In the embodiment shown, the first and second metal interconnects are only shown to illustrate the connection relationship and do not represent their actual manufacturing positions. They can be set according to actual needs.

[0037] In an optional embodiment of the present invention, the buffer layer further includes stepped structures on both sides, and a gate dielectric layer is provided on both the stepped structures and the isolation groove.

[0038] In an optional embodiment of the present invention, the active layer is disposed on the first isolation layer to form a monolithic heterogeneous integration; it can be understood that the Si active layer is printed on the first SiN isolation layer to form a monolithic heterogeneous integration of Si MOS field-effect transistor and SiN / AlGaN / GaN / AlN on SiC HEMT.

[0039] In an optional embodiment of the present invention, the first gate is made of polysilicon, the first source and the first drain are both made of aluminum, and the first source and the first drain form an ohmic contact with the active layer.

[0040] In an optional embodiment of the present invention, the thickness of the active layer is 100-300 nm along the direction perpendicular to the substrate, the thickness of the first gate is 100-200 nm, and the thickness of the first source and the first drain are both 30-100 nm.

[0041] In an optional embodiment of the present invention, the thickness of the active layer is 100–300 nm along a direction perpendicular to the substrate.

[0042] In an optional embodiment of the present invention, the gate dielectric layer is made of aluminum oxide, and the thickness of the gate dielectric layer is 15-30 nm along the direction perpendicular to the substrate.

[0043] In an optional embodiment of the present invention, the material of the second gate includes a stack of nickel and gold, and the materials of the second source and the second drain are both stacks of titanium, aluminum, nickel and gold. The second source and the second drain both form ohmic contacts with the second barrier layer.

[0044] In an optional embodiment of the present invention, the thickness of the second source and the second drain are both 200-300 nm along the direction perpendicular to the substrate, and the thickness of the second gate is 120-250 nm.

[0045] In an optional embodiment of the present invention, the thickness of the substrate is 300-800 μm and the thickness of the buffer layer is 20-500 nm along the direction perpendicular to the substrate.

[0046] In an optional embodiment of the present invention, the thickness of the first i-GaN channel layer and the second i-GaN channel layer are both 100 to 300 nm along the direction perpendicular to the substrate.

[0047] The thickness of both the first AlGaN barrier layer and the second AlGaN barrier layer is 15–30 nm.

[0048] The thickness of both the first SiN passivation layer and the second SiN passivation layer is 15–20 nm.

[0049] The thickness of both the first SiN isolation layer and the second SiN isolation layer is 150–200 nm.

[0050] The thickness of both the first and second metal interconnects is 200–300 nm.

[0051] Based on the same inventive concept Figure 4 This is a schematic diagram illustrating the fabrication of an enhanced SiC substrate GaN power electronic device according to an embodiment of the present invention. The present invention also provides a method for fabricating an enhanced SiC substrate GaN power electronic device, used to fabricate the enhanced SiC substrate GaN power electronic device provided in the above embodiments of the present invention. Please refer to the above embodiments for device examples, which will not be repeated here. The fabrication method includes:

[0052] S1. Preparation of SiN / AlGaN / GaN / AlN / SiC materials;

[0053] A SiN / AlGaN / GaN / AlN / SiC material was obtained by sequentially epitaxially forming an AlN buffer layer, an i-GaN channel layer, an AlGaN barrier layer, and a SiN passivation layer on a SiC substrate using metal-organic chemical vapor deposition (MOCVD). Figure 4 As shown in f.

[0054] The thickness of the SiC substrate is 300–800 μm; the thickness of the AlN buffer layer is 20–500 nm; the thickness of the i-GaN channel layer is 100–300 nm; the thickness of the AlGaN barrier layer is 15–30 nm; and the thickness of the SiN passivation layer is 15–20 nm.

[0055] S2, depositing a SiN isolation layer;

[0056] A SiN isolation layer was deposited on the SiN / AlGaN / GaN / AlN / SiC material prepared in S1 using a low-pressure chemical vapor deposition process; the thickness of the SiN isolation layer was 150–200 nm. Figure 4 As shown in g.

[0057] S3. Prepare the SOI wafer to obtain the single-crystal silicon thin film product to be transferred;

[0058] The specific preparation process is as follows:

[0059] S3.1. Photolithography and reactive ion etching processes are used to form single-crystal silicon thin film islands on SOI wafers;

[0060] S3.2. Using a wet etching process, the product obtained in S3.1 is placed in a 49% HF solution to etch away the buried oxide layer that is not covered by the monocrystalline silicon thin film islands.

[0061] S3.3. Anchor points are prepared at the edge of the monocrystalline silicon thin film using photolithography to prevent displacement and detachment of the monocrystalline silicon thin film after the buried oxide layer is completely etched.

[0062] S3.4. Using a wet etching process, the product obtained in S3.3 is immersed in a 49% HF solution to completely etch the buried oxide layer, causing the single-crystal silicon thin film to fall onto the SOI wafer substrate, thus obtaining the single-crystal silicon thin film product to be transferred; Figure 4 a~4e.

[0063] S4. Transfer the single-crystal silicon thin film product to be transferred onto the product prepared in S2;

[0064] Using transfer printing technology, the single-crystal silicon thin film to be transferred is transferred onto the product prepared in step S2 to form a Si active layer, with the Si active layer located on one side of the product prepared in step S2. The transfer process is as follows:

[0065] S4.1 The product prepared in S2 is placed in acetone, anhydrous ethanol and deionized water for ultrasonic cleaning in sequence, and then dried with a nitrogen gun.

[0066] S4.2. Solid polydimethylsiloxane PDMS is bonded to an SOI wafer with the buried oxide layer etched away, and then the two are separated at a speed of 10 cm / s so that the single crystal silicon film adheres to the polydimethylsiloxane PDMS.

[0067] S4.3 Solid polydimethylsiloxane (PDMS) with a single-crystal silicon thin film adhered to it is bonded to the product prepared in S2. The two are then separated at a speed of 1 mm / s to allow the single-crystal silicon thin film to adhere to the product prepared in S2, completing the transfer of the single-crystal silicon thin film and forming a Si active layer on the product prepared in S2. The thickness of the Si active layer is 100–300 nm. Figure 4 As shown in h.

[0068] S5, Isolation groove etching;

[0069] An isolation trench is etched to the AlN buffer layer on one side of the Si active layer, and Si / SiN / AlGaN / GaN / AlN islands and SiN / AlGaN / GaN / AlN islands are formed on both sides of the isolation trench; the depth of the isolation trench is 600-700 nm.

[0070] In a Si / SiN / AlGaN / GaN / AlN island, the i-GaN channel layer, AlGaN barrier layer, and SiN passivation layer are respectively the first i-GaN channel layer, the first AlGaN barrier layer, the first SiN passivation layer, and the first SiN isolation layer; in another SiN / AlGaN / GaN / AlN island, the i-GaN channel layer, AlGaN barrier layer, and SiN passivation layer are respectively the second i-GaN channel layer, the second AlGaN barrier layer, the second SiN passivation layer, and the second SiN isolation layer. Figure 4 As shown in i.

[0071] S6, Table surface etching;

[0072] Mesa etching is performed on the edges of the product prepared by S5 to form a stepped structure extending to the AlN buffer layer. When multiple devices are used simultaneously, the stepped structure can isolate the devices, so that failure of one device will not affect the normal operation of other devices. The mesa etching depth is 600-700 nm; Figure 4 As shown in j.

[0073] S7, N-drift region in Si active layer forming Si / SiN / AlGaN / GaN / AlN islands;

[0074] Phosphorus ions were implanted into the Si active layer of Si / SiN / AlGaN / GaN / AlN islands using an ion implantation process, with an implantation dose of 2 × 10⁻⁶. 13 cm -2The injected energy is 25 keV, forming an N-drift region; such as Figure 4 As shown in k.

[0075] S8, N+ source / drain regions in the Si active layer that forms Si / SiN / AlGaN / GaN / AlN islands;

[0076] Phosphorus ions were implanted into the Si active layer of Si / SiN / AlGaN / GaN / AlN islands using an ion implantation process, with an implantation dose of 3 × 10⁻⁶. 15 cm -2 The injected energy is 30keV, forming the N+ source region and the N+ drain region within the N- drift region; such as Figure 4 As shown in l.

[0077] S9, P+ bulk extraction region in the Si active layer that forms Si / SiN / AlGaN / GaN / AlN islands;

[0078] Boron ions were implanted into the Si active layer of Si / SiN / AlGaN / GaN / AlN islands using an ion implantation process, with an implantation dose of 3 × 10⁻⁶. 15 cm -2 The injection energy was 30 keV, forming a P+ body extraction region. Under a nitrogen atmosphere, the product obtained from S9 was subjected to rapid thermal annealing at 1000℃ for 30 seconds to simultaneously activate the impurities from the three injections and repair the lattice damage caused by the injection. Figure 4 As shown in m.

[0079] Source and drain region dielectric etching of S10, SiN / AlGaN / GaN / AlN islands;

[0080] Using photolithography and reactive ion dry etching processes, the second SiN isolation layer and the second SiN passivation layer at corresponding positions on the source and drain regions of the SiN / AlGaN / GaN / AlN islands are etched away; for example... Figure 4 As shown in n.

[0081] S11, Prepare the second source / drain electrode;

[0082] The source and drain metal regions on the SiN / AlGaN / GaN / AlN islands were defined using photolithography. Electron beam evaporation was then used to sequentially deposit 20 nm thick titanium, 140 nm thick aluminum, 55 nm thick nickel, and 45 nm thick gold metal to form the second source and drain, respectively. Annealing was then performed at 850 °C in a nitrogen atmosphere for 30 s, ensuring that both the second source and drain formed ohmic contacts with the second AlGaN barrier layer. Figure 4 As shown in o.

[0083] Dielectric etching of the gate region of S12, SiN / AlGaN / GaN / AlN islands;

[0084] The second SiN isolation layer at the corresponding position on the gate region of the SiN / AlGaN / GaN / AlN island is etched away using photolithography and reactive ion dry etching processes; for example... Figure 4 As shown in p.

[0085] S13, Prepare the second gate;

[0086] The gate metal region on the SiN / AlGaN / GaN / AlN island is defined using photolithography. A 50nm thick layer of nickel metal and a 200nm thick layer of gold metal are sequentially deposited using electron beam evaporation to form the second gate. Figure 4 As shown in q.

[0087] S14, Gate dielectric layer growth;

[0088] Aluminum oxide (ANO) was deposited on the surface of the product prepared by S13 under a nitrogen atmosphere using atomic layer deposition (ALD) to form a gate dielectric layer; the thickness of the gate dielectric layer was 20 nm. Figure 4 As shown in r.

[0089] S15, Prepare the first gate;

[0090] The gate metal region on the Si / SiN / AlGaN / GaN / AlN island is defined using photolithography. A 200nm thick polysilicon layer is deposited on the gate dielectric layer of the Si / SiN / AlGaN / GaN / AlN island using low-pressure chemical vapor deposition to form the first gate. Figure 4 As shown in s.

[0091] Source and drain region dielectric etching of S16, Si / SiN / AlGaN / GaN / AlN islands;

[0092] The gate dielectric layer at corresponding positions on the source and drain regions of Si / SiN / AlGaN / GaN / AlN islands is etched away using photolithography and inductively coupled plasma etching processes; for example... Figure 4 As shown in t.

[0093] S17. Prepare the first source and drain electrodes;

[0094] The source and drain metal regions on the Si / SiN / AlGaN / GaN / AlN islands were defined using photolithography. A 100nm thick layer of aluminum metal was deposited using electron beam evaporation to form the first source and first drain. Annealing was then performed at 400℃ in a nitrogen atmosphere for 60s, ensuring ohmic contacts between the first source and first drain and their corresponding source and drain regions. Figure 4 As shown in u.

[0095] S18, Etching and opening of the gate dielectric layer;

[0096] Using photolithography and inductively coupled plasma etching processes, portions of the gate dielectric layer covering the second gate, second source, and second drain are etched away to form vias, thereby exposing the second gate, second source, and second drain. Figure 4 As shown in v.

[0097] S19. Preparation of interconnect metals;

[0098] Using photolithography and electron beam evaporation processes, a 50nm thick layer of nickel metal and a 200nm thick layer of gold metal are sequentially deposited on the gate dielectric layer to form a first metal interconnect, thereby forming a metal interconnect between the first source and the second gate. Then, a 50nm thick layer of nickel metal and a 200nm thick layer of gold metal are sequentially deposited on the gate dielectric layer to form a second metal interconnect, thereby forming a metal interconnect between the first drain and the second source, resulting in an enhanced SiC substrate GaN power electronic device. Figure 4 As shown in w.

[0099] In an optional embodiment of the present invention, the beneficial effects of the enhanced SiC substrate GaN power electronic device provided in the above embodiments of the present invention are verified through simulation experiments. Please refer to [link to relevant documentation]. Figures 5-7 , Figure 5 This is a schematic diagram comparing the breakdown characteristics of a device with an AlN buffer layer and a device with a conventional iron-doped GaN buffer layer, provided in an embodiment of the present invention. Figure 6 This is a schematic diagram comparing the dynamic resistance degradation of a device with an AlN buffer layer and a device with a conventional iron-doped GaN buffer layer under off-state high-voltage stress conditions, as provided in an embodiment of the present invention. Figure 7 This is a schematic diagram comparing the output current dependence on temperature between a device with an AlN buffer layer and a device with a conventional iron-doped GaN buffer layer provided in this embodiment of the invention. The device with the AlN buffer layer has a breakdown voltage >1600V with a gate-drain spacing of 18μm, and its dynamic on-resistance at 1200V degrades by less than 10% compared to its static state. In contrast, the device with a conventional iron-doped GaN buffer layer has a breakdown voltage <1000V with a gate-drain spacing of 18μm, and its dynamic on-resistance at 900V degrades by more than 100% compared to its static state. Furthermore, the saturation current density of the device decreases significantly with increasing temperature, indicating poor thermal stability. Therefore, the device provided by this invention has superior performance.

[0100] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0101] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0102] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An enhanced SiC substrate GaN power electronic device, characterized by, The application relates to a semiconductor device, which comprises a substrate and a buffer layer on the substrate, the buffer layer comprising an isolation groove, the buffer layer being divided into a first region and a second region by the isolation groove in a direction perpendicular to the substrate; wherein the material of the substrate is SiC, and the material of the buffer layer is AlN. In the first region, a first channel layer, a first barrier layer, a first passivation layer, a first isolation layer and an active layer are sequentially arranged on the buffer layer, a drift region, a lead-out region and a source region are arranged on the upper surface of the active layer, the lead-out region is arranged in connection with the source region, the drift region is arranged in separation from the source region, a drain region is arranged on the upper surface of the drift region, a first source electrode is arranged on the upper surface of the lead-out region and the source region, a first drain electrode is arranged on the upper surface of the drain region, a gate dielectric layer is arranged between the first source electrode and the first drain electrode, and a first gate electrode is arranged on the gate dielectric layer. In the second region, a second channel layer, a second barrier layer, a second passivation layer and a second isolation layer are sequentially arranged on the buffer layer, a second source electrode and a second drain electrode are arranged on the second isolation layer, the second source electrode and the second drain electrode extend to the upper surface of the second barrier layer, a second gate electrode is arranged between the second source electrode and the second drain electrode, and the second gate electrode extends to the upper surface of the second passivation layer. The first drain electrode is electrically connected to the second source electrode through a first metal interconnection line, and the first source electrode is electrically connected to the second gate electrode through a second metal interconnection line. Both sides of the buffer layer further comprise a step structure, and the gate dielectric layer is arranged on the step structure and the isolation groove.

2. The enhanced SiC substrate GaN power electronic device of claim 1, wherein, The material of the first gate electrode is polysilicon, the materials of the first source electrode and the first drain electrode are both aluminum, and the first source electrode and the first drain electrode both form ohmic contact with the active layer.

3. The enhanced SiC substrate GaN power electronic device of claim 1, wherein, In a direction perpendicular to the substrate, the thickness of the active layer is 100-300 nm, the thickness of the first gate electrode is 100-200 nm, and the thickness of the first source electrode and the first drain electrode is both 30-100 nm.

4. The enhanced SiC substrate GaN power electronic device of claim 1, wherein, In a direction perpendicular to the substrate, the thickness of the active layer is 100-300 nm.

5. The enhanced SiC substrate GaN power electronic device of claim 1, wherein, The material of the gate dielectric layer is aluminum oxide, and the thickness of the gate dielectric layer is 15-30 nm in a direction perpendicular to the substrate.

6. The enhanced SiC substrate GaN power electronic device of claim 1, wherein, The material of the second gate electrode comprises laminated nickel and gold, the materials of the second source electrode and the second drain electrode both comprise laminated titanium, aluminum, nickel and gold, and the second source electrode and the second drain electrode both form ohmic contact with the second barrier layer.

7. The enhanced SiC substrate GaN power electronic device of claim 1, wherein, In a direction perpendicular to the substrate, the thickness of the second source electrode and the second drain electrode is both 200-300 nm, and the thickness of the second gate electrode is 120-250 nm.

8. The enhanced SiC substrate GaN power electronic device of claim 1, wherein, In a direction perpendicular to the substrate, the thickness of the substrate is 300-800 mu m, and the thickness of the buffer layer is 20-500 nm.

9. The enhanced SiC substrate GaN power electronic device of claim 1, wherein, ​

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