Backside deep trench isolation structure for suppressing leakage

Abstract

A backside deep trench isolation structure for inhibiting leakage. A pixel array substrate includes a semiconductor substrate including a pixel array, a first side, and a second side opposite the first side; a guard ring region in the semiconductor substrate formed of doped semiconductor, enclosing the pixel array, and extending from the first side into the semiconductor substrate; and a peripheral region in the semiconductor substrate and enclosing the guard ring region. The peripheral region includes at least one device and a deep trench isolation (DTI) structure region disposed between the guard ring region and the at least one device and proximate the second side of the semiconductor substrate. The DTI structure region is configured to block a current path between a P-N junction in the guard ring region and the at least one device.

Description

Technical Field

[0001] This disclosure generally relates to image sensors, and specifically, but not exclusively, to complementary metal-oxide-semiconductor (CMOS) image sensors. Background Technology

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, surveillance cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is expected that their functionality and performance metrics will be enhanced in as many ways as possible (e.g., resolution, power consumption, dynamic range) through device architecture design and image acquisition and processing. The technologies used to manufacture image sensors continue to evolve rapidly. For example, the demand for higher resolution and lower power consumption has encouraged further miniaturization and integration of these devices.

[0003] A typical image sensor operates in response to incident image light from an external scene. The image sensor comprises an array of pixels having portions that absorb incident image light and generate image charge upon absorption. The image charge generated by the pixel light can be measured as an analog output image signal on a bit line that varies according to the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out as an analog image signal from the bit line and converted into a digital value to produce a digital image (e.g., image data) representing the external scene. The analog image signal on the bit line is coupled to a readout circuit that includes an input stage with analog-to-digital converter (ADC) circuitry to convert those analog image signals from the pixel array into digital image signals. Summary of the Invention

[0004] In one aspect, this disclosure relates to a pixel array substrate comprising: a semiconductor substrate including a pixel array, a first side and a second side opposite to the first side; a guard ring region formed of doped semiconductor in the semiconductor substrate, enclosing the pixel array and extending from the first side into the semiconductor substrate; and a peripheral region in the semiconductor substrate enclosing the guard ring region, wherein the peripheral region includes: at least one device; and a deep trench isolation (DTI) structure region disposed between the guard ring region and the at least one device and adjacent to the second side of the semiconductor substrate, wherein the DTI structure region is configured to block a current path between a PN junction in the guard ring region and the at least one device.

[0005] In another aspect, this disclosure relates to a pixel array substrate comprising: a semiconductor substrate including a pixel array, a first side and a second side opposite to the first side, wherein the pixel array includes: a plurality of photodiodes; and a first deep trench isolation (DTI) structure region disposed adjacent to the second side of the semiconductor substrate, wherein the first DTI structure region includes a first plurality of DTI structures; a guard ring region on the semiconductor substrate, enclosing the pixel array and extending from the first side into the semiconductor substrate; and a peripheral region in the semiconductor substrate and enclosing the guard ring, wherein the peripheral region includes: at least one device; and a second DTI structure region disposed between the guard ring region and the at least one device and adjacent to the second side of the semiconductor substrate, wherein the first DTI structure region is configured to isolate each of the plurality of photodiodes in the semiconductor substrate, and wherein the second DTI structure region is configured to block a current path between the PN junction guard ring in the guard ring region and the at least one device.

[0006] In another aspect, this disclosure relates to an imaging system comprising: a semiconductor substrate including a pixel array, a first side, and a second side opposite to the first side; a guard ring region enclosing the pixel array in the semiconductor substrate; and a peripheral region in the semiconductor substrate enclosing the guard ring region, wherein the peripheral region includes: at least one device including a doped region; a deep trench isolation (DTI) structure disposed between the guard ring region and the at least one device and adjacent to the second side of the semiconductor substrate; and a blanket-covered deep doped well disposed adjacent to the second side of the semiconductor substrate, extending across the pixel array, the guard ring region, and the peripheral region, wherein the doped region extends from the first side and contacts the blanket-covered deep doped well, wherein the DTI structure is configured to extend through the blanket-covered deep doped well, thereby dividing the blanket-covered deep doped well into a first sub-doped well portion extending across the peripheral region and a second sub-doped well portion extending across the guard ring region, and blocking a current path between a PN junction in the guard ring region and the doped region of the at least one device. Attached Figure Description

[0007] The following figures illustrate non-limiting and non-exhaustive embodiments of this disclosure, wherein the same reference numerals refer to the same parts throughout the various views unless otherwise specified.

[0008] Figure 1 This describes an example of an imaging system based on the teachings of this disclosure.

[0009] Figure 2 This illustration shows a partial cross-sectional schematic diagram of a pixel array substrate according to the teachings of this disclosure.

[0010] Figure 3A The diagram at point C illustrates a top-down view of an example pixel array substrate according to the teachings of this disclosure.

[0011] Throughout the various views of the drawings, corresponding reference symbols indicate the corresponding components. Those skilled in the art will understand that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be enlarged relative to other elements to aid in an improved understanding of the various embodiments of this disclosure. Furthermore, common but well-known elements that are useful or necessary in commercially viable embodiments are generally not depicted to facilitate a more intuitive understanding of these various embodiments of this disclosure. Detailed Implementation

[0012] Examples of pixel array substrates with back-side deep trench isolation structure regions that provide reduced current leakage are disclosed. Numerous specific details are set forth in the following description to provide a thorough understanding of the examples. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of these specific details or with other methods, components, materials, etc. In other examples, well-known structures, materials, or operations have not been shown or described in detail to avoid ambiguity regarding certain aspects.

[0013] Throughout this specification, the reference to "an example" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one instance of this disclosure. Therefore, the phrases "in an example" or "in an embodiment" appearing in various places throughout this specification do not necessarily refer to the same example. Furthermore, a particular feature, structure, or characteristic may be combined in any suitable manner in one or more examples.

[0014] For ease of description, spatial relative terms such as “below,” “under,” “above,” “under,” “above,” “top,” “bottom,” “left,” “right,” “center,” “middle,” etc., may be used herein to describe the relationship of one element or feature to another element(s), as illustrated in the figures. It will be understood that, in addition to the orientations depicted in the figures, the spatial relative terms are intended to also cover different orientations of the device during use or operation. For example, if the device in the figures is rotated or flipped, then an element described as “below,” “under,” or “below other elements or features” will be oriented “above other elements or features.” Thus, the exemplary terms “below” and “under” can cover both above and below orientations. The device may be oriented in other ways (rotated ninety degrees or otherwise) and the spatial relative descriptive terms used herein will be interpreted accordingly. Furthermore, it will be understood that when an element is referred to as “between two other elements,” it may be the only element between the two other elements, or there may be one or more intervening elements.

[0015] Throughout this specification, certain terms used refer to the field. These terms have their general meaning in the field of origin, unless specifically defined herein or otherwise clearly indicated by the context of their use. It should be noted that component names and symbols (e.g., Si for silicon) may be used interchangeably throughout this document; however, they have the same meaning.

[0016] It should be understood that throughout this disclosure, the term "semiconductor substrate" may refer to a portion or the entirety of a semiconductor wafer (e.g., a silicon wafer). A semiconductor substrate may comprise or may otherwise be formed of: silicon, silicon-germanium alloys, germanium, silicon carbide alloys, indium gallium arsenide alloys, any other alloys formed from group III to V compounds, combinations thereof, or a bulk substrate thereof.

[0017] As will be discussed, various examples of pixel array substrates with deep trench isolation structures or back-side deep trench isolation structures that provide reduced current leakage are disclosed. In various pixel array substrates, the pixel array is enclosed in a guard ring region, and one or more devices (e.g., transistors, diodes) are contained in a peripheral region outside the guard ring region. For small pixels (e.g., submicron pixels), blanket-covered deep N-doped wells can be placed close to the back side of the pixel array substrate to form deeper photodiode regions and maximize the full well capacity (FWC) of the pixel without complex or difficult fabrication processes. However, depending on the bias conditions, the blanket-covered deep N-doped wells can create current leakage paths between one or more devices in the peripheral region and the pixel array and / or the guard ring region. Current leakage paths can lead to unnecessary and high power consumption of the imaging system during, for example, standby modes (e.g., low-power modes).

[0018] It should be understood that the pixel array substrate according to the teachings of this disclosure includes a back-side deep trench isolation (DTI) structure region in the peripheral region between one or more devices and a guard ring region. The pixel array substrate may still include a blanket-covered deep N-doped well for maximizing the free flow capacity (FWC) of small pixels, because the DTI structure region blocks the current leakage path generated by the blanket-covered deep N-doped well.

[0019] Therefore, as will be shown and described in the various examples below, an example pixel array substrate includes: a semiconductor substrate comprising a pixel array, a front side, and a back side opposite the front side; a guard ring region formed of doped semiconductor on the semiconductor substrate, surrounding the pixel array and extending from the front side into the semiconductor substrate; and a peripheral region in the semiconductor substrate, surrounding the guard ring region. The peripheral region includes at least one device and a deep trench isolation (DTI) structure region disposed between the guard ring region and the at least one device and adjacent to the back side of the semiconductor substrate. The DTI structure region is configured to block the current path between the PN junction in the guard ring region and the at least one device.

[0020] To illustrate, Figure 1 An example of an imaging system 100 having a pixel array substrate 109 according to the teachings of this disclosure is shown. Specifically, Figure 1 The illustration depicts an imaging system 100 comprising a pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and functional logic 108 disposed on a pixel array substrate 109. In one example, the pixel array 102 is a two-dimensional (2D) array comprising a plurality of pixel circuits 104 (e.g., P1, P2, ..., Pn) arranged in rows (e.g., R1 to Ry) and columns (e.g., C1 to Cx) to acquire image data of people, locations, objects, etc., which can then be used to present images of people, locations, objects, etc.

[0021] In various embodiments, the readout circuit 106 may be configured to read out the image signal via the column bit line 112. In various embodiments, the readout circuit 106 may include an analog-to-digital converter (ADC) 107 according to the teachings of this disclosure. In embodiments, the digital image data value generated by the ADC in the readout circuit 106 may then be received by functional logic 108. The functional logic 108 may simply store the digital image data, or even manipulate the digital image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, etc.).

[0022] In one example, control circuitry 110 is coupled to pixel array 102 to control the operation of a plurality of photodiodes in pixel array 102. For example, control circuitry 110 may generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with, for example, the illumination effect of a flash.

[0023] In one example, the imaging system 100 may be implemented on a single semiconductor wafer. In another example, the imaging system 100 may be implemented on a stack of semiconductor wafers. For example, the pixel array 102 and peripheral circuitry including pixel driving and / or biasing circuitry may be implemented on the pixel wafer, while the readout circuitry 106, control circuitry 110, and / or functional logic 108 may be implemented on an application-specific integrated circuit (ASIC) wafer. The pixel wafer and the ASIC wafer may be stacked and interconnected via bonding (hybrid bonding, oxide bonding, etc.) or one or more through-substrate vias (TSVs). In yet another example, the pixel array 102, peripheral circuitry including pixel driving and / or biasing circuitry, and / or control circuitry 110 may be implemented on the pixel wafer, while the readout circuitry 106 and / or functional logic 108 may be implemented on an ASIC wafer. The pixel wafer and the ASIC wafer may be stacked and interconnected via bonding (hybrid bonding, oxide bonding, etc.) or one or more TSVs.

[0024] In one example, the imaging system 100 may be included in a digital camera, mobile phone, laptop computer, endoscope, security camera, or automotive imaging device. Additionally, the imaging system 100 may be coupled to other hardware blocks, such as processors (general purpose or other), memory elements, outputs (USB ports, wireless transmitters, HDMI ports, etc.), illumination / flash, electrical inputs (keyboards, touch displays, trackpads, mice, microphones, etc.), and / or displays. These other hardware blocks can deliver instructions to the imaging system 100, retrieve image data from the imaging system 100, or manipulate image data supplied by the imaging system 100.

[0025] Figure 2 This diagram illustrates a partial cross-sectional view of the pixel array substrate 209 according to the teachings of this disclosure. It should be understood that... Figure 2 The pixel array substrate 209 can be included in, for example, Figure 1 The example shown is of a pixel array substrate 109 in an imaging system 100, and similarly named and numbered elements described above are similarly coupled and function in the following text.

[0026] In the illustrated example, the pixel array substrate 209 includes a semiconductor substrate 220 having a pixel array 202, a front side 221 (first side), and a back side 223 (second side) opposite the front side. In some embodiments, the back side 223 may be the illuminated side of the pixel array substrate 209. The semiconductor substrate 220 may be a silicon substrate and may be doped with a first conductivity type, such as a P-type doped silicon substrate. A guard ring region 240 formed of doped semiconductor is disposed in the semiconductor substrate 220 and extends from the front side 221 toward the back side 223 into the semiconductor substrate 220. A peripheral region 250 is also disposed in the semiconductor substrate 220 and includes at least one device 260 (e.g., a transistor, diode). The pixel array substrate 209 includes a metal grid pattern region 226 disposed on the back side 223, a buffer layer (e.g., an oxide layer) 224 disposed between the metal grid pattern region 226 and the semiconductor substrate 220, and a blanket-covered deep N-doped well 222. It includes a blanket-covered deep N-doped well 222 formed from doped semiconductors to maximize the full well capacity (FWC) of the pixel without a complex or difficult manufacturing process.

[0027] A blanket-covered deep N-doped well 222 can be formed by blanket-implanting a dopant of a second conductivity type across the semiconductor substrate 220 from the front side 221. The blanket-covered deep N-doped well 222 may have a second conductivity type opposite to the first conductivity type.

[0028] Each of the blanket-covered deep N-doped well 222, the buffer layer 224, and the metal grid pattern region 226 may extend across the pixel array 202, the guard ring region 240, and the peripheral region 250. The blanket-covered deep N-doped well 222 may have a uniform dopant concentration across the pixel array 202, the guard ring region 240, and the peripheral region 250. The guard ring region 240 may be arranged to provide isolation between the pixel array 202 and the peripheral region 250. Although in Figure 2 The portion of the cross-sectional schematic diagram depicted is not visible in the diagram, but in the pixel array substrate 209, the protective ring region 240 can enclose the pixel array 202 and the peripheral region 250 can enclose the protective ring region 240.

[0029] The pixel array 202 includes photodiodes 214 disposed in a first P-type well region 234 and configured to generate image charges in response to incident light. Each photodiode 214 may include one or more photodiode doped regions having a conductivity type opposite to that of the semiconductor substrate 220. For example, one or more photodiode doped regions of the photodiode 214 may be a doped semiconductor composed of dopants or impurities having a second conductivity type (e.g., N-type) opposite to the first conductivity type (e.g., P-type).

[0030] In the illustrated embodiment, each photodiode 214 includes a shallow N-doped region 216 (“shallow photodiode doped region”) and a deep N-doped region 218 (“deep photodiode doped region”) extending from the front side 221 through the first P-type well region 234 to the blanket-covered deep N-doped well 222. The shallow N-doped region 216 has a junction depth smaller than that of the deep N-doped region 218 relative to the front side 221. The shallow N-doped region 216 may have a higher doping concentration than the deep N-doped region 218 and the blanket-covered deep N-doped well 222 to form the photodiode 214, which has a suitable potential profile between the front side 221 and the back side 223 to maximize the corresponding full-well capacity and alleviate transport hysteresis problems.

[0031] Each of the shallow N-doped region 216 and the deep N-doped region 218 may have the same conductivity type as the blanket-covered deep N-doped well 222. That is, the shallow N-doped region 216, the deep N-doped region 218, and the blanket-covered deep N-doped well 222 may all be formed of a dopant or impurity of a second conductivity type, opposite to the first conductivity type of the first P-type well region 234. For example, the shallow N-doped region 216, the deep N-doped region 218, and the blanket-covered deep N-doped well 222 may each be formed of a semiconductor doped with an N-type dopant (e.g., phosphorus and arsenic).

[0032] It should be understood that, in the illustrated embodiment, the blanket-covered deep N-doped well 222 has an N-doped region (i.e., the same doped region as the photodiode 214 but with a conductivity type opposite to the first conductivity type of the semiconductor substrate 220). However, in other embodiments, the polarity can be reversed (i.e., the blanket-covered deep N-doped well 222, the shallow N-doped region 216, and the deep N-doped region 218 of the photodiode 214 can be formed of P-type, while the first P-type well region 234 and the semiconductor substrate 220 can be N-type).

[0033] A blanket-covered deep N-doped well 222 can be disposed in the semiconductor substrate 220 between the deep N-doped region 218 of each corresponding photodiode 214 and the back side 223 of the semiconductor substrate 220. The blanket-covered deep N-doped well 222 can overlap with the deep N-doped region 218 in the depth direction or be otherwise electrically connected to the deep N-doped region 218. The corresponding portions of the shallow N-doped region 216, the deep N-doped region 218, and the blanket-covered deep N-doped well 222 can together form the N-type doped region of the corresponding photodiode 214.

[0034] The pixel array 202 may further include a high-k passivation 228 disposed between the back side 223 of the semiconductor substrate 220 and the buffer layer 224. The high-k passivation 228 may be formed of one or more layers having a dielectric constant greater than 3.9, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, etc. In some embodiments, the pixel array 202 may further include an anti-reflection (AR) layer disposed between the high-k passivation 228 and the buffer layer 224 to reduce reflection and increase transmittance. The AR layer may be formed of a material such as tantalum oxide.

[0035] The metal grid pattern region 226 may have alternative patterns 229a and 229b disposed in the pixel array 202 region, forming and aligned with each of the photodiodes 214 to provide optical isolation. The alternative patterns 229a and 229b may be disposed in the color filter array to separate adjacent color filters.

[0036] The pixel array 202 may also include a pixel array deep trench isolation (DTI) structure region 230 disposed near the back side 223 and extending from the back side 223 toward the front side 221. The pixel array DTI structure region 230 includes a plurality of DTI structures 232. Individuals of the DTI structures 232 may be configured to be disposed between adjacent ones in the deep N-doped region 218 of the photodiode 214 and to isolate each photodiode in the semiconductor substrate 220.

[0037] Pixel array deep trench isolation (DTI) structure regions 230 may be formed such that high-k passivation 228 surrounds each DTI structure 232. Each DTI structure 232 and the surrounding high-k passivation 228 may be deposited in the corresponding trench structure such that the high-k passivation 228 is between each respective DTI structure 232 and the semiconductor substrate 220. The high-k passivation 228 may cover the surface region of the back side 223 of the semiconductor substrate 220 between adjacent DTI structures 232. Each DTI structure 232 may include one or more dielectric materials (e.g., silicon oxide or dielectric materials having a refractive index lower than that of the semiconductor substrate 220) and / or conductive materials (e.g., tungsten, aluminum, polysilicon). Each DTI structure 232 may have an isolation depth D4 relative to the back side 223 and may be separated up to a pitch D5. Individual units of the DTI structure 232 can be arranged to extend from the back side 223 into the semiconductor substrate through the blanket-covered deep N-doped well 222 to an isolation depth D4, thereby separating the blanket-covered deep N-doped well 222 within the pixel array 202 into multiple electrically isolated N-doped well portions. Each of the multiple N-doped well portions is located between the deep N-doped region 218 of each corresponding photodiode 214 and the back side 223 of the semiconductor substrate 220, and contributes to the overall full-well capacity of each corresponding photodiode 214. In various embodiments, the isolation depth D4 can vary in the individual DTI structures 232, and the spacing D5 can also vary among different neighbors in the DTI structure 232.

[0038] The guard ring region 240 may include a plurality of alternating first doped regions and a plurality of second doped regions. The first doped regions and the second doped regions are arranged to have different conductivity types, thereby forming one or more PN junctions across the guard ring region 240 in a lateral manner along a direction parallel to the positive side 221, thereby providing isolation between the pixel array 202 and the peripheral region 250.

[0039] Each of the first doped regions may further include a first heavily doped region and a doped well region each having the same conductivity type (e.g., a first conductivity type (e.g., P-type)). The first heavily doped region and the doped well region may be arranged in the depth direction between the front side 221 and the back side 223 of the semiconductor substrate 220, wherein the first heavily doped region is formed or otherwise disposed in the doped well region. The first heavily doped region may have a dopant concentration greater than that of the doped well region.

[0040] Each of the second doped regions may further include a second heavily doped region, a shallowly doped region, and a deeply doped region disposed in the depth direction between the front side 221 and the back side 223 of the semiconductor substrate 220. The shallowly doped region may be formed between the second heavily doped region and the deeply doped region. The second heavily doped region, the shallowly doped region, and the deeply doped region have a second conductivity type (e.g., N-type) but may have different dopant concentrations. For example, the second heavily doped region may have a higher dopant concentration than the shallowly doped region and the deeply doped region.

[0041] In the illustrated embodiment, the guard ring region 240 includes an N+ doped region 248 disposed on the positive side 221, a shallow N-doped region 249 below the N+ doped region 248, and a deep N-doped region 244 extending through the semiconductor substrate 220 to the blanket-covered deep N-doped well 222. In the illustrated embodiment, each of the N+ doped region 248, the shallow N-doped region 249, and the deep N-doped region 244 has the same second conductivity type as the blanket-covered deep N-doped well 222 (i.e., all formed of dopants or impurities having the second conductivity type). For example, the N+ doped region 248, the shallow N-doped region 249, and the deep N-doped region 244 may be formed of N-type dopants (e.g., phosphorus and arsenic).

[0042] The deep N-doped region 244 may be in direct contact with the blanket-covered deep N-doped well 222. The shallow N-doped region 249 may be disposed between the N+ doped region 248 and the deep N-doped region 244. The N+ doped region 248 may have a dopant concentration greater than that of each of the shallow N-doped region 249, the deep N-doped region 244, and the blanket-covered deep N-doped well 222.

[0043] The guard ring region 240 further includes a second P-type well region 242. The guard ring region 240 may share a first P-type well region 234 with the pixel array 202 and a third P-type well region 252 with the peripheral region 250. P+ doped regions 246 are formed or otherwise disposed in the P-type well regions 234, 242, and 252 near the front side 221. N+ doped regions 248 are each coupled to the pixel voltage PIXVDD 292, and the P+ doped region 246 is coupled to the pixel ground voltage level PIXGND 290. The guard ring region 240 also includes a plurality of shallow trench isolation (STI) structures 236 disposed on the front side 221 and configured to isolate the respective regions.

[0044] At least one of the plurality of shallow trench isolation (STI) structures 236 may be disposed in a well region having a first conductivity type (e.g., a first P-type well region 234, a third P-type well region 252). Each of the plurality of shallow trench isolation (STI) structures 236 may have a structural depth at least greater than the junction depth of each corresponding shallow N-doped region 249. Each of the second P-type well region 242 and the third P-type well region 252 may extend between the front side 221 and the back side 223 of the semiconductor substrate 220. The second P-type well region 242 and the third P-type well region 252 interface with a blanket-covered deep N-doped well 222 to form a PN junction 225, which may potentially cause current leakage paths in the pixel array substrate 209 because the blanket-covered deep N-doped well 222 may electrically couple the deep N-doped region 244 in the guard ring region 240.

[0045] The peripheral region 250 includes at least one device 260 (e.g., a potential-doped device, such as a potential diode) formed in the third P-type well region 252. Each device 260 may include an N+ doped region 268 disposed on the front side 221, a shallow N-doped region 266 below the N+ doped region 268, and a deep N-doped region 264 extending through the third P-type well region 252 to a blanket-covered deep N-doped well 222, such that each of the deep N-doped regions 264 is electrically connected to the blanket-covered deep N-doped well 222. The N+ doped region 268, the shallow N-doped region 266, and the deep N-doped region 264 may be electrically coupled to each other. Each device may also include a P+ doped region 246 disposed within the third P-type well region 252. The peripheral region 250 may also include a back-side metal 254 disposed in the metal grid pattern region 226 and configured to ground the semiconductor substrate 220. The back-side metal 254 may completely cover the peripheral region 250. One or more of the N+ doped regions 268 may be coupled to a voltage source AVDD 280 to receive a bias voltage. The bias voltage provided by the voltage source AVDD 280 may differ from the pixel voltage PIXVDD 292. The bias voltage provided by the voltage source AVDD 280 may be greater than the pixel ground voltage level, resulting in the formation of one or more PN junction leakage paths. In a conventional imaging system, current will leak between the device 260 in the peripheral region 250 and the guard ring region 240 via, for example, the PN junction 225 in the guard ring region 240 through the blanket-covered deep N-doped well 222.

[0046] To block this current leakage, the pixel array substrate 209 according to the teachings of this disclosure includes a deep trench isolation (DTI) structure region or a back-side deep trench isolation (BDTI) structure region 270 disposed in the peripheral region 250 between the device 260 and the guard ring region 240 and near the back side 223. The BDTI structure region 270 effectively divides the blanket-covered deep N-doped well 222 into a first sub-doped well portion extending across at least one device 260 in the peripheral region 250 and a second sub-doped well portion extending across the guard ring region 240. The first sub-doped well portion extending across at least one device 260 in the peripheral region 250 and the second sub-doped well portion extending across the guard ring region 240 are structurally separated and electrically isolated from each other. Dividing the blanket-covered deep N-doped well 222 into first and second sub-doped well portions can reduce or prevent current leakage between device 260 and guard ring region 240, for example, by separating the deep N-doped region 264 of device 260 in peripheral region 250 from the deep N-doped region 244 in guard ring region 240, and / or blocking one or more current paths between PN junction 225 in guard ring region 240 and device 260, thereby avoiding unnecessary power consumption of the imaging system during, for example, standby mode (e.g., low power mode).

[0047] In some embodiments, the BDTI structure region 270 may be positioned to enclose the protection ring region 240. In some embodiments, the BDTI structure region 270 may be positioned to enclose at least one device 260 or all devices 260 in the peripheral region 250 to effectively disconnect one or more current paths between the PN junction 225 in the protection ring region 240 and the device 260.

[0048] BDTI structure region 270 may include a plurality of BDTI structures 272. In some embodiments, the BDTI structures 272 may be structurally interconnected to form a grid. In such embodiments, a plurality of DTI structures 232 may also be formed within the pixel array 202 to provide an isolation grid. BDTI structure region 270 may be configured such that a high-k passivation 228 surrounds each BDTI structure 272. BDTI structure region 270 is structurally disconnected from pixel array DTI structure region 230.

[0049] Each BDTI structure 272 and the surrounding high-k passivation layer 228 may be deposited in a corresponding trench structure such that a corresponding segment of the high-k passivation layer 228 is between each corresponding BDTI structure 272 and the semiconductor substrate 220. The high-k passivation layer 228 may be disposed between the BDTI structure 272 and the semiconductor substrate 220. The filler material may include a dielectric material (e.g., silicon oxide or a dielectric material having a refractive index lower than that of the semiconductor substrate 220) and / or a conductive material (e.g., tungsten, aluminum, or polysilicon). The high-k passivation 228 may cover the surface region of the back side 223 of the semiconductor substrate 220 between adjacent BDTI structures 272. In the illustrated embodiment, the high-k passivation layer 228 may be configured to extend continuously across the pixel array 202, the guard ring region 240, and the peripheral region 250 on and cover the surface region of the back side 223.

[0050] Each BDTI structure 272 may have an isolation depth D1 relative to the back side 223 and may be separable up to a spacing D2. The BDTI structure region 270 may have a width D3 overall (e.g., at least 5 μm, at least 10 μm, at least 20 μm). In various instances, the isolation depth D1 may vary among individual BDTI structures 272, and the spacing D2 may also vary among different neighbors of the BDTI structures 272. In some embodiments, the isolation depth D1 extended by each BDTI structure 272 is greater than the junction depth of the blanket-covered deep N-doped well 222 relative to the back side 223 of the semiconductor substrate 220. In some embodiments, the isolation depth D1 extended by each BDTI structure 272 is greater than the interface depth between the blanket-covered deep N-doped well 222 and the third P-type well region 252. Within the region of the BDTI structure region 270, the blanket-covered deep N-doped well 222 may be separated or divided into a plurality of electrically isolated N-doped well portions. Each of the plurality of N-doped well portions may have a doped well region width substantially the same as the spacing D2 between adjacent BDTI structures 272. In some embodiments, the plurality of BDTI structures 272 contained in BDTI structure region 270 may have similar or identical structural characteristics to the plurality of DTI structures 232 contained in pixel array DTI structure region 230. For example, the BDTI structure isolation depth D1 may be similar or identical to the pixel array DTI structure isolation depth D4, and / or the BDTI structure spacing D2 may be similar or identical to the pixel array DTI structure spacing D5. By having similar or identical structural characteristics, pixel array DTI structure region 230 and BDTI structure region 270 can be fabricated more easily and cost-effectively because a common DTI pattern can be used to insert a common patterned photoresist mask over the entire pixel array substrate 209.

[0051] In some embodiments, the BDTI structure region 270 may include one or more individual BDTI structures 272 disposed between at least one device 260 in the guard ring region 240 and the peripheral region 250 to effectively divide the blanket-covered deep N-doped well 222 into a first sub-doped well portion extending across at least one device 260 in the peripheral region 250 and a second sub-doped well portion extending across the guard ring region 240. The first sub-doped well portion extending across at least one device 260 in the peripheral region 250 and the second sub-doped well portion extending across the guard ring region 240 may be electrically isolated from each other.

[0052] For example, a single BDTI structure 272 having a sufficient structural width (e.g., at least 1 μm) can be positioned to surround the guard ring region 240 to minimize the amount of required substrate space. In another example, multiple BDTI structures 272 can be individually positioned and spaced apart by an appropriate pitch (e.g., pitch D2) to surround or otherwise enclose the guard ring region 240, rather than forming a structurally interconnected grid to block the aforementioned current leakage between the device 260 in the peripheral region 250 and the guard ring region 240. In some embodiments, individual BDTI structures 272 can be spaced apart by the same pitch D5 (e.g., pitch D2) as adjacent DTI structures 232 of the pixel array DTI structure region 230. Each of the individual BDTI structures 272 can have similar or identical structural characteristics to each of the DTI structures 232 of the pixel array DTI structure region 230. In some embodiments, the individual BDTI structure 272 of the BDTI structure region 270 can be formed using the same process as the DTI structure 232 of the pixel array DTI structure region 230 (e.g., by using the same patterned photoresist mask) to reduce manufacturing costs.

[0053] In some embodiments, the deep N-doped region 244 may be removed or omitted from the pixel array substrate 209 to further disconnect the current leakage path between the guard ring region 240 and one or more devices 260 disposed in the peripheral region 250 and reduce power consumption.

[0054] Figure 3A The diagram at point C illustrates a top-down view of an example pixel array substrate 309 according to the teachings of this disclosure. It should be understood that... Figure 3A The pixel array substrate 309 to C can be as follows Figure 2 The example of pixel array substrate 209 shown above, and similarly named and numbered elements described above are similarly coupled and function in the following text.

[0055] In the illustrated example, each pixel array substrate 309 includes a pixel array 302 disposed within the substrate 309 and a guard ring region 340 that substantially encloses the pixel array 302 on all sides. The guard ring region 340 defines a peripheral region 350 on the opposite side of the pixel array 302. Each pixel array substrate 309 also includes a plurality of devices 360 disposed in the peripheral region 350 and a BDTI structure region 370 having one or more BDTI structures 372 (described as individual rectangles that may or may not form a grid). The BDTI structure region 370 may be separated and disconnected from the pixel array BDTI structure region (e.g., pixel array BDTI structure region 230) in the pixel array 302. In the illustrated example, the BDTI structure region 370 is at least separated from the pixel array BDTI structure region by a guard ring structure formed by a junction in the guard ring region 340. As described above regarding Figure 2 The discussion focuses on how the BDTI structure region 370 can block current leakage paths in the blanket-covered deep N-doped well (e.g., blanket-covered deep N-doped well 222) between the device 360 ​​and the guard ring region 340. As will be discussed in further detail below, the BDTI structure region 370 can be patterned on the back side of the pixel array substrate 309. The back side can be the illuminated side of the pixel array substrate 309.

[0056] refer to Figure 3A The BDTI structure region 370 is formed around the pixel array 302 and the guard ring region 340, but not around the device 360 ​​in the peripheral region 350. The BDTI structure region 370 is still positioned between the device 360 ​​and the guard ring region 340, and can block the current leakage path between the device 360 ​​and the guard ring region 340. (Refer to...) Figure 3B The BDTI structure region 370 is formed around the individual devices 360, but not around the pixel array 302 and the guard ring region 340. The BDTI structure region 370 is still positioned between the devices 360 and the guard ring region 340, and can block the current leakage path between the devices 360 and the guard ring region 340. (Reference) Figure 3C The BDTI structure region 370 is formed around the grouped devices, but not around the pixel array 302 and the guard ring region 340. The BDTI structure region 370 is still located between the device 360 ​​and the guard ring region 340, and can block the current leakage path between the device 360 ​​and the guard ring region 340.

[0057] from Figure 3B and 3C It is understood that device 360 ​​can be grouped into multiple groups, and multiple BDTI structure regions 370 can surround each group or each individual device 360. It should be understood that they can be combined in various ways. Figure 3AThe layout described in section C is as follows. For example, the BDTI structure region 370 may cover the entire peripheral region 350, such that the BDTI structure region 370 surrounds the pixel array 302, the guard ring region 340, and the device 360. It should be further understood that other layouts of the BDTI structure region 370 may be used.

[0058] It should be understood that, in some embodiments, instead of the illustrated embodiment comprising a plurality of BDTI structures 372 structurally interconnected to form a grid, one or more individually positioned BDTI structures 372 may be used to surround or otherwise enclose the protection ring region 340, or to surround or otherwise enclose each group or individual device 360 ​​of the device 360, to block current leakage paths between the device 360 ​​and the protection ring region 340, while minimizing the space required in the peripheral region 350. For example, a single BDTI structure 372 may be positioned to surround or otherwise enclose the protection ring region 340, or to surround or otherwise enclose each group or individual device 360 ​​of the device 360. In another example, a plurality of BDTI structures 372 may be individually positioned with appropriate spacing between them to surround or otherwise enclose the protection ring region 340.

[0059] In various instances, the material and dimensions (e.g., width) of the BDTI structure region 370, as well as the material and dimensions (e.g., trench or isolation depth, spacing) of the individual BDTI structures 372 and the number of BDTI structures 372, can be individually configured based on the specific requirements of the imaging system (e.g., leakage level, available substrate or wafer space and / or process capabilities).

[0060] It is not intended that the foregoing description of the illustrative examples in this disclosure (including the description in the abstract) be exhaustive or limit this disclosure to its precise form. While specific examples of this disclosure have been described herein for illustrative purposes, those skilled in the art will recognize that various modifications are possible within the scope of this disclosure.

[0061] These modifications may be made to this disclosure based on the detailed description above. The terminology used in the appended claims should not be construed as limiting this disclosure to the specific instances disclosed in this specification. Rather, the scope of this disclosure shall be determined entirely by the appended claims, which shall be interpreted according to the established principles of claim interpretation.

Claims

1. A pixel array substrate, comprising: A semiconductor substrate comprising a pixel array, a first side, and a second side opposite to the first side; A protective ring region, formed of doped semiconductor in the semiconductor substrate, surrounds the pixel array and extends from the first side into the semiconductor substrate; and A peripheral region, which is located in the semiconductor substrate and encloses the protective ring region, wherein the peripheral region comprises: At least one device; and A deep trench isolation structure region is disposed between the protection ring region and the at least one device and on the second side of the semiconductor substrate. The deep trench isolation structure region is configured to block the current path between the PN junction in the protection ring region and the at least one device.

2. The pixel array substrate of claim 1, further comprising a blanket-covered deep doped well adjacent to the second side of the semiconductor substrate, wherein the blanket-covered deep doped well extends across the pixel array, the guard ring region, and the peripheral region.

3. The pixel array substrate of claim 2, wherein the deep trench isolation structure region is configured to divide the blanket-covered deep doped well into a first sub-doped well portion extending across the at least one device and a second sub-doped well portion extending across the guard ring region.

4. The pixel array substrate of claim 2, wherein the deep trench isolation structure region is configured to extend from the second side of the semiconductor substrate to an isolation depth, and wherein the isolation depth is deeper than the thickness of the blanket-covered deep doped well relative to the second side.

5. The pixel array substrate of claim 2, wherein the at least one device includes a doped region configured to extend from the first side and contact the blanket-covered deep doped well, wherein the doped region of the at least one device and the blanket-covered deep doped well have the same conductivity type.

6. The pixel array substrate of claim 2, wherein the guard ring region comprises a shallow doped region having a first junction depth and a deep doped region having a second junction depth, wherein the second junction depth is greater than the first junction depth relative to the first side, and wherein the deep doped region extends between the shallow doped region and the blanket-covered deep doped well.

7. The pixel array substrate according to claim 6, wherein the deep doped region is in direct contact with the blanket-covered deep doped well, wherein the shallow doped region, the deep doped region and the blanket-covered deep doped well have the same conductivity type.

8. The pixel array substrate of claim 1, further comprising a high-k passivation layer adjacent to the second side of the semiconductor substrate, wherein the high-k passivation layer extends across the peripheral region, the guard ring region, and the deep trench isolation structure region.

9. The pixel array substrate of claim 1, wherein the deep trench isolation structure region is configured to enclose the protective ring region.

10. The pixel array substrate of claim 1, wherein the at least one device comprises a plurality of devices, and wherein the deep trench isolation structure region is configured to enclose each of the devices.

11. The pixel array substrate of claim 1, wherein the at least one device comprises a plurality of devices, and wherein the deep trench isolation structure region is configured to enclose the at least one device.

12. The pixel array substrate of claim 1, wherein the deep trench isolation structure region comprises a plurality of deep trench isolation structures interconnected in a grid.

13. The pixel array substrate of claim 1, wherein the deep trench isolation structure region comprises a plurality of deep trench isolation structures spaced apart from each other.

14. A pixel array substrate, comprising: A semiconductor substrate comprising a pixel array, a first side, and a second side opposite to the second side, wherein the pixel array comprises: Multiple photodiodes; and A first deep trench isolation structure region is disposed close to the second side of the semiconductor substrate, wherein the first deep trench isolation structure region includes a first plurality of deep trench isolation structures; A protective ring region, which encloses the pixel array on the semiconductor substrate and extends from the first side into the semiconductor substrate; and A peripheral region, which is located in the semiconductor substrate and encloses the protective ring, wherein the peripheral region comprises: At least one device; and A second deep trench isolation structure region is disposed between the protection ring region and the at least one device and on the second side of the semiconductor substrate. The first deep trench isolation structure region is configured to isolate each of the plurality of photodiodes in the semiconductor substrate, and The second deep trench isolation structure region is configured to block the current path between the PN junction protection ring in the protection ring region and the at least one device.

15. The pixel array substrate of claim 14, wherein the first deep trench isolation structure region and the second deep trench isolation structure region are configured to extend from the second side to a common isolation depth.

16. The pixel array substrate of claim 14, wherein the first deep trench isolation structure region is configured to extend from the second side to a first isolation depth, and wherein the second deep trench isolation structure region is configured to extend from the second side of the semiconductor substrate to a second isolation depth different from the first isolation depth.

17. The pixel array substrate of claim 14, wherein the second deep trench isolation structure region includes a second plurality of deep trench isolation structures, wherein adjacent members of the first plurality of deep trench isolation structures are configured to be spaced apart by a common spacing distance, and wherein adjacent members of the second plurality of deep trench isolation structures are configured to be spaced apart by the common spacing distance.

18. The pixel array substrate of claim 14, wherein each of the photodiodes includes a photodiode doped region configured to extend from the first side, and wherein individual of the first plurality of deep trench isolation structures is configured to be disposed between adjacent photodiode doped regions of the photodiodes.

19. The pixel array substrate of claim 18, further comprising a blanket-covered deep doped well extending across the pixel array, the guard ring region, and the peripheral region adjacent to the second side of the semiconductor substrate, wherein the blanket-covered deep doped well has the same conductivity type as the photodiode doped region, wherein the second deep trench isolation structure region is configured to divide the blanket-covered deep doped well into a first sub-doped well portion extending across the peripheral region and a second sub-doped well portion extending across the guard ring region.

20. An imaging system comprising: A semiconductor substrate comprising a pixel array, a first side, and a second side opposite to the first side; A protective ring region that encloses the pixel array within the semiconductor substrate; and A peripheral region, which is located in the semiconductor substrate and encloses the protective ring region, wherein the peripheral region comprises: At least one device, comprising a doped region; and A deep trench isolation structure is disposed between the protection ring region and the at least one device and close to the second side of the semiconductor substrate; and A blanket-covered deep-doped well, disposed close to the second side of the semiconductor substrate, extends across the pixel array, the guard ring region, and the peripheral region, wherein the doped region extends from the first side and contacts the blanket-covered deep-doped well. The deep trench isolation structure is configured to extend through the blanket-covered deep doped well, thereby dividing the blanket-covered deep doped well into a first sub-doped well portion extending across the peripheral region and a second sub-doped well portion extending across the guard ring region, and blocking the current path between the PN junction in the guard ring region and the doped region of the at least one device.

21. The imaging system of claim 20, wherein the deep trench isolation structure is configured to enclose the protective ring area.

22. The imaging system of claim 20, wherein the at least one device comprises a plurality of devices, and wherein the deep trench isolation structure is configured to enclose all of the devices.

Images