Solar cell and method of manufacturing the same, photovoltaic module
By forming a tunneling layer on the semiconductor substrate of a solar cell and performing plasma hydrogenation treatment, the problem of insufficient passivation quality of the tunneling oxide layer is solved, thereby improving the passivation performance and efficiency of the cell.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TRINA SOLAR CO LTD
- Filing Date
- 2024-08-27
- Publication Date
- 2026-07-21
AI Technical Summary
In existing solar cells, contact recombination in the metal-silicon interface region, Auger recombination due to diffusion in the silicon substrate, and deep-level recombination are the main factors restricting the improvement of cell efficiency. The passivation quality of the tunneling oxide layer needs to be improved.
A tunneling layer is formed on a semiconductor substrate using plasma technology, and the tunneling layer is then hydrogenated using plasma technology to form a doped semiconductor layer and an electrode with an ohmic contact. Process parameters are optimized to improve passivation performance.
Reducing the density of unsaturated dangling bonds on the surface of the tunneling layer improves the passivation quality of the tunneling layer, thereby enhancing battery efficiency.
Smart Images
Figure CN119008780B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of solar photovoltaic cell technology, and in particular to a solar cell and its preparation method, and a photovoltaic module. Background Technology
[0002] With the continuous development of solar cell technology, the requirements for photoelectric conversion efficiency are becoming increasingly stringent. However, improving the efficiency of industrially produced solar cells still faces many challenges. Among these, contact recombination at the metal-silicon interface, Auger recombination due to diffusion in the silicon substrate, and deep-level recombination are the main factors restricting efficiency improvement. Related technologies reduce surface carrier recombination by setting passivation contact structures on the silicon substrate surface. These passivation contact structures consist of a tunneling oxide layer and a doped polycrystalline silicon layer. However, the passivation quality and performance of current tunneling oxide layers need further improvement. Summary of the Invention
[0003] Therefore, it is necessary to provide a solar cell, its preparation method, and a photovoltaic module to address the above-mentioned problems.
[0004] In a first aspect, embodiments of this application provide a method for preparing a solar cell, comprising:
[0005] A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface disposed opposite to each other;
[0006] A first tunneling layer is formed on at least a portion of the first surface using a first plasma process;
[0007] The first tunneling layer is hydrogenated using a second plasma process.
[0008] A first doped semiconductor layer is formed on the side of the first tunneling layer away from the semiconductor substrate;
[0009] A first electrode is formed on the side of the first doped semiconductor layer away from the semiconductor substrate, making ohmic contact with the first doped semiconductor layer.
[0010] In one embodiment, the process gas of the second plasma process includes ammonia and argon, and the volume flow ratio of the ammonia and the argon is between 3:1 and 2:1.
[0011] And / or, the cavity pressure of the second plasma process is between 1200 mbar and 1500 mbar;
[0012] And / or, the power of the second plasma process is between 11000W and 13000W;
[0013] And / or, the processing time of the second plasma process is between 50s and 60s;
[0014] And / or, the processing temperature of the second plasma process is between 440°C and 455°C.
[0015] In one embodiment, forming a first doped semiconductor layer on the side of the first tunneling layer away from the semiconductor substrate includes:
[0016] A doped amorphous semiconductor layer is formed on the side of the first tunneling layer away from the semiconductor substrate using a third plasma process;
[0017] A protective layer is formed on the side of the doped amorphous semiconductor layer away from the semiconductor substrate;
[0018] The doped amorphous semiconductor layer is crystallized to form the first doped semiconductor layer.
[0019] In one embodiment, the first plasma process, the second plasma process, and the third plasma process all use the same plasma equipment.
[0020] In one embodiment, the process gas of the third plasma process includes silane, argon and phosphine, and the volume flow ratio of silane, argon and phosphine is between 22:40:1 and 22:55:1.
[0021] And / or, the cavity pressure of the third plasma process is between 2700 mbar and 2900 mbar;
[0022] And / or, the power of the third plasma process is between 12000W and 13000W;
[0023] And / or, the processing time of the third plasma process is between 3450s and 3550s;
[0024] And / or, the processing temperature of the third plasma process is between 440°C and 455°C.
[0025] In one embodiment, the process gas of the first plasma process includes nitrous oxide, and the volumetric flow rate of the nitrous oxide is between 10,000 sccm and 12,000 sccm.
[0026] And / or, the cavity pressure of the first plasma process is between 2700 mbar and 2900 mbar;
[0027] And / or, the power of the first plasma process is between 15000W and 16000W;
[0028] And / or, the processing time of the first plasma process is between 100s and 140s;
[0029] And / or, the processing temperature of the first plasma process is between 430°C and 450°C.
[0030] In one embodiment, the semiconductor substrate has a first conductive region and a second conductive region arranged along a first direction; the first direction is perpendicular to the thickness direction of the semiconductor substrate.
[0031] The formation of a first tunneling layer on at least a portion of the first surface using a first plasma process includes:
[0032] A first tunneling layer is formed on the first surface located in the first conductive region using a first plasma process.
[0033] In one embodiment, after providing the semiconductor substrate and before forming the first tunneling layer on at least a portion of the first surface using a first plasma process, the process includes:
[0034] A second tunneling layer is formed on the first surface located in the second conductive region;
[0035] A second doped semiconductor layer is formed on the side of the second tunneling layer away from the semiconductor substrate.
[0036] In one embodiment, an isolation region is further provided on the semiconductor substrate, the isolation region being located between the first conductive region and the second conductive region;
[0037] The step of forming a first tunneling layer on the first surface located in the first conductive region using a first plasma process includes: forming a first tunneling material layer on the first surface located in the first conductive region and the isolation region using a first plasma process; wherein the first tunneling material layer located in the first conductive region and on the first surface forms the first tunneling layer.
[0038] After forming a first doped semiconductor layer on the side of the first tunneling layer away from the semiconductor substrate, and before forming a first electrode in ohmic contact with the first doped semiconductor layer on the side of the first doped semiconductor layer away from the semiconductor substrate, the process includes:
[0039] Remove the first tunneling material layer located in the isolation zone and form an isolation groove on the first surface located in the isolation zone;
[0040] The semiconductor substrate is texturized.
[0041] A first passivation layer group is formed on the side of the first doped semiconductor layer away from the semiconductor substrate, and a second passivation layer group is formed on the second surface.
[0042] Secondly, embodiments of this application provide a solar cell, comprising:
[0043] A semiconductor substrate, including a first surface and a second surface disposed opposite to each other;
[0044] A first tunnel layer is disposed on at least a portion of the first surface;
[0045] A first doped semiconductor layer is disposed on the side of the first tunneling layer away from the semiconductor substrate; and
[0046] The first electrode is disposed on the side of the first doped semiconductor layer away from the semiconductor substrate and is in ohmic contact with the first doped semiconductor layer;
[0047] The first tunneling layer is configured to be hydrogenated by a plasma process after being deposited using a plasma process.
[0048] In one embodiment, the semiconductor substrate has a first conductive region, a second conductive region, and an isolation region arranged along a first direction, the isolation region being located between the first conductive region and the second conductive region; the first direction is perpendicular to the thickness direction of the semiconductor substrate; the first tunneling layer is disposed on the first surface located on the first conductive region;
[0049] The solar cell also includes:
[0050] The second tunneling layer is disposed on the first surface located in the second conductive region;
[0051] A second doped semiconductor layer is disposed on the side of the second tunneling layer away from the semiconductor substrate;
[0052] An isolation groove is disposed on the first surface located in the isolation zone;
[0053] A first passivation layer group is disposed on the side of the first doped semiconductor layer and the second doped semiconductor layer away from the semiconductor substrate;
[0054] A second passivation layer group is disposed on the second surface;
[0055] The second electrode penetrates the first passivation layer group and is in ohmic contact with the second doped semiconductor layer.
[0056] In one embodiment, the solar cell further includes a nitrogen-rich layer, which is disposed on at least a portion of the surface of the first tunneling layer on the side away from the semiconductor substrate.
[0057] Thirdly, embodiments of this application provide a photovoltaic module, including a solar cell in any of the second-direction embodiments.
[0058] The solar cells and their fabrication methods and photovoltaic modules provided in this application, after forming a first tunneling layer by plasma deposition, undergo hydrogenation treatment of the first tunneling layer by plasma process. This can reduce the density of unsaturated dangling bonds on the surface of the first tunneling layer, improve the passivation quality and passivation performance of the first tunneling layer, and thus help improve the cell efficiency. Attached Figure Description
[0059] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0060] Figure 1 This is a schematic flowchart of a method for fabricating a solar cell according to an embodiment of this application.
[0061] Figure 2 This is a schematic diagram of another process for fabricating a solar cell according to an embodiment of this application.
[0062] Figure 3 for Figure 2 The diagram shows a partial cross-sectional structure of the second tunneling material layer and the second intrinsic semiconductor material layer after they are formed during the fabrication process shown.
[0063] Figure 4 for Figure 2 A schematic diagram of a local cross-sectional structure after the formation of the second doped semiconductor material layer and the borosilicate glass layer during the preparation method shown.
[0064] Figure 5 for Figure 2 A schematic diagram of a local cross-sectional structure after the mask layer is formed during the fabrication process shown.
[0065] Figure 6 for Figure 2 This is a schematic diagram of a partial cross-sectional structure after a portion of the borosilicate glass layer has been removed during the preparation process shown.
[0066] Figure 7 for Figure 2 The diagram shows a partial cross-sectional structure after the second doped semiconductor material layer and the second tunneling material layer are removed in a certain area during the fabrication process shown.
[0067] Figure 8for Figure 2 The diagram shows a partial cross-sectional structure of the first tunneling material layer, the doped amorphous semiconductor layer, and the protective layer after they are formed during the preparation process shown.
[0068] Figure 9 for Figure 2 The diagram shows a partial cross-sectional structure after the protective layer in some areas is removed during the preparation process shown.
[0069] Figure 10 for Figure 2 A schematic diagram of a local cross-sectional structure after the isolation groove is formed during the preparation method shown.
[0070] Figure 11 for Figure 2 A schematic diagram of a local cross-sectional structure of the semiconductor substrate after texturing during the fabrication process shown.
[0071] Figure 12 for Figure 2 A schematic diagram of a partial cross-sectional structure after the protective layer and borosilicate glass layer are removed during the preparation process shown.
[0072] Figure 13 for Figure 2 A schematic diagram of a local cross-sectional structure after the passivation material layer is formed during the preparation method shown.
[0073] Figure 14 This is a schematic diagram of a partial cross-sectional structure of a solar cell provided in an embodiment of this application.
[0074] Figure label:
[0075] 1. Solar cell; 11. Semiconductor substrate; 11a. First conductive region; 11b. Second conductive region; 11c. Isolation region; 111. First surface; 112. Second surface; 121. First tunneling layer; 122. First doped semiconductor layer; 131. Second tunneling layer; 132. Second doped semiconductor layer; 141. First electrode; 142. Second electrode; 15. Isolation trench; 16. First passivation layer group; 161. First passivation layer; 162. First antireflection layer; 17. Second passivation layer group; 171. Second passivation layer; 172. Second antireflection layer; 21. Second tunneling material layer; 22. Second intrinsic semiconductor material layer; 23. Second doped semiconductor material layer; 24. Borosilicate glass layer; 25. Mask layer; 26. First tunneling material layer; 27. Doped amorphous semiconductor layer; 28. Protective layer; 29. Passivation material layer. Detailed Implementation
[0076] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.
[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0078] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.
[0079] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0080] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0081] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the application.
[0082] Firstly, referring to Figure 1 and combined Figures 3-14 As shown, this application provides a method for fabricating a solar cell 1, which can be used to fabricate back contact (BC) cells, tunnel oxide passivating contacts (TOPCon) cells, etc.
[0083] The preparation method specifically includes the following steps:
[0084] S100: A semiconductor substrate 11 is provided, comprising a first surface 111 and a second surface 112 disposed opposite to each other. Here, one of the first surface 111 and the second surface 112 is a light-facing surface, and the other is a backlight surface. It is understood that the material of the semiconductor substrate 11 can be silicon, compound semiconductors, and wide bandgap semiconductor materials. Exemplarily, silicon includes crystalline silicon and amorphous silicon. Compound semiconductors include selenium, selenides, etc. Wide bandgap semiconductor materials include silicon carbide, gallium nitride, diamond, etc. It should be noted that the semiconductor substrate 11 can be double-sided polished in this step. For example, by treating it in an alkaline polishing solution at 60°C-80°C for 200-250 seconds, a bulk structure with a size of 13μm-18μm is formed on the surface of the semiconductor substrate 11. The alkaline polishing solution may include tetramethylamino hydroxide, potassium hydroxide, and polishing agents, etc.
[0085] S400: A first tunneling layer 121 is formed on at least a portion of the first surface 111 using a first plasma process. Exemplarily, the first tunneling layer 121 can be made of a dielectric material, such as silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, or titanium oxide. Specifically, the first tunneling layer 121 can be deposited using a PECVD (Plasma Enhanced Chemical Vapor Deposition) process.
[0086] S500: The first tunneling layer 121 is hydrogenated using a second plasma process. Hydrogenation of the first tunneling layer 121 saturates the dangling bonds on its surface with hydrogen, reducing the density of unsaturated dangling bonds and improving the passivation quality and performance of the first tunneling layer 121. Furthermore, performing the second plasma process immediately after the first plasma process helps reduce process costs. For example, the first and second plasma processes can be performed within the same chamber, eliminating the need to transfer the semiconductor substrate 11 from one chamber to another, thus avoiding the need to repeatedly construct the vacuum environment required for the plasma process.
[0087] S600: A first doped semiconductor layer 122 is formed on the side of the first tunneling layer 121 away from the semiconductor substrate 11. The material of the first doped semiconductor layer 122 can be amorphous silicon, polycrystalline silicon, microcrystalline silicon, silicon carbide, etc. It is understood that the first doped semiconductor layer 122 can be prepared using processes such as ALD (Atomic Layer Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), and LPCVD (Low Pressure Chemical Vapor Deposition). The doping type of the first doped semiconductor layer 122 can be N-type or P-type.
[0088] S1000: A first electrode 141 is formed on the side of the first doped semiconductor layer 122 away from the semiconductor substrate 11, making ohmic contact with the first doped semiconductor layer 122. The material of the first electrode 141 includes, but is not limited to, one or more of aluminum, titanium, nickel, cobalt, silver, copper, and tin. The first electrode 141 can be formed by coating and sintering.
[0089] In one embodiment, the process gas for the second plasma process includes ammonia and argon. Thus, in the second plasma process, the bombardment of Ar ions enhances the ionization of H in NH3, and the ionized H reduces the density of unsaturated dangling bonds on the surface of the first tunneling layer 121. The ionized N in NH3 forms a nitrogen-rich layer on the surface of the first tunneling layer 121, which blocks H leakage during metallization sintering, suppressing the decrease in passivation quality of the first tunneling layer 121 during sintering. Furthermore, the N in the nitrogen-rich layer enhances the energy of the Si-H bonds, further improving the electrical properties and thermal stability of the first doped semiconductor layer 122.
[0090] In one embodiment, the volumetric flow rate ratio of ammonia to argon is between 3:1 and 2:1. Exemplarily, the volumetric flow rate ratio of ammonia to argon can be 3:1, 2.5:1, 2:1, etc. By keeping the volumetric flow rate ratio of ammonia to argon within the above range, it is beneficial to better reduce the density of unsaturated dangling bonds on the surface of the first tunneling layer 121, and further improve the electrical performance and thermal stability of the first doped semiconductor layer 122.
[0091] In one embodiment, the chamber pressure of the second plasma process is between 1200 mbar and 1500 mbar. Exemplarily, the chamber pressure of the second plasma process can be 1200 mbar, 1300 mbar, 1400 mbar, 1500 mbar, etc.
[0092] In one embodiment, the power of the second plasma process is between 11000W and 13000W. For example, the power of the second plasma process can be 11000W, 12000W, 13000W, etc.
[0093] In one embodiment, the processing time of the second plasma process is between 50s and 60s. For example, the processing time of the second plasma process can be 50s, 55s, 58s, 60s, etc.
[0094] In one embodiment, the processing temperature of the second plasma process is between 440°C and 455°C. Exemplarily, the processing temperature of the second plasma process can be 440°C, 450°C, 455°C, etc.
[0095] By setting the process parameters of the second plasma process within the aforementioned range, it is beneficial to better reduce the density of unsaturated dangling bonds on the surface of the first tunneling layer 121, and further improve the electrical performance and thermal stability of the first doped semiconductor layer 122.
[0096] In one embodiment, S600: A first doped semiconductor layer 122 is formed on the side of the first tunneling layer 121 away from the semiconductor substrate 11, specifically including the following steps:
[0097] S610: A doped amorphous semiconductor layer 27 is formed on the side of the first tunneling layer 121 away from the semiconductor substrate 11 using a third plasma process. For example, the doped amorphous semiconductor layer 27 may be a phosphorus-containing amorphous silicon layer; further, a phosphorus-containing amorphous silicon layer may be deposited using a PECVD process. It should be noted that a step-by-step deposition method may be used during the deposition of the doped amorphous semiconductor layer 27.
[0098] S620: A protective layer 28 is formed on the side of the doped amorphous semiconductor layer 27 away from the semiconductor substrate 11. Exemplarily, the protective layer 28 may be a silicon oxide layer; further, a silicon oxide layer may be deposited using a PECVD process. Specifically, silane and nitrous oxide may be introduced to deposit a silicon oxide layer on the surface of the doped amorphous semiconductor layer 27. The volumetric flow rate ratio of silane to nitrous oxide may be 2:9, 1:4.8, 1:5, etc.; the chamber pressure may be 1400 mbar-1600 mbar; the power may be 8500 W-9500 W; the temperature may be 430°C-440°C; and the deposition time may be 40 s-50 s.
[0099] S630: The doped amorphous semiconductor layer 27 is crystallized to form the first doped semiconductor layer 122. Exemplarily, the semiconductor substrate 11 can be placed in an annealing furnace at a constant temperature of 900℃-930℃ for 40s-60s, with a heating rate of 0.1℃ / s and a heating time of 250s-350s. It should be noted that the initial temperature in the annealing furnace can be between 810℃ and 825℃, and the temperature can be raised multiple times, with each heating time being 250s-350s. The structure after the protective layer 28 and the first doped semiconductor layer 122 are formed is as follows... Figure 8 As shown.
[0100] In one embodiment, the first plasma process, the second plasma process, and the third plasma process all employ the same plasma equipment. Specifically, a PECVD equipment is used for the first plasma process, the second plasma process, and the third plasma process. Thus, the fabrication process maintains good continuity during the preparation of the first tunneling layer 121 and the first doped semiconductor layer 122. The first plasma process, the second plasma process, and the third plasma process are performed consecutively within the same cavity, eliminating the need to transfer the semiconductor substrate 11 from one cavity to another. This avoids repeatedly constructing the vacuum environment required for the plasma process, reducing process costs. Furthermore, throughout the entire process, there is no need to remove the semiconductor substrate 11 from the cavity to the air environment, preventing contamination of the semiconductor substrate 11, the first tunneling layer 121, and the first doped semiconductor layer 122 by impurities from the external environment.
[0101] In one embodiment, the process gas for the third plasma process includes silane, argon, and phosphine. It should be noted that silane can provide a silicon source, and phosphine can provide a doping source. Using argon can, on the one hand, promote the ionization of silane, increasing the deposition rate, and on the other hand, reduce the hydrogen content in the doped amorphous semiconductor layer 27, controlling porosity and reducing the probability of the doped amorphous semiconductor layer 27 bursting during crystallization.
[0102] In one embodiment, the volumetric flow rate ratio of silane, argon, and phosphine is between 22:40:1 and 22:55:1. Exemplarily, the volumetric flow rate ratio of silane, argon, and phosphine can be 22:40:1, 22:48:1, 22:52:1, 22:55:1, etc.
[0103] In one embodiment, the chamber pressure of the third plasma process is between 2700 mbar and 2900 mbar. Exemplarily, the chamber pressure of the third plasma process can be 2700 mbar, 2800 mbar, 2900 mbar, etc.
[0104] In one embodiment, the power of the third plasma process is between 12000W and 13000W. Exemplarily, the power of the third plasma process can be 12000W, 12500W, 12800W, 13000W, etc.
[0105] In one embodiment, the processing time of the third plasma process is between 3450s and 3550s. Exemplarily, the processing time of the third plasma process can be 3450s, 3500s, 3550s, etc.
[0106] In one embodiment, the processing temperature of the third plasma process is between 440°C and 455°C. Exemplarily, the processing temperature of the third plasma process can be 440°C, 450°C, 455°C, etc.
[0107] By setting the process parameters of the third plasma process within the aforementioned range, it is possible to promote the ionization of silane and increase the deposition rate, while also reducing the H content in the doped amorphous semiconductor layer 27, controlling the porosity, and reducing the probability of the doped amorphous semiconductor layer 27 bursting during crystallization.
[0108] In one embodiment, the process gas of the first plasma process includes nitrous oxide, and the volumetric flow rate of nitrous oxide is between 10,000 sccm and 12,000 sccm. Exemplarily, the volumetric flow rate of nitrous oxide can be 10,000 sccm, 11,000 sccm, or 12,000 sccm.
[0109] In one embodiment, the chamber pressure of the first plasma process is between 2700 mbar and 2900 mbar. Exemplarily, the chamber pressure of the first plasma process can be 2700 mbar, 2800 mbar, 2900 mbar, etc.
[0110] In one embodiment, the power of the first plasma process is between 15000W and 16000W. Exemplarily, the power of the first plasma process can be 15000W, 15500W, 16000W, etc.
[0111] In one embodiment, the processing time of the first plasma process is between 100s and 140s. Exemplarily, the processing time of the first plasma process can be 100s, 120s, 130s, 140s, etc.
[0112] In one embodiment, the processing temperature of the first plasma process is between 430°C and 450°C. Exemplarily, the processing temperature of the first plasma process can be 430°C, 440°C, 450°C, etc.
[0113] By keeping the process parameters of the first plasma process within the above range, it is beneficial to form a first tunneling layer 121 with better film quality and more uniform thickness.
[0114] It should be noted that the processing temperatures of the first, second, and third plasma processes are all between 400℃ and 500℃. Performing the first, second, and third plasma processes consecutively within the same cavity eliminates the need for repeated heating, as the processing temperatures of each stage are similar, thus reducing the fabrication time and cost of solar cell 1.
[0115] In one embodiment, reference Figure 5 As shown, a first conductive region 11a and a second conductive region 11b are provided on the semiconductor substrate 11 along a first direction X. The first direction X is perpendicular to the thickness direction of the semiconductor substrate 11. Furthermore, an isolation region 11c is also provided on the semiconductor substrate 11, and the isolation region 11c is located between the first conductive region 11a and the second conductive region 11b.
[0116] S400: A first tunneling layer 121 is formed on at least a portion of the first surface 111 using a first plasma process, specifically including the following steps:
[0117] S410: A first tunneling layer 121 is formed on the first surface 111 of the first conductive region 11a using a first plasma process. Specifically, refer to... Figure 8 As shown, a first tunneling material layer 26 is deposited on the side of the semiconductor substrate 11 near the first surface 111. The first tunneling material layer 26 covers the first conductive region 11a, the second conductive region 11b and the isolation region 11c. The first tunneling material layer 26 covering the first conductive region 11a forms the first tunneling layer 121.
[0118] In one embodiment, reference Figure 2 As shown, S100: After providing the semiconductor substrate 11, S400: Before forming the first tunneling layer 121 on at least a portion of the first surface 111 using a first plasma process, the following steps are also included:
[0119] S200: A second tunneling layer 131 is formed on the first surface 111 located in the second conductive region 11b. Specifically, refer to... Figure 3 As shown, a second tunneling material layer 21 is formed on the first surface 111 and the second surface 112. The second tunneling material layer 21 located in the second conductive region 11b and on the first surface 111 forms a second tunneling layer 131.
[0120] For example, the second tunneling layer 131 can be deposited by an LPCVD process. The material of the second tunneling layer 131 can be a dielectric material, such as silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, or titanium oxide.
[0121] S300: A second doped semiconductor layer 132 is formed on the side of the second tunneling layer 131 away from the semiconductor substrate 11. For example, refer to... Figure 3 As shown, firstly, a second intrinsic semiconductor material layer 22 (e.g., an intrinsic microcrystalline amorphous hybrid layer) is deposited on the second tunneling material layer 21 using an LPCVD process. Then, referring to... Figure 4 As shown, a semiconductor substrate 11 is placed in an annealing furnace, and a borosilicate glass layer 24 is deposited on the second intrinsic semiconductor material layer 22. The second intrinsic semiconductor material layer 22 is crystallized at a high temperature, and boron in the borosilicate glass layer 24 is doped into the second intrinsic semiconductor material layer 22, thereby forming a second doped semiconductor material layer 23. Next, referring to... Figure 5 As shown, a mask layer 25 is formed on the side where the first surface 111 is located, exposing the second doped semiconductor material layer 23 located in the isolation region 11c and the first conductive region 11a. Next, referring to... Figure 6 As shown, the borosilicate glass layer 24 on the second surface 112 and the borosilicate glass layer 24 on the first surface 111 located in the isolation region 11c and the first conductive region 11a are removed. Exemplarily, the borosilicate glass layer 24 can be removed using a hydrofluoric acid solution or a laser. Next, referring to... Figure 7 As shown, an alkaline solution is used to remove the mask layer 25, using the retained borosilicate glass layer 24 as a mask. An alkaline solution containing polishing agent is then used to remove the second tunneling material layer 21 and the second doped semiconductor material layer 23 from other areas, leaving the second tunneling material layer 21 and the second doped semiconductor material layer 23 in the second conductive region 11b intact. Next, the semiconductor substrate 11 is sequentially cleaned in an ammonia solution for 5 minutes, in a hydrochloric acid solution for 5 minutes, and in a hydrofluoric acid solution for 10 seconds. After cleaning, subsequent steps are performed.
[0122] In one embodiment, S410: Forming a first tunneling layer 121 on the first surface 111 of the first conductive region 11a using a first plasma process includes the following steps:
[0123] S411: A first tunneling material layer 26 is formed on the first surface 111 located between the first conductive region 11a and the isolation region 11c using a first plasma process. (Refer to...) Figure 8 As shown, a first tunneling material layer 26 located in the first conductive region 11a and on the first surface 111 forms a first tunneling layer 121, wherein the first tunneling material layer 26 also covers the retained borosilicate glass layer 24.
[0124] S600: After forming the first doped semiconductor layer 122 on the side of the first tunneling layer 121 away from the semiconductor substrate 11, S1000: Before forming the first electrode 141 in ohmic contact with the first doped semiconductor layer 122 on the side of the first doped semiconductor layer 122 away from the semiconductor substrate 11, the following steps are further included:
[0125] S700: Remove the first tunneling material layer 26 located in the isolation zone 11c, and form an isolation groove 15 on the first surface 111 located in the isolation zone 11c. Specifically, refer to... Figure 9 As shown, firstly, a laser is used to open the protective layer 28 of the isolation region 11c. During this process, a single-sided chain HF cleaning machine can also be used to remove the protective layer 28 deposited around the edges and sides of the second surface 112 of the semiconductor substrate 11. Next, referring to... Figure 10 As shown, the semiconductor substrate 11 is placed in an alkaline solution (such as ammonia and potassium hydroxide solution) containing polishing agent to remove the first tunneling layer 121 and the first doped semiconductor layer 122 of the isolation region 11c, and an isolation trench 15 is etched on the semiconductor substrate 11 to form an isolation trench 15 with a depth of about 3 μm.
[0126] S800: Texturing process is performed on the semiconductor substrate 11. Specifically, refer to... Figure 11 As shown, the semiconductor substrate 11 is first immersed in an alkaline solution (such as an ammonia solution) containing a texturing additive for texturing treatment. Next, referring to... Figure 12 As shown, hydrofluoric acid solution is used to remove the borosilicate glass layer 24 and the protective layer 28.
[0127] S900: A first passivation layer group 16 is formed on the side of the first doped semiconductor layer 122 away from the semiconductor substrate 11, and a second passivation layer group 17 is formed on the second surface 112. Exemplarily, passivation material layers 29 may be deposited on the first surface 111 and the second surface 112 respectively, with the passivation material layer 29 on the first surface 111 forming the first passivation layer group 16, and the passivation material layer 29 on the second surface 112 forming the second passivation layer group 17.
[0128] Optionally, an aluminum oxide layer with a thickness of 5nm-10nm is first deposited on the first surface 111 and the second surface 112 using an ALD process. Then, multiple silicon nitride layers are deposited on the first surface 111 and the second surface 112 using a PECVD process. The refractive index of the silicon nitride layers is between 2 and 2.3. The aluminum oxide layer and the silicon nitride layer on the first surface 111 constitute the first passivation layer group 16, and the aluminum oxide layer and the silicon nitride layer on the second surface 112 constitute the second passivation layer group 17.
[0129] After S900 is completed, S1000 is performed. It can be understood that in S1000, the first electrode 141 and the second electrode 142 can be formed simultaneously. (Refer to...) Figure 14 As shown, the first electrode 141 penetrates the first passivation layer group 16 and makes an ohmic contact with the first doped semiconductor layer 122, and the second electrode 142 penetrates the first passivation layer group 16 and makes an ohmic contact with the second doped semiconductor layer 132. The first electrode 141 and the second electrode 142 can be formed by coating and sintering, wherein the sintering temperature can be between 840℃ and 850℃.
[0130] It should be noted that, through testing, the inventors found that the solar cells prepared using the preparation method provided in the embodiments of this application have a PL brightness that is approximately 5000 higher than that prepared using conventional methods.
[0131] Secondly, referring to Figure 14 As shown, this application provides a solar cell 1, which can be fabricated by the method described above. The solar cell 1 can be a back contact (BC) cell, a tunnel oxide passivating contact (TOPCon) cell, or the like.
[0132] Specifically, the solar cell 1 includes a semiconductor substrate 11, a first tunneling layer 121, a first doped semiconductor layer 122, and a first electrode 141. The semiconductor substrate 11 includes a first surface 111 and a second surface 112 disposed opposite to each other. The first tunneling layer 121 is disposed on at least a portion of the first surface 111. The first doped semiconductor layer 122 is disposed on the side of the first tunneling layer 121 away from the semiconductor substrate 11. The first electrode 141 is disposed on the side of the first doped semiconductor layer 122 away from the semiconductor substrate 11 and is in ohmic contact with the first doped semiconductor layer 122.
[0133] The first tunneling layer 121 is configured to be hydrogenated by plasma process after being deposited using plasma process.
[0134] The solar cell 1 provided in this application, after forming a first tunneling layer 121 by plasma deposition, undergoes hydrogenation treatment of the first tunneling layer 121 by plasma process. This can reduce the density of unsaturated dangling bonds on the surface of the first tunneling layer 121, improve the passivation quality and passivation performance of the first tunneling layer 121, and thus help improve the cell efficiency.
[0135] In one embodiment, a first conductive region 11a, a second conductive region 11b, and an isolation region 11c are provided on the semiconductor substrate 11 along a first direction X, with the isolation region 11c located between the first conductive region 11a and the second conductive region 11b. The first direction X is perpendicular to the thickness direction of the semiconductor substrate 11. A first tunneling layer 121 is provided on the first surface 111 of the first conductive region 11a.
[0136] The solar cell 1 further includes a second tunneling layer 131, a second doped semiconductor layer 132, an isolation trench 15, a first passivation layer group 16, a second passivation layer group 17, and a second electrode 142. The second tunneling layer 131 is disposed on the first surface 111 located in the second conductive region 11b. The second doped semiconductor layer 132 is disposed on the side of the second tunneling layer 131 away from the semiconductor substrate 11. The isolation trench 15 is disposed on the first surface 111 located in the isolation region 11c. The first passivation layer group 16 is disposed on the side of the first doped semiconductor layer 122 and the second doped semiconductor layer 132 away from the semiconductor substrate 11, and the first passivation layer group 16 also covers the trench wall of the isolation trench 15. The second passivation layer group 17 is disposed on the second surface 112. The second electrode 142 penetrates the first passivation layer group 16 and is in ohmic contact with the second doped semiconductor layer 132.
[0137] Optionally, the first passivation layer group 16 includes a first passivation layer 161 and a first antireflection layer 162 stacked together, and the second passivation layer group 17 includes a second passivation layer 171 and a second antireflection layer 172 stacked together. The first passivation layer 161 and the second passivation layer 171 may be made of aluminum oxide, and the first antireflection layer 162 and the second antireflection layer 172 may be made of silicon nitride and silicon oxynitride.
[0138] In one embodiment, the solar cell 1 further includes a nitrogen-rich layer, with at least a portion of the surface of the first tunneling layer 121 on the side away from the semiconductor substrate 11 having the nitrogen-rich layer. It should be noted that during the hydrogenation treatment of the first tunneling layer 121 using the second plasma process, the bombardment of Ar ions can enhance the ionization of H in NH3, and the ionized H can reduce the density of unsaturated dangling bonds on the surface of the first tunneling layer 121. The ionized N in NH3 can form a nitrogen-rich layer on the surface of the first tunneling layer 121, blocking H leakage during metallization sintering, suppressing the decrease in passivation quality of the first tunneling layer 121 during sintering, and the N in the nitrogen-rich layer can enhance the energy of the Si-H bonds, further improving the electrical performance and thermal stability of the first doped semiconductor layer 122. It is understood that the nitrogen-rich layer is a film containing nitrogen.
[0139] Thirdly, embodiments of this application provide a photovoltaic module, including a solar cell in any of the second-direction embodiments.
[0140] For example, the photovoltaic module includes multiple solar cells, which can be wired together in series via solder strips to collect the electrical energy generated by each individual solar cell for subsequent transmission. Of course, the solar cells can be arranged at intervals or stacked together in a shingled configuration.
[0141] Furthermore, the photovoltaic module also includes an encapsulation layer and a cover plate. The encapsulation layer covers the surface of the cell string, and the cover plate covers the surface of the encapsulation layer away from the cell string. Solar cells are electrically connected in a single unit or in multiple segments to form multiple cell strings, which are electrically connected in series and / or parallel. Specifically, in some embodiments, multiple cell strings can be electrically connected through conductive links. The encapsulation layer covers the surface of the solar cell. Exemplarily, the encapsulation layer can be an organic encapsulation film such as an ethylene-vinyl acetate copolymer film, a polyethylene octene co-elastomer film, or a polyethylene terephthalate film. The cover plate can be a light-transmitting cover plate such as a glass cover plate or a plastic cover plate.
[0142] It should be understood that, in the embodiments of this application, at least some of the steps in the accompanying drawings may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0143] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0144] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for preparing a solar cell, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface disposed opposite to each other; A first tunneling layer is formed on at least a portion of the first surface using a first plasma process; the first tunneling layer includes silicon oxide, aluminum oxide, silicon nitride, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, or titanium oxide; The first tunneling layer is hydrogenated using a second plasma process; wherein, in the second plasma process, a nitrogen-rich layer is also formed on the surface of the first tunneling layer; the process gas of the second plasma process includes ammonia and argon; the volumetric flow rate ratio of the ammonia and argon is between 3:1 and 2:1; the chamber pressure of the second plasma process is between 1200 mbar and 1500 mbar; the power of the second plasma process is between 11000 W and 13000 W; the processing time of the second plasma process is between 50 s and 60 s; and the processing temperature of the second plasma process is between 440℃ and 455℃. A first doped semiconductor layer is formed on the side of the first tunneling layer away from the semiconductor substrate; A first electrode is formed on the side of the first doped semiconductor layer away from the semiconductor substrate, making ohmic contact with the first doped semiconductor layer.
2. The method for preparing a solar cell according to claim 1, characterized in that, The formation of a first doped semiconductor layer on the side of the first tunneling layer away from the semiconductor substrate includes: A doped amorphous semiconductor layer is formed on the side of the first tunneling layer away from the semiconductor substrate using a third plasma process; A protective layer is formed on the side of the doped amorphous semiconductor layer away from the semiconductor substrate; The doped amorphous semiconductor layer is crystallized to form the first doped semiconductor layer.
3. The method for preparing a solar cell according to claim 2, characterized in that, The first plasma process, the second plasma process, and the third plasma process all use the same plasma equipment.
4. The method for preparing a solar cell according to claim 2, characterized in that, The process gases of the third plasma process include silane, argon and phosphine, and the volume flow ratio of silane, argon and phosphine is between 22:40:1 and 22:55:
1. And / or, the cavity pressure of the third plasma process is between 2700 mbar and 2900 mbar; And / or, the power of the third plasma process is between 12000W and 13000W; And / or, the processing time of the third plasma process is between 3450s and 3550s; And / or, the processing temperature of the third plasma process is between 440°C and 455°C.
5. The method for preparing a solar cell according to claim 1, characterized in that, The process gas for the first plasma process includes nitrous oxide, and the volumetric flow rate of the nitrous oxide is between 10,000 sccm and 12,000 sccm. And / or, the cavity pressure of the first plasma process is between 2700 mbar and 2900 mbar; And / or, the power of the first plasma process is between 15000W and 16000W; And / or, the processing time of the first plasma process is between 100s and 140s; And / or, the processing temperature of the first plasma process is between 430°C and 450°C.
6. The method for preparing a solar cell according to any one of claims 1-5, characterized in that, The semiconductor substrate has a first conductive region and a second conductive region arranged along a first direction; the first direction is perpendicular to the thickness direction of the semiconductor substrate. The formation of a first tunneling layer on at least a portion of the first surface using a first plasma process includes: A first tunneling layer is formed on the first surface located in the first conductive region using a first plasma process.
7. The method for preparing a solar cell according to claim 6, characterized in that, After providing the semiconductor substrate, and before forming the first tunneling layer on at least a portion of the first surface using a first plasma process, the process includes: A second tunneling layer is formed on the first surface located in the second conductive region; A second doped semiconductor layer is formed on the side of the second tunneling layer away from the semiconductor substrate.
8. The method for preparing a solar cell according to claim 6, characterized in that, An isolation region is further provided on the semiconductor substrate, and the isolation region is located between the first conductive region and the second conductive region; The step of forming a first tunneling layer on the first surface located in the first conductive region using a first plasma process includes: forming a first tunneling material layer on the first surface located in the first conductive region and the isolation region using a first plasma process; wherein the first tunneling material layer located in the first conductive region and on the first surface forms the first tunneling layer. After forming a first doped semiconductor layer on the side of the first tunneling layer away from the semiconductor substrate, and before forming a first electrode in ohmic contact with the first doped semiconductor layer on the side of the first doped semiconductor layer away from the semiconductor substrate, the process includes: Remove the first tunneling material layer located in the isolation zone and form an isolation groove on the first surface located in the isolation zone; The semiconductor substrate is texturized. A first passivation layer group is formed on the side of the first doped semiconductor layer away from the semiconductor substrate, and a second passivation layer group is formed on the second surface.
9. A solar cell, characterized in that, The solar cell is manufactured using the method for preparing a solar cell according to any one of claims 1-8, wherein the solar cell comprises: A semiconductor substrate, including a first surface and a second surface disposed opposite to each other; A first tunnel layer is disposed on at least a portion of the first surface; A first doped semiconductor layer is disposed on the side of the first tunneling layer away from the semiconductor substrate; and The first electrode is disposed on the side of the first doped semiconductor layer away from the semiconductor substrate and is in ohmic contact with the first doped semiconductor layer.
10. The solar cell according to claim 9, characterized in that, The semiconductor substrate has a first conductive region, a second conductive region, and an isolation region arranged along a first direction, with the isolation region located between the first conductive region and the second conductive region; the first direction is perpendicular to the thickness direction of the semiconductor substrate. The first tunneling layer is disposed on the first surface located in the first conductive region; The solar cell also includes: The second tunneling layer is disposed on the first surface located in the second conductive region; A second doped semiconductor layer is disposed on the side of the second tunneling layer away from the semiconductor substrate; An isolation groove is disposed on the first surface located in the isolation zone; A first passivation layer group is disposed on the side of the first doped semiconductor layer and the second doped semiconductor layer away from the semiconductor substrate; A second passivation layer group is disposed on the second surface; The second electrode penetrates the first passivation layer group and is in ohmic contact with the second doped semiconductor layer.
11. The solar cell according to claim 9, characterized in that, The solar cell further includes a nitrogen-rich layer, which is disposed on at least a portion of the surface of the first tunneling layer away from the semiconductor substrate.
12. A photovoltaic module, characterized in that, Including the solar cell as described in any one of claims 9-11.