Chip packaging structure

Abstract

The embodiment of the present application provides a chip packaging structure, including a core encapsulation unit, and twelve memories connected to the core encapsulation unit; the core encapsulation unit includes one or two main core rows, each main core row includes a first main core and a second main core adjacent to each other on short sides; the twelve memories are evenly distributed on both sides of the long side of the core encapsulation unit and arranged in a row direction, or a part of the twelve memories are distributed on one side or both sides of the long side of the core encapsulation unit and arranged in a row direction, and the other part is distributed on one side or both sides of the short side of the core encapsulation unit and arranged in a row direction. By applying the chip packaging structure, large-capacity, high-bandwidth data exchange can be achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip packaging structure. Background Art

[0002] With the continuous reduction of integrated circuit process technology and the continuous improvement of integration, chip manufacturing has approached the physical limit. The space for further improving chip performance by simply reducing the size of transistors is gradually shrinking, which will also lead to a rapid increase in manufacturing costs and complexity. In addition, with the influence of various factors such as chip heat dissipation, transmission bandwidth, and manufacturing yield, the performance improvement of a single chip has been limited.

[0003] As Moore's Law in chip manufacturing gradually becomes ineffective, chiplet technology has gradually become the most promising technology field in the post-Moore era. Chiplet technology is a method of designing and manufacturing integrated circuits that separates the functions of each module in the SOC (System on Chip) chip into multiple smaller independent units, which are called chiplets. Each chiplet can contain specific functional blocks, processor cores, memory units or other components. The chiplets are packaged through high-density interconnections to achieve or exceed the performance of existing SOCs.

[0004] The core idea of ​​core chip technology is to split large integrated circuits into smaller, more modular parts to design, manufacture and assemble chips more flexibly. It breaks through the bottleneck of single chip lithography area and reduces dependence on advanced process technology. It improves chip performance and reduces manufacturing costs.

[0005] As high-performance chips such as GPUs (Graphics Processing Units) become more powerful, chips need to access data from memory faster to shorten application processing time. For example, AI (Artificial Intelligence) and vision fields have extremely high requirements for memory capacity, computing power, and bandwidth performance. Therefore, how to improve the bandwidth and memory capacity of chip packaging structures has become a key issue facing chiplet technology. Summary of the invention

[0006] The purpose of the embodiment of the present application is to provide a chip packaging structure to achieve large-capacity, high-bandwidth data exchange. The specific technical solution is as follows:

[0007] The present application provides a chip packaging structure, comprising: a chip packaging unit, and twelve memories connected to the chip packaging unit;

[0008] The core particle packaging unit includes one or two main core particle rows, each of which includes a first main core particle and a second main core particle adjacent to each other at short sides;

[0009] The twelve memories are evenly distributed on both sides of the long side of the core encapsulation unit and arranged in rows, or a part of the twelve memories are distributed on one side or both sides of the long side of the core encapsulation unit and arranged in columns, and another part of the twelve memories are distributed on one side or both sides of the short side of the core encapsulation unit and arranged in columns.

[0010] Optionally, when the chip encapsulation unit includes a main chip row, the twelve memories are arranged in any of the following ways:

[0011] The twelve memories are evenly distributed on both sides of the long side direction of the chip packaging unit;

[0012] Eight of the twelve memories are evenly distributed on both sides of the long side of the core encapsulation unit, and the other four memories are evenly distributed on both sides of the short side of the core encapsulation unit; four of the eight memories are evenly distributed on both sides of the first main core, and the other four are symmetrically distributed on both sides of the second main core.

[0013] Optionally, when the chip encapsulation unit includes two main chip rows, the twelve memories are arranged in any of the following ways:

[0014] The twelve memories are evenly distributed on both sides of the long side direction of the chip packaging unit;

[0015] Eight of the twelve memories are evenly distributed on both sides of the long side of the core encapsulation unit, and the other four memories are evenly distributed on both sides of the short side of the core encapsulation unit; four of the eight memories located on both sides of the long side of the core encapsulation unit are evenly distributed on both sides of the first main core, and the other four are evenly distributed on both sides of the second main core;

[0016] Four of the twelve memories are evenly distributed on both sides of the long side of the core encapsulation unit, and the other eight memories are evenly distributed on both sides of the short side of the core encapsulation unit; two of the four memories located on both sides of the long side of the core encapsulation unit are respectively located on both sides of the first main core, and the other two are respectively located on both sides of the second main core.

[0017] Optionally, when the twelve memories are evenly distributed on both sides of the long side of the chip encapsulation unit, the chip encapsulation structure further includes: a first input-output chip and a second input-output chip respectively located on both sides of the short side of the chip encapsulation unit;

[0018] The first input-output core particle is close to the first main core particle and connected to the first main core particle, and the second input-output core particle is close to the second main core particle and connected to the second main core particle.

[0019] Optionally, the chip packaging structure further includes: horizontally interconnected input-output core particles and / or vertically interconnected input-output core particles;

[0020] The lateral interconnection type input and output chip is located at one side of the long side direction of the chip encapsulation unit, and is respectively connected to two adjacent main chips in the row direction of the chip encapsulation unit;

[0021] The vertically interconnected input / output chip is located at one side of the short side direction of the chip encapsulation unit, and is respectively connected to two adjacent main chips in the column direction within the chip encapsulation unit.

[0022] Optionally, when the number of memories distributed on one side of the long side of the chip encapsulation unit is not greater than four, the lateral interconnection type input-output chip comprises: a third input-output chip located on the one side of the long side of the chip encapsulation unit;

[0023] The third input-output chip is arranged in a row queue with the memory located on the side of the long side of the chip packaging unit, and the projection of the third input-output chip in the row direction overlaps with the projection of the first main chip in the row direction and the projection of the second main chip in the row direction; the third input-output chip is connected to the first main chip and the second main chip respectively.

[0024] Optionally, when the chip encapsulation unit includes two main chip rows, and the number of memories distributed on one side of the short side of the chip encapsulation unit is not greater than two, the vertically interconnected input-output chip includes: a fourth input-output chip located on the one side of the short side;

[0025] The fourth input-output chip is arranged in a column queue with the memory located on the side of the short side of the chip packaging unit, and the projection of the fourth input-output chip in the column direction overlaps with the projection of the two main chip rows in the column direction; and the fourth input-output chip is respectively connected to the main chip located on the side of the two main chip rows.

[0026] Optionally, the chip packaging structure further includes non-functional core particles, and the non-functional core particles are distributed at corners around the core particle packaging unit.

[0027] Optionally, the chip packaging structure further includes a substrate and an interposer;

[0028] The interposer is arranged on the substrate, the chip encapsulation unit and the memory are arranged on a side of the interposer away from the substrate, and adjacent main chips in the chip encapsulation unit are interconnected through the interposer.

[0029] Optionally, the memory is HBM.

[0030] Beneficial effects of the embodiments of the present application:

[0031] The chip packaging structure provided in the embodiment of the present application optimizes the combination arrangement scheme between the main core particles and the memory. One or two main core particle rows are set in the chip packaging structure, and each main core particle row includes a first main core particle and a second main core particle adjacent to each other on short sides. Therefore, when the memory is set around the one or two main core particle rows, twelve memories can be arranged, thereby increasing the number of memories that can be integrated in the chip packaging structure, thereby increasing the overall content bandwidth and capacity of the chip packaging structure.

[0032] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0034] Figure 1 A schematic diagram of a chip packaging structure in the related art;

[0035] Figure 2 Another schematic diagram of a chip packaging structure in the related art;

[0036] Figure 3 A first schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0037] Figure 4 A second schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0038] Figure 5 A third schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0039] Figure 6 A fourth schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0040] Figure 7 A fifth schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0041] Figure 8 A sixth schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0042] Fig. 9 A seventh schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0043] Reference numerals:

[0044] Main core-11, first main core-11a, second main core-11b, memory-12, first input-output core-13a, second input-output core-13b, non-functional core-14, third input-output core-15a, fourth input-output core-15b, fifth input-output core-16a, sixth input-output core-16b, intermediate layer-2, substrate-3. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0046] In the existing packaging technology, the main chip and the memory are generally interconnected and packaged as a whole to achieve large-capacity, high-bandwidth data exchange. However, when combining the main chip and the memory, the available packaging solutions are very limited, generally 1+6 and 2+8.

[0047] The 1+6 packaging solution is as follows: Figure 1 As shown, it includes a substrate 3, an interposer 2 arranged on the substrate 3, and a main core particle 11 arranged on a side of the interposer 2 away from the substrate, and three memories 12 are connected to the left and right sides of the main core particle 11 respectively.

[0048] In the current 2.5D packaging technology, in order to integrate more memories, the conventional solution is to continue to increase the area of ​​the main chip, so that more memory interfaces can be designed on both sides of the main chip to connect more memories while improving the performance of the main chip. Based on this solution, the number of memories connected to both sides of the main chip can be increased from 6 to 8, resulting in an improved 1+8 packaging solution.

[0049] The 2+8 packaging solution is as follows Figure 2As shown, it includes a substrate 3, an interposer 2 disposed on the substrate 3, and two main core particles 11 disposed on the side of the interposer 2 away from the substrate, and the two main core particles 11 are respectively connected to four memories 12. The 2+8 packaging solution divides a large main core particle into two small main core particles, and interconnects the two main core particles through D2D (Die to Die, chip interconnection technology) technology, so that the area of ​​performance carried by each main core particle is reduced to break the pain point of chip design and manufacturing. In the 2+8 packaging solution, the number of memories interconnected by a single main core particle is reduced, but the number of memories in the overall packaging structure is increased from 6 to 8, and the performance and memory of the overall chip are increased.

[0050] However, in the above two solutions, the amount of memory that can be integrated is still very limited, and cannot meet the bandwidth and capacity requirements of chip memory in many application scenarios today.

[0051] In view of this, the present application embodiment provides a chip packaging structure, see Figures 3 to 9 , the chip packaging structure provided in the embodiment of the present application includes: a chip packaging unit, and twelve memories 12 connected to the chip packaging unit;

[0052] The chip encapsulation unit includes one or two main chip rows, and each main chip row includes a first main chip 11 a and a second main chip 11 b adjacent to each other at short sides.

[0053] Among them, the main core particle is the main module of the chip, usually a module chip such as GPU (Graphics Processing Unit), CPU (Central Processing Unit), NPU (Neural Network Processing Unit), DPU (Data Processing Unit), etc. In the chip packaging structure provided in the embodiment of the present application, each two adjacent main core particles in the chip packaging unit are interconnected through D2D technology, and the specific content of D2D technology can refer to the relevant technology.

[0054] The memory 12 may adopt a conventional DRAM (Dynamic Random Access Memory) such as DDR (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power Double Data Rate), or may adopt HBM (High Bandwidth Memory).

[0055] In one embodiment of the present application, the memory 12 is preferably HBM. Compared with traditional DRAM, HBM uses TSV (Through Silicon Via) technology to connect multiple DRAMs together and interconnect with the main core particles, which can provide the chip with more I / O (input / output) numbers, higher bandwidth, larger memory capacity, lower power consumption, smaller size, and lower latency, which highlights the advantages when processing large amounts of data and high-speed computing scenarios. At present, HBM has been used in HPC (High Performance Computing), AI and machine learning, data centers, GPUs, automotive industries and other multi-chip fields to accelerate scientific research and complex computing tasks, speed up neural network processing and large amounts of data analysis, speed up data transmission speeds and graphics-intensive applications, etc.

[0056] For example, the main core particles mentioned above can be packaged together with the memory 12 by using CoWoS (Chip-on-Wafer-on-Substrate with Siinterposer, a chip packaging technology) 2.5D packaging technology.

[0057] When the twelve memories 12 are specifically laid out, the twelve memories 12 can be evenly distributed on both sides of the long side direction (i.e., the row direction) of the chip encapsulation unit and arranged in a queue along the row direction, or a part of the twelve memories 12 can be distributed on one side or both sides of the long side direction of the chip encapsulation unit and arranged in a queue along the column direction, and the other part can be distributed on one side or both sides of the short side direction (i.e., the column direction) of the chip encapsulation unit and arranged in a queue along the column direction.

[0058] Considering the general specifications of the main chip and HBM, the arrangement of the twelve memories 12 can be designed under the following conditions: the number of memories 12 on one side of the long side of each main chip does not exceed 3, and the number of memories 12 on one side of the short side does not exceed 2. Preferably, when designing the arrangement of the twelve memories 12, the chip packaging structure can be symmetrical in both the row direction and the column direction to ensure that the chip packaging structure has good structural performance.

[0059] Combine the following Figures 3 to 9 The several specific arrangements of the main chip and the twelve memories 12 that can be selected are given in the specification to further describe the chip packaging structure provided in the embodiment of the present application in detail.

[0060] Figures 3 to 5 The illustrated chip packaging structure includes a main chip row, in which a first main chip 11 a and a second main chip 11 b are interconnected by a D2D technology.

[0061] exist Figure 3 In the illustrated structure, twelve memories 12 are evenly distributed on both sides of the long side of the chip packaging unit. Figure 3 The schematic structure can be divided into two symmetrical areas A and B by the dotted lines in the figure. The first main core particle 11a is interconnected with the six memories 12 in the A area through the HBM interface, and the second main core particle 11b is interconnected with the six memories 12 in the B area through the HBM interface. The interconnection technology between the memory 12 and the main core particle can refer to the contents in the relevant technology.

[0062] Figure 4 The structure shown is Figure 3 On the basis of the structure in the middle, it further includes a first input-output core particle 13a and a second input-output core particle 13b located on both sides of the short side direction of the core particle packaging unit. The first input-output core particle 13a is close to the first main core particle 11a and is interconnected with the first main core particle 11a through the D2D technology, and the second input-output core particle 13b is close to the second main core particle 11b and is interconnected with the second main core particle 11b through the D2D technology.

[0063] The input-output chip (IO die) is also called the coordinated data forwarding chip. It is used to realize the interconnection between the chip packaging structure and the external structure. It is a dedicated interconnection chip.

[0064] By removing the input and output modules in the main core particle and designing them as dedicated input and output core particles, the area in the main core particle originally used to implement the input and output functions can be saved, thereby providing more memory interface space. When the input and output modules in the main core particle are removed, the main core particle can still be maintained at its original size, so that the main core particle can carry stronger performance, or, while ensuring that each main core particle can provide six memory interfaces, the size of each main core particle can be appropriately reduced (for example, the size of each main core particle in the column direction can be appropriately reduced), thereby helping to avoid the design and manufacture of large-sized core particles and reduce the manufacturing cost of core particles.

[0065] Moreover, by designing dedicated input and output core particles in the chip packaging structure, it is also easier to carry out targeted design of the input and output core particles according to the actual interconnection protocol between the chip packaging structure and the external structure during the design phase, which is more helpful to meet the different requirements for the chip packaging structure in different application scenarios.

[0066] In addition, Figure 4 , and subsequent Figure 5 , Figures 7 to 9 The illustrated structure also includes: non-functional core particles (Dummy Die) 14 distributed at the corners around the core particle packaging unit.

[0067] The non-functional core particles 14 are only structural components and are not used to achieve specific functions. For example, a silicon block without a circuit structure can be used as the non-functional core particle 14. Placing the non-functional core particles 14 at the four corners of the chip packaging structure helps to optimize the entire chip packaging structure and make it have good anti-warping performance.

[0068] Furthermore, in some embodiments of the present application, the chip packaging structure further includes: horizontally interconnected input-output core particles and / or vertically interconnected input-output core particles;

[0069] The lateral interconnection type input and output chip is located on one side of the long side direction of the chip encapsulation unit, and is respectively connected to two adjacent main chips in the row direction of the chip encapsulation unit;

[0070] The vertically interconnected input-output chip is located on one side of the short side of the chip packaging unit, and is respectively connected to two adjacent main chips in the column direction within the chip packaging unit.

[0071] The above-mentioned lateral interconnection type input-output core particles and vertical interconnection type input-output core particles are not only used to realize the interconnection function between the chip packaging structure and the external structure, but also can realize the interconnection between the internal main core particles, thereby improving the interconnection bandwidth between the main core particles.

[0072] Specifically, when the number of memories 12 distributed on one side of the long side of the chip encapsulation unit is not more than four, a third input-output chip 15a can be set on the side of the long side as a horizontally interconnected input-output chip; when the chip encapsulation unit includes two main chip rows, and the number of memories 12 distributed on one side of the short side of the chip encapsulation unit is not more than two, a fourth input-output chip 15b can be set on the side of the short side as a vertically interconnected input-output chip. This is described below in conjunction with a specific embodiment.

[0073] exist Figure 5 In the illustrated structure, eight of the twelve memories 12 are evenly distributed on both sides of the long side of the chip encapsulation unit, and the other four memories 12 are evenly distributed on both sides of the short side of the chip encapsulation unit. Four of the eight memories 12 distributed on both sides of the long side of the chip encapsulation unit are evenly distributed on both sides of the first main chip 11a, and the other four are evenly distributed on both sides of the second main chip 11b.

[0074] and Figure 3 , Figure 4 The structure is similar to Figure 5 In the illustrated structure, six memories 12 surrounding the first main core particle 11 a are interconnected with the first main core particle 11 a , and six memories 12 surrounding the second main core particle 11 b are interconnected with the second main core particle 11 b .

[0075] Figure 5 The chip packaging unit further includes two third input-output chips 15a located on both sides of the long side direction, located Figure 5 A third input-output chip 15a in the upper part is arranged in a row with the other four memories 12 in the horizontal direction, and the projection of the third input-output chip 15a in the row direction overlaps with the projection of the first main chip 11a in the row direction and the projection of the second main chip 11b in the row direction. Figure 5 Similarly, a third input-output chip 15a in the lower half is arranged in a row queue with the other four memories 12 in the horizontal direction, and the projection of the third input-output chip 15a in the row direction overlaps with the projection of the first main chip 11a in the row direction and the projection of the second main chip 11b in the row direction.

[0076] The two third input-output core particles 15a are interconnected with the first main core particle 11a and the second main core particle 11b respectively. Figure 5In the schematic structure, in addition to being able to be directly interconnected through the D2D technology, the first main core particle 11a and the second main core particle 11b can also use the interconnection function of the third input-output core particle 15a to achieve interconnection through the path of "first main core particle 11a-third input-output core particle 15a-second main core particle 11b", thereby improving the interconnection bandwidth between the first main core particle 11a and the second main core particle 11b.

[0077] Figures 6 to 9 The illustrated chip packaging structure includes two main chip rows, and adjacent main chip rows in the two main chip rows are interconnected by D2D technology. For ease of explanation, the four main chip rows in the two main chip rows are marked as D1, D2, D3 and D4 in clockwise direction.

[0078] exist Figure 6 In the illustrated structure, twelve memories 12 are evenly distributed on both sides of the long side of the chip packaging unit. Figure 6 The schematic structure can be divided into four areas C, D, E and F by the dotted lines in the figure. The main core particle D1 is interconnected with the three memories 12 in the C area, the main core particle D2 is interconnected with the three memories 12 in the D area, the main core particle D3 is interconnected with the three memories 12 in the E area, and the main core particle D4 is interconnected with the three memories 12 in the F area.

[0079] Figure 7 The structure shown is Figure 6 On the basis of the structure in the middle, it further includes two first input-output core particles 13a and two second input-output core particles 13b located on both sides of the short side direction of the core particle packaging unit. The first input-output core particles in the first row are interconnected with the main core particle D1, the first input-output core particles in the second row are interconnected with the main core particle D4, the second input-output core particles in the first row are interconnected with the main core particle D2, and the second input-output core particles in the second row are interconnected with the main core particle D3.

[0080] exist Figure 8 In the illustrated structure, eight of the twelve memories 12 are evenly distributed on both sides of the long side of the chip encapsulation unit, and the other four memories 12 are evenly distributed on both sides of the short side of the chip encapsulation unit. Four of the eight memories 12 located on both sides of the long side of the chip encapsulation unit are evenly distributed on both sides of the first main chip 11a, and the other four are evenly distributed on both sides of the second main chip 11b.

[0081] and Figure 6 , Figure 7 The structure is similar to Figure 8 In the illustrated structure, each main chip in D1, D2, D3 and D4 is interconnected with three memories 12 around it.

[0082] and, Figure 8The schematic structure further includes two third input-output chips 15a located on both sides of the long side of the chip packaging unit, and two fourth input-output chips 15b located on both sides of the short side of the chip packaging unit.

[0083] The arrangement and function of the two third input and output core particles 15a are similar to Figure 5 The diagram in is similar. Figure 8 The fourth input-output chip 15b on the left side is arranged in a row with the other two memories 12 in the vertical direction, and the projection of the fourth input-output chip 15b in the column direction overlaps with the projection of the two main chip rows in the column direction. Figure 8 The fourth input-output chip 15b on the right side is arranged in a row with the other two memories 12 in the vertical direction, and the projection of the fourth input-output chip 15b in the column direction overlaps with the projection of the two main chip rows in the column direction.

[0084] In the above two third input-output core particles 15a and two fourth input-output core particles 15b, Figure 8 The third input-output core 15a in the upper part is interconnected with the main cores D1 and D2 respectively, and is located at Figure 8 The third input-output core 15a in the lower part is interconnected with the main cores D3 and D4 respectively, and is located at Figure 8 The fourth input-output chip 15b on the left is interconnected with the main chips D1 and D4 respectively. Figure 8 The fourth input-output core particle 15b on the right is interconnected with the main core particles D2 and D3 respectively. Figure 8 In the illustrated structure, adjacent main core particles in the row direction or column direction can be directly interconnected through the D2D technology, and can also be interconnected by connecting the input and output core particles of the adjacent main core particles, thereby improving the interconnection bandwidth between the main core particles.

[0085] exist Fig. 9 In the illustrated structure, four memories 12 out of the twelve memories 12 are evenly distributed on both sides of the long side of the chip encapsulation unit, and the other eight memories 12 are evenly distributed on both sides of the short side of the chip encapsulation unit; two of the four memories 12 located on both sides of the long side of the chip encapsulation unit are respectively located on both sides of the first main core particle 11a, and the other two are respectively located on both sides of the second main core particle 11b.

[0086] and Figures 6 to 8 The structure is similar to Fig. 9 In the illustrated structure, each main chip in D1, D2, D3 and D4 is interconnected with three memories 12 around it.

[0087] And in Fig. 9The schematic structure also includes two fifth input-output core particles 16a and two sixth input-output core particles 16b located on both sides of the long side of the core particle packaging unit. Fig. 9 A fifth input-output chip 16a in the upper part is interconnected with the main chip D1 and is located at Fig. 9 A fifth input-output chip 16a in the lower part is interconnected with the main chip D4 and is located at Fig. 9 A sixth input-output chip 16b in the upper part is interconnected with the main chip D2 and is located at Fig. 9 A sixth input-output chip 16b in the lower half is interconnected with the main chip D3.

[0088] In addition, the above Figures 3 to 9 The chip packaging unit shown in the figure also includes a substrate 3 and an interposer 2. The interposer 2 is arranged on the substrate 3, and each main core particle in the core particle packaging unit and the aforementioned twelve memories 12 are arranged on the side of the interposer 2 away from the substrate 3. For this structure, the adjacent main core particles in the core particle packaging unit, the main core particles and the input and output core particles, and the main core particles and the memories 12 can be interconnected through the interposer 2. How to realize the interconnection between these structures through the interposer 2 can refer to the contents in the relevant technology.

[0089] Exemplarily, the intermediate layer 2 may be a silicon adapter plate or a redistribution layer.

[0090] Based on the above description, it can be seen that the chip packaging structure provided in the above embodiment of the present application optimizes the combination arrangement scheme between the main core particles and the memory. One or two main core particle rows are set in the chip packaging structure, and each main core particle row includes a first main core particle and a second main core particle adjacent to each other on the short sides. Therefore, when the memory is set around the one or two main core particle rows, twelve memories can be arranged, thereby increasing the number of memories that can be integrated in the chip packaging structure, thereby increasing the overall content bandwidth and capacity of the chip packaging structure.

[0091] Below Figure 7 The chip packaging structure shown is an example, and the interconnection scheme adopted by the chip packaging structure provided in the embodiment of the present application is briefly described.

[0092] Figure 7 The schematic chip package structure includes four types of cores: four main cores, 12 memories, four input-output cores, and four non-functional cores, for a total of 24 cores.

[0093] The upper side of the main chip D1 is interconnected with three memories 12, the left side is interconnected with a first input-output chip 13a through the D2D technology, and the right side and the lower side are interconnected with the main chips D2 and D3 respectively through the D2D technology.

[0094] If the D2D interface on the left side of the main chip D1 is compatible with the D2D interface on the right side, then D2 can be obtained by translating D1 to the right, and the second input-output chip 13b interconnected with D2 can be obtained by rotating the first input-output chip 13a interconnected with D1 by 180 degrees. The upper side of D2 is interconnected with three memories 12, the left D2D interface is compatible with the D2D interface on the right side of D1, and the right side of D2 is interconnected with the second input-output chip 13b through the D2D interface.

[0095] D4 can be obtained by rotating D1 by 180 degrees, and the first input-output core particle 13a interconnected with D4 can be obtained by translating downward the first input-output core particle 13a interconnected with D1. D3 can be obtained by translating D4 to the right, and the second input-output core particle 13b interconnected with D3 can be obtained by rotating the first input-output core particle 13a interconnected with D4 by 180 degrees.

[0096] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0097] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0098] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A chip packaging structure, characterized in that: include: A chip encapsulation unit, and twelve memories connected to the chip encapsulation unit; The core particle packaging unit includes one or two main core particle rows, each of which includes a first main core particle and a second main core particle adjacent to each other on short sides; each two adjacent main core particles are interconnected by D2D technology; When the chip packaging structure includes a main core particle row, eight of the twelve memories are evenly distributed on both sides of the long side of the core particle packaging unit, and the other four memories are evenly distributed on both sides of the short side of the core particle packaging unit; four of the eight memories located on both sides of the long side of the core particle packaging unit are evenly distributed on both sides of the first main core particle, and the other four are symmetrically located on both sides of the second main core particle; the chip packaging structure also includes horizontally interconnected input-output core particles located on both sides of the long side of the chip packaging unit; the horizontally interconnected input-output core particles located on one side of the long side of the chip packaging unit are arranged in a row queue with the memories on this side, and the projection of the horizontally interconnected input-output core particles in the row direction overlaps with the projection of the first main core particle in the row direction and the projection of the second main core particle in the row direction, and the horizontally interconnected input-output core particles are connected to the first main core particle and the second main core particle respectively; When the chip packaging structure includes two main core grain rows, eight of the twelve memories are evenly distributed on both sides of the long side of the core grain packaging unit, and the other four memories are evenly distributed on both sides of the short side of the core grain packaging unit; four of the eight memories located on both sides of the long side of the core grain packaging unit are evenly distributed on both sides of the first main core grain, and the other four are evenly distributed on both sides of the second main core grain; the chip packaging structure also includes horizontally interconnected input-output core grains located on both sides of the long side of the chip packaging unit, and vertically interconnected input-output core grains located on both sides of the short side of the chip packaging unit; horizontally interconnected input-output core grains located on one side of the long side of the chip packaging unit The input-output chiplets are arranged in a row queue with the memory on the side, and the projection of the horizontally interconnected input-output chiplets in the row direction overlaps with the projection of the first main chiplets in the row direction and the projection of the second main chiplets in the row direction, and the horizontally interconnected input-output chiplets are connected to the first main chiplets and the second main chiplets respectively; the vertically interconnected input-output chiplets located on one side of the short side of the chip packaging unit are arranged in a column queue with the memory on the side, and the projection of the vertically interconnected input-output chiplets in the column direction overlaps with the projection of the two main chiplet rows in the column direction, and the vertically interconnected input-output chiplets are connected to the main chiplets located on the side of the two main chiplet rows respectively; The horizontally interconnected input-output core particles and the vertically interconnected input-output core particles are used to realize the interconnection between the chip packaging structure and the external structure, and the interconnection between the main core particles.

2. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure also includes non-functional core particles, and the non-functional core particles are distributed at the corners around the core particle packaging unit.

3. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure also includes a substrate and an interposer; The interposer is arranged on the substrate, the chip encapsulation unit and the memory are arranged on a side of the interposer away from the substrate, and adjacent main chips in the chip encapsulation unit are interconnected through the interposer.

4. The chip packaging structure according to claim 1, characterized in that: The memory is a high bandwidth memory HBM.

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