Silicon wafer cutting process
Patent Information
- Application Number
- CN202411454887.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-17
- Publication Date
- 2026-09-01
- Estimated Expiration
- 2044-10-17
AI Technical Summary
[0004]本发明的主要目的在于提供一种硅片切割工艺,以解决现有技术中太阳能硅片的表面粗糙度较高手感较差的问题
[0015]According to the technical solution of this invention, the silicon wafer dicing process includes a pretreatment stage, a first stage, a second stage, and a third stage. A dicing wire is sequentially wound and installed on a first reel, a first roller, a second roller, and a second reel to form a wire mesh between the first and second rollers. The speed of the dicing wire is gradually increased to a first preset speed, and the operating cycle of the dicing wire is increased from the first preset cycle to a second preset cycle. Maintaining the first preset speed, the process operates for a third preset cycle, where the third preset cycle is a constant or variable value, and the difference L between the third preset cycle and the second preset cycle is greater than or equal to 0.05. The cutting line speed is gradually reduced to the second preset speed, and the cutting line cycle is reduced from the third preset cycle to the fourth preset cycle. By dividing the cutting process into four stages, the wire mesh is set in the pre-processing stage. Then, in the first stage, the cutting line cycle is increased to the second preset cycle, and in the second stage, the cutting line cycle is increased to the third preset cycle. The increased cycle in the first and second stages further increases the distance the cutting line moves, thereby reducing the width of the texture on the silicon wafer surface after silicon block cutting, thus reducing the surface roughness of the silicon wafer and improving the feel of the silicon wafer surface. This solves the problem of high surface roughness and poor feel of solar silicon wafers in the prior art.
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Figure CN119017574B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of silicon wafer manufacturing technology, and more specifically, to a silicon wafer cutting process. Background Technology
[0002] Currently, silicon wafer cutting technology faces numerous challenges, particularly defects such as surface cracks, lines, fissures, short circuits, and material buildup. These defects affect the performance and efficiency of silicon wafers, reducing the conversion efficiency of solar cells. Although the thickness and size of silicon wafers are continuously decreasing, the cutting process still uses relatively fixed parameters, such as wire speed, table speed, cutting depth, cut-off wire speed, cut-off bow shape, and the amount of steel wire used. This results in insufficient silicon wafer cutting quality and efficiency, failing to meet the needs of industry development. Furthermore, solar silicon wafer production requires a large amount of raw materials. Increased raw material costs and the production of substandard products also increase production costs. Additionally, during solar operation, high surface roughness or low flatness accuracy of the silicon wafer affects photoelectric conversion efficiency. Currently, the parameters of the diamond wire used in cutting result in wider lines on solar photovoltaic products, leading to higher surface roughness and a poorer feel.
[0003] As can be seen from the above, the existing technology has the problem of high surface roughness and poor feel of solar silicon wafers. Summary of the Invention
[0004] The main objective of this invention is to provide a silicon wafer cutting process to solve the problem of high surface roughness and poor feel of solar silicon wafers in the prior art.
[0005] To achieve the above objectives, the present invention provides a silicon wafer dicing process, comprising: a pretreatment stage: sequentially winding and installing a dicing wire on a first spool, a first roller, a second roller, and a second spool to form a wire mesh between the first roller and the second roller; a first stage: gradually increasing the speed of the dicing wire to a first preset speed, and increasing the operating cycle of the dicing wire from the first preset cycle to a second preset cycle; a second stage: maintaining the first preset speed and operating at a third preset cycle, wherein the third preset cycle is a constant or variable value, and the difference L between the third preset cycle and the second preset cycle is greater than or equal to 0.05; and a third stage: gradually decreasing the speed of the dicing wire to the second preset speed, and decreasing the operating cycle of the dicing wire from the third preset cycle to a fourth preset cycle.
[0006] Furthermore, in the second stage, a third preset period is set to be greater than 1.35.
[0007] Furthermore, the silicon wafer cutting process includes: setting the ratio of the first preset cycle to the third preset cycle to satisfy 0.31 to 0.33; and / or setting the ratio of the third preset cycle to the fourth preset cycle to satisfy 2.22 to 2.25.
[0008] Furthermore, in the third stage, the speed of the cutting line is first kept constant at the first preset linear speed, and then gradually reduced to the second preset linear speed.
[0009] Furthermore, the silicon wafer dicing process also includes controlling the downward movement speed of the silicon block in the first, second, and third stages. In the first stage, the downward movement speed of the silicon block is gradually increased to a first preset stage speed. In the second stage, the first preset stage speed is increased to a second preset stage speed and maintained at the second preset stage speed, and then the second preset stage speed is gradually decreased to a third preset stage speed. In the third stage, the third preset stage speed is gradually decreased to a fourth preset stage speed.
[0010] Furthermore, in the pretreatment stage, the initial cutting position of the silicon block is set at -0.1mm.
[0011] Furthermore, in the pre-processing stage, the cutting line includes old and new lines connected together, with the new line being longer than the old line. The old line is entirely placed on the first reel, and a portion of the new line is placed on the first reel. The other portion of the new line is wound around the first and second rollers to form a wire mesh and connected to the second reel.
[0012] Furthermore, in the preprocessing stage, the length of the new line is set to satisfy a ratio of 10:7 with the length of the old line.
[0013] Furthermore, the silicon wafer cutting process also includes controlling the downward movement speed of the silicon block in the first, second and third stages. In the third stage, the third preset stage speed is gradually reduced to the fourth preset stage speed, and when the cutting depth reaches 186.5mm, the output length of the second wire wheel is adjusted to be greater than that of the first wire wheel to reduce the amount of old wire used.
[0014] Furthermore, the silicon wafer dicing process also includes supplying liquid to the dicing line through a liquid supply pipeline in the first, second, and third stages.
[0015] According to the technical solution of this invention, the silicon wafer dicing process includes a pretreatment stage, a first stage, a second stage, and a third stage. A dicing wire is sequentially wound and installed on a first reel, a first roller, a second roller, and a second reel to form a wire mesh between the first and second rollers. The speed of the dicing wire is gradually increased to a first preset speed, and the operating cycle of the dicing wire is increased from the first preset cycle to a second preset cycle. Maintaining the first preset speed, the process operates for a third preset cycle, where the third preset cycle is a constant or variable value, and the difference L between the third preset cycle and the second preset cycle is greater than or equal to 0.05. The cutting line speed is gradually reduced to the second preset speed, and the cutting line cycle is reduced from the third preset cycle to the fourth preset cycle. By dividing the cutting process into four stages, the wire mesh is set in the pre-processing stage. Then, in the first stage, the cutting line cycle is increased to the second preset cycle, and in the second stage, the cutting line cycle is increased to the third preset cycle. The increased cycle in the first and second stages further increases the distance the cutting line moves, thereby reducing the width of the texture on the silicon wafer surface after silicon block cutting, thus reducing the surface roughness of the silicon wafer and improving the feel of the silicon wafer surface. This solves the problem of high surface roughness and poor feel of solar silicon wafers in the prior art. Attached Figure Description
[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:
[0017] Figure 1 A flowchart of a silicon wafer dicing process is shown in a specific embodiment of the present invention; and
[0018] Figure 2 A comparison diagram of the existing process and the bow wire of this application is shown in a specific embodiment of the present invention. Detailed Implementation
[0019] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0020] It should be noted that, unless otherwise specified, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0021] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction of the component itself; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not intended to limit this invention.
[0022] Obviously, the embodiments described above are merely some, not all, embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort should fall within the scope of protection of the present invention.
[0023] To address the problem of high surface roughness and poor feel of solar silicon wafers in existing technologies, this invention provides a silicon wafer cutting process.
[0024] like Figure 1 As shown, the silicon wafer dicing process includes a pretreatment stage, a first stage, a second stage, and a third stage. A dicing wire is sequentially wound and installed on a first spool, a first roller, a second roller, and a second spool to form a wire mesh between the first and second rollers. The speed of the dicing wire is gradually increased to a first preset speed, and the operating cycle of the dicing wire increases from the first preset cycle to the second preset cycle. Maintaining the first preset speed, the dicing wire operates for a third preset cycle, which is either a constant or a variable value, and the difference L between the third preset cycle and the second preset cycle is greater than or equal to 0.05. The speed of the dicing wire is then gradually decreased to the second preset speed, and the operating cycle of the dicing wire decreases from the third preset cycle to the fourth preset cycle.
[0025] By dividing the dicing process into four stages, the wire mesh is set up in the pre-processing stage. Then, in the first stage, the dicing wire's operating cycle is increased to a second preset cycle. In the second stage, the operating cycle is further increased to a third preset cycle. Increasing the operating cycle in both stages increases the distance the dicing wire travels, thereby reducing the texture width on the silicon wafer surface after dicing, thus reducing surface roughness and improving the wafer's feel. The principle is that texture width is affected by factors such as cycle time, stage speed, wire speed, and dicing depth. With constant stage speed, wire speed, and dicing depth, the cycle time is inversely proportional to the texture size; therefore, the larger the cycle time, the smaller the texture width.
[0026] It should be noted that the operating cycle refers to the distance the cutting line travels from the first spool to the second spool, and then from the second spool back to the first spool.
[0027] Specifically, the parameters for cutting silicon blocks should be set as shown in the table below.
[0028] Table 1
[0029]
[0030]
[0031] In this embodiment, the linear speed of the cutting line and the stage speed of the silicon block at each step are precisely controlled. Through precise control of the linear speed and stage speed, the process effectively avoids silicon wafer damage caused by improper speed and significantly improves the yield.
[0032] In another embodiment of this application, the change in the linear velocity of the cutting line is synchronized with the change in the table speed, that is, the linear velocity and the table speed increase or decrease synchronously.
[0033] It should be noted that the first stage refers to steps 1 to 4 in Table 1, the second stage refers to steps 5 to 15 in Table 1, and the third stage refers to steps 16 to 22 in Table 1.
[0034] In this embodiment, in the second stage, the third preset period is set to be greater than 1.35.
[0035] Specifically, in the second stage, the third preset cycle is 1.39 in step 6, then rises to 1.46, and remains at 1.46 from step 6 to step 12 of the second stage. The preset cycle throughout the second stage is above 1.35. The larger the third preset cycle in this stage, the smaller the width of the resulting texture.
[0036] In this embodiment, the silicon wafer cutting process includes: setting the ratio of the first preset period to the third preset period to satisfy 0.31 to 0.33; and / or setting the ratio of the third preset period to the fourth preset period to satisfy 2.22 to 2.25.
[0037] Specifically, the first preset cycle is 0.47, the third preset cycle is 1.45 or 1.46, and the fourth preset cycle is 0.65.
[0038] In this embodiment, in the third stage, the cutting line speed is first kept constant at a first preset line speed, and then gradually reduced to a second preset line speed.
[0039] Specifically, in this application, the first preset linear speed is 2100 m / min, and the cutting line maintains a speed of 2100 m / min in the second stage. During this stage, the silicon block is cut at a uniform speed, thereby improving the flatness of the silicon wafer surface. Such a high-speed cutting process can significantly improve production efficiency, reduce the processing time of a single silicon wafer, and is suitable for production environments with high output demands, especially in the semiconductor manufacturing industry where rapid response to market demands is required.
[0040] In this embodiment, the silicon wafer cutting process further includes controlling the downward movement speed of the silicon block in the first, second and third stages. In the first stage, the downward movement speed of the silicon block is gradually increased to a first preset stage speed. In the second stage, the first preset stage speed is increased to a second preset stage speed and maintained at the second preset stage speed, and then the second preset stage speed is gradually decreased to a third preset stage speed. In the third stage, the third preset stage speed is gradually decreased to a fourth preset stage speed.
[0041] Specifically, this setup ensures stability during the cutting process, reduces vibration and cracks during silicon wafer cutting, and is suitable for cutting hard materials, especially high-hardness silicon wafers, significantly improving cutting quality and efficiency. In the first stage, increasing the downward movement speed of the silicon block combined with high-speed cutting of the dicing wire accelerates the contact and cutting between the silicon block and the dicing wire. In the second stage, maintaining a second preset stage speed achieves uniform cutting of the silicon block, preventing unevenness on the silicon wafer surface caused by cutting a rapidly moving silicon block. Steps 20 to 22 in Table 1 represent the finishing stage of cutting the silicon block. In this stage, the preset stage speeds of the above three steps are reduced to prevent the silicon block from moving too fast, causing the dicing wire to form a large downward arc, thereby reducing the incidence of overcutting and finishing line marks. It should be noted that overcutting refers to the situation where all steps have been completed, but due to the large downward arc (bow) formed by the dicing wire, the silicon block has not been completely cut at the arced position of the dicing wire. Compared with existing processes, the finishing stage speed of this application is shown in Table 2.
[0042] Table 2
[0043]
[0044]
[0045] Specifically, Table 2 shows the table speed and approximate angle of the arc formed in the three finishing steps compared to existing processes. This application adjusts the preset table speed in the three finishing steps to achieve a larger included angle in the arc formed, resulting in a smoother arc. (See attached table.) Figure 2 As shown, the left side shows the wire bow formed by the existing process, and the right side shows the wire bow formed by this application. Compared with the existing process, the fourth preset stage speed of this application is lower, which makes the wire bow flatter than the original process and avoids the need for additional cutting. The optimization of the wire bow shape not only reduces the silicon wafer stress during the cutting process, but also improves the surface quality of the silicon wafer, providing a solid foundation for manufacturing high-performance electronic components.
[0046] In this embodiment, during the preprocessing stage, the initial cutting position of the silicon block is set to -0.1mm.
[0047] Specifically, the method of setting the interval between the silicon block and the dicing line during the preprocessing stage can predict the position of the dicing line cutting the silicon block before the dicing begins. If the dicing position is not reasonable, for example, the dicing line does not come into contact with the silicon block after cutting, it can be adjusted in time to ensure the dicing effect.
[0048] In this embodiment, during the preprocessing stage, the cutting line includes an old line and a new line connected together, with the new line being longer than the old line. The old line is entirely placed on the first reel, and a portion of the new line is placed on the first reel. The other portion of the new line is wound around the first roller and the second roller to form a wire mesh and connected to the second reel.
[0049] It should be noted that "new thread" refers to a cutting thread that has never been used, while "old thread" refers to a cutting thread that has already been used.
[0050] Specifically, at the start of cutting in this application, the silicon block is located above the new wire. At the start of cutting, the feed rate of the first roller is greater than the return rate. That is, the cutting wire first moves a certain length towards the second roller, and then moves a certain distance towards the first roller. For example, in Table 1, the feed rate in the first step is 750m and the return rate is 730m. The cutting wire moves 750m towards the second roller and then 730m towards the first roller. In other words, the entire cutting wire moves 20m towards the second roller. Since new wire is used on the first and second rollers during the pre-processing stage, the first step of the cutting process is simply the movement of the new wire. Similarly, in the second step, the cutting depth of the silicon block is 5mm. At this point, cutting of the silicon block has begun. Because the feed rate is greater than the return rate, the cutting wire used to cut the silicon block is a new wire. The new wire has not been used before, thus providing a better cutting effect. The old wire, having been used, has lower structural strength, surface wear, and a risk of breakage after prolonged use.
[0051] In this embodiment, during the preprocessing stage, the length of the new line is set to satisfy a ratio of 10:7 with the length of the old line.
[0052] Specifically, by laying new wires on the first and second rollers during the pre-processing stage, and utilizing the range between the lengths of the old and new wires, the new wires are mainly used when cutting silicon blocks, resulting in better cutting effects. The old wires are mainly set on the first wire reel, and are only used when all the new wires on the first and second rollers are wound onto the second wire reel, thus ensuring the stability of the cutting effect.
[0053] In this embodiment, the silicon wafer cutting process further includes controlling the downward movement speed of the silicon block in the first, second and third stages. In the third stage, the third preset stage speed is gradually reduced to the fourth preset stage speed, and when the cutting depth reaches 186.5mm, the wire output length of the second wire wheel is adjusted to be greater than the wire output length of the first wire wheel to reduce the amount of old wire used.
[0054] Specifically, during the cutting process from -1mm to 185mm depth, the old wire also participates in the cutting. By utilizing the worn steel wire to cut at a specific depth, not only is the use of new wire saved, but cutting costs are also optimized, providing a sustainable solution for production. When the cutting depth reaches 186.5mm, that is, starting from step 17, the feed amount of the cutting wire is less than the return amount. In other words, at this point, the entire cutting wire moves towards the first reel. In this way, the new wire moves towards the first reel, so that the cutting wire used when cutting silicon blocks gradually becomes the main type of new wire, thereby reducing the use of old wire and avoiding an increased rate of take-up marks caused by excessive use of old wire.
[0055] Furthermore, the implementation of the new and old wire switching strategy ensured the rational allocation of the use of new and old steel wires while maintaining cutting quality and efficiency, thus extending the lifespan of the materials. In the production environment handling thin silicon wafers, this strategy effectively prevented wafer breakage caused by minor fluctuations during the cutting process, significantly improving yield and production efficiency.
[0056] In another optional embodiment of this application, the silicon wafer dicing process further includes predicting the wear rate of the steel wires during the dicing process. Predicting the wear rate allows for advance planning of steel wire replacement and maintenance, avoiding production interruptions caused by sudden steel wire damage and ensuring the continuity and efficiency of the production process.
[0057] In this embodiment, the silicon wafer cutting process also includes supplying liquid to the cutting line through a liquid supply pipeline in the first, second and third stages.
[0058] Specifically, there are two fluid supply lines, one above the first roller and the other above the second roller. These two lines supply cutting fluid to the dicing lines before and after the silicon ingot is cut, cleaning the dicing lines to prevent particles from scratching the silicon wafer and reducing the temperature on the dicing lines. This pretreatment also extends the lifespan of older dicing lines, reduces cutting quality issues caused by performance degradation, and significantly lowers production costs.
[0059] In this embodiment, the silicon wafer cutting process also includes monitoring and controlling the cutting temperature. The introduction of the temperature monitoring and control system ensures the temperature stability of the cutting area, avoids thermal damage and cracks in the silicon wafer caused by high temperature, and improves the yield.
[0060] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects: by setting the silicon wafer cutting process to include a pretreatment stage, a first stage, a second stage, and a third stage, the cutting wire is sequentially wound and installed on a first wire reel, a first roller, a second roller, and a second wire reel to form a wire mesh between the first roller and the second roller. The speed of the cutting wire is gradually increased to a first preset wire speed, and the operating cycle of the cutting wire is increased from the first preset cycle to the second preset cycle. The first preset wire speed is maintained, and the cutting wire operates at a third preset cycle, where the third preset cycle is a constant or variable value, and the difference L between the third preset cycle and the second preset cycle is greater than 1. The value is equal to 0.05. The speed of the cutting line is gradually reduced to the second preset line speed. The running cycle of the cutting line is reduced from the third preset cycle to the fourth preset cycle. By dividing the cutting process into four stages, the wire mesh is set in the pre-processing stage. Then, in the first stage, the running cycle of the cutting line is increased to the second preset cycle. In the second stage, the running cycle of the cutting line is increased to the third preset cycle. The running cycle is increased in the first and second stages, thereby increasing the distance the cutting line moves. This reduces the width of the texture on the surface of the silicon wafer after the silicon block is cut, thereby reducing the roughness of the silicon wafer surface and improving the feel of the silicon wafer surface.
[0061] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0062] It should be noted that the terms "upper" and "lower," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.
[0063] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A silicon wafer cutting process, characterized in that, The silicon wafer cutting process includes: Pre-processing stage: The cutting wire is sequentially wound and installed on the first wire reel, the first roller, the second roller and the second wire reel to form a wire mesh between the first roller and the second roller; First stage: The speed of the cutting line is gradually increased to a first preset line speed, and the running cycle of the cutting line is increased from the first preset cycle to the second preset cycle; Second stage: Maintain the first preset linear velocity and run at a third preset period, wherein the third preset period is a constant or a variable value, and the difference L between the third preset period and the second preset period is greater than or equal to 0.05; Third stage: Adjust the speed of the cutting line to gradually reduce to the second preset line speed, and reduce the running cycle of the cutting line from the third preset cycle to the fourth preset cycle; In the preprocessing stage, the cutting line comprises an old line and a new line joined together, wherein the length of the new line is greater than the length of the old line. All the old thread is placed on the first reel, and a portion of the new thread is placed on the first reel. The other portion of the new thread is wound around the first roller and the second roller to form the wire mesh and connected to the second reel. In the preprocessing stage, the length of the new line is set to satisfy a ratio of 10:7 with the length of the old line; When cutting begins, the amount of wire fed by the first spool is greater than the amount of wire returned.
2. The silicon wafer cutting process according to claim 1, characterized in that, In the second stage, the third preset period is set to be greater than 1.
35.
3. The silicon wafer cutting process according to claim 1, characterized in that, The silicon wafer cutting process includes: The ratio of the first preset period to the third preset period is set to satisfy 0.31 to 0.33; and / or The ratio of the third preset period to the fourth preset period is set to satisfy 2.22 to 2.
25.
4. The silicon wafer cutting process according to claim 1, characterized in that, In the third stage, the speed of the cutting line is first kept constant at the first preset line speed, and then gradually reduced to the second preset line speed.
5. The silicon wafer cutting process according to claim 1, characterized in that, The silicon wafer dicing process further includes controlling the downward movement speed of the silicon block in the first stage, the second stage, and the third stage, wherein, In the first stage, the downward movement speed of the silicon block is gradually increased to a first preset stage speed; In the second stage, the first preset speed is increased to the second preset speed and the second preset speed is maintained continuously, and then the second preset speed is gradually reduced to the third preset speed. In the third stage, the third preset speed is gradually reduced to the fourth preset speed.
6. The silicon wafer cutting process according to claim 1, characterized in that, In the pretreatment stage, the initial cutting position of the silicon block is set to -0.1 mm.
7. The silicon wafer cutting process according to claim 1, characterized in that, The silicon wafer dicing process further includes controlling the downward movement speed of the silicon block in the first stage, the second stage, and the third stage, wherein, In the third stage, the third preset table speed is gradually reduced to the fourth preset table speed, and when the cutting depth reaches 186.5mm, the output length of the second thread spool is adjusted to be greater than the output length of the first thread spool in order to reduce the amount of old thread used.
8. The silicon wafer cutting process according to any one of claims 1 to 7, characterized in that, The silicon wafer cutting process also includes supplying liquid to the cutting line through a liquid supply pipeline in the first stage, the second stage, and the third stage.
Citation Information
Patent Citations
Cutting method and system for improving appearance line mark degradation of solar cell
CN117863373A