Semiconductor structure and method of manufacturing the same
By designing a larger first conductive structure in the semiconductor structure to directly contact the connecting pad, the influence of the second conductive structure on the isolation effect of the isolation structure is resolved, thus enhancing the isolation effect of the isolation structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2024-09-24
- Publication Date
- 2026-07-14
AI Technical Summary
In the prior art, the setting of the second conductive structure affects the isolation effect of the isolation structure, and how to reduce this effect has become an urgent problem to be solved.
By setting the size of the first conductive structure in the semiconductor structure to be larger than that of the second conductive structure and making it in direct contact with the connecting pad, the distance between the isolation structure and the conductive structures on both sides is increased, thereby enhancing the isolation effect.
This effectively reduces the impact of the second conductive structure on the isolation effect of the isolation structure, thus improving the isolation performance of the isolation structure.
Smart Images
Figure CN119028953B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] Typically, a semiconductor structure includes a first conductive structure, an isolation structure, and a second conductive structure. The first conductive structure is used to connect device layers between semiconductor structures, and the second conductive structure is located between the first conductive structure and the isolation structure. The placement of the second conductive structure improves the consistency of the pattern of the first conductive structure but affects the isolation effect of the isolation structure. How to reduce the impact of the second conductive structure on the isolation effect of the isolation structure has become an urgent problem to be solved. Summary of the Invention
[0003] Based on this, a semiconductor structure and its fabrication method are provided, which can reduce the impact of the second conductive structure on the isolation effect of the isolation structure.
[0004] A semiconductor structure, comprising:
[0005] Base;
[0006] Connecting pad, located on the substrate;
[0007] A multilayer structure located on a connecting pad includes an insulating layer and a conductive layer alternately stacked along a first direction;
[0008] An isolation structure is located in the stacked structure, penetrates the stacked structure along the first direction, and extends along the second direction, which is perpendicular to the first direction;
[0009] A first conductive structure and a second conductive structure are spaced apart and located in the stacked structure. The first conductive structure is in direct contact with the connecting pad, and the second conductive structure is in direct contact with the isolation structure. The size of the first conductive structure is larger than the size of the second conductive structure.
[0010] In one embodiment, the isolation structure includes a second isolation layer and a third isolation layer stacked along the first direction, the third isolation layer being located on the top surface of the second isolation layer away from the substrate.
[0011] In one embodiment, the second conductive structure includes a first portion located on the sidewall of the isolation structure and a second portion covering the top surface of the isolation structure portion, the bottom surface of the second portion being higher than the bottom surface of the third isolation layer.
[0012] In one embodiment, the first part and the second part are integrally connected.
[0013] In one embodiment, the semiconductor structure further includes:
[0014] A device isolation layer is located at the bottom of the stacked structure near the substrate, and the top surface of the device isolation layer away from the substrate is in contact with the bottom surface of the stacked structure near the substrate;
[0015] The first portion penetrates the device isolation layer and is in direct contact with the connection pad.
[0016] A method for fabricating a semiconductor structure, comprising:
[0017] A substrate is provided on which a connecting pad is formed;
[0018] A stacked structure is formed on the connecting pad, the stacked structure comprising an insulating layer and a conductive layer alternately stacked along a first direction;
[0019] An isolation structure, a second conductive structure, and a first conductive structure are respectively formed in the stacked structure;
[0020] The isolation structure and the second conductive structure are in direct contact. The isolation structure penetrates the stacked structure along the first direction and extends along the second direction, which is perpendicular to the first direction. The second conductive structure is spaced apart from the first conductive structure. The first conductive structure is in direct contact with the connecting pad, and the size of the first conductive structure is larger than the size of the second conductive structure.
[0021] In one embodiment, forming the isolation structure, the second conductive structure, and the first conductive structure respectively in the stacked structure includes:
[0022] An isolation structural material layer is formed in the stacked structure. The isolation structural material layer includes a second isolation material layer and a third isolation material layer stacked along the first direction. The third isolation material layer is located on the top surface of the second isolation material layer away from the substrate.
[0023] A first signal filling hole is formed in the isolation structure material layer and the stacked structure to form an isolation structure composed of the remaining isolation structure material layer. The first signal filling hole includes an integrally formed third filling hole and a fourth filling hole. Along the first direction, the third filling hole penetrates the stacked structure, and the fourth filling hole extends from a portion of the top surface of the isolation structure material layer into the isolation structure material layer.
[0024] A second signal filling hole is formed in the stacked structure, the second signal filling hole penetrates the stacked structure along the first direction, and is spaced apart from the first signal filling hole;
[0025] Metal material is filled into the first signal filling hole and the second signal filling hole to form a second conductive structure located in the first signal filling hole and a first conductive structure located in the second signal filling hole.
[0026] In one embodiment, along the first direction, the fourth filling hole extends from a portion of the top surface of the third insulating material layer into the third insulating material layer.
[0027] In one embodiment, prior to forming the laminated structure on the connecting pad, the preparation method further includes:
[0028] A device isolation layer is formed on the substrate, wherein the top surface of the device isolation layer away from the substrate contacts the bottom surface of the stacked structure near the substrate;
[0029] The third filling hole and the second signal filling hole penetrate the device isolation layer and expose the connection pad.
[0030] In one embodiment, the method for fabricating the semiconductor structure further includes:
[0031] A plurality of stacked structures spaced apart along the first direction are formed on the substrate;
[0032] The process includes forming an isolation structure, a second conductive structure, and a first conductive structure in the stacked structure before forming the next stacked structure; the second conductive structures in each stacked structure are sequentially contacted along the first direction, and the isolation structures in each stacked structure are sequentially arranged along the first direction.
[0033] In the above semiconductor structure, the size of the first conductive structure is larger than the size of the second conductive structure. This arrangement increases the distance between the isolation structure and the second conductive structure and the first conductive structure on both sides, or between the second conductive structure and the second conductive structure, thereby increasing the isolation effect of the isolation structure in a third direction parallel to the substrate.
[0034] In the above-mentioned semiconductor structure fabrication method, the first conductive structure formed in the stacked structure is in direct contact with the connection pad. The device layer in the substrate is brought out through the contact between the first conductive structure and the connection pad. Furthermore, the size of the first conductive structure is larger than the size of the second conductive structure. This arrangement increases the distance between the isolation structure and the second conductive structure and the first conductive structure on both sides, or between the second conductive structure and the second conductive structure, thereby increasing the isolation effect of the isolation structure in the third direction parallel to the substrate. Attached Figure Description
[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0036] Figure 1 This is a schematic flowchart of the semiconductor structure fabrication method in some embodiments;
[0037] Figure 2 This is a schematic cross-sectional view of the semiconductor structure after the stacked structure is formed in some embodiments;
[0038] Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure after the isolation trench is formed in some embodiments;
[0039] Figure 4 This is a schematic cross-sectional view of the semiconductor structure after the formation of the isolation structure material layer in some embodiments;
[0040] Figure 5 This is a cross-sectional schematic diagram of the semiconductor structure after the isolation structure is formed in some embodiments;
[0041] Figure 6 This is a schematic cross-sectional view of the semiconductor structure after the second conductive structure is formed in some embodiments;
[0042] Figure 7 for Figure 6 A cross-sectional view corresponding to the AA direction;
[0043] Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure after the second conductive structure is formed in some other embodiments.
[0044] Explanation of reference numerals in the attached figures:
[0045] Substrate 102; Second isolation material layer 103; Stacked structure 104; Second isolation layer 110; Third isolation layer 112; Isolation structure 114; Second conductive structure 116; Device isolation layer 118; First conductive structure 120; Connecting pad 122; Insulating layer 202; Conductive layer 204; Hard mask layer 208; Photoresist pattern layer 210; Third isolation material layer 220; Second signal filling hole 223; First portion 224; Second portion 226; Isolation trench 302; Third filling hole 306; Fourth filling hole 308. Detailed Implementation
[0046] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.
[0048] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0049] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0050] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0051] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.
[0052] Figure 1 This is a schematic flowchart of the semiconductor structure fabrication method in some embodiments, such as... Figure 1 As shown, in this embodiment, a method for fabricating a semiconductor structure is provided, comprising:
[0053] S102, providing a substrate on which a connecting pad is formed.
[0054] A substrate is provided, on which connection pads are formed, enabling electrical connections between device layers in the substrate and device layers above the connection pads. As an example, the substrate may be composed of undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), germanium-on-insulator (GeOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof.
[0055] S104, a stacked structure is formed on the connecting pad, the stacked structure including an insulating layer and a conductive layer alternately stacked along a first direction.
[0056] A laminated structure is formed on the bonding pad, the laminated structure comprising an insulating layer and a conductive layer alternately laminated along a first direction perpendicular to the substrate. As an example, the insulating layer is made of silicon dioxide, and the conductive layer is made of tungsten.
[0057] S106, an isolation structure, a second conductive structure, and a first conductive structure are formed in the stacked structure, respectively.
[0058] Specifically, an isolation structure, a first conductive structure, and a second conductive structure are formed in the stacked structure. The sidewalls of the isolation structure and the second conductive structure are in direct contact. The isolation structure penetrates the stacked structure along the first direction and extends along a second direction parallel to the substrate, which is perpendicular to the first direction. The second conductive structure is spaced apart from the first conductive structure. The first conductive structure is in direct contact with the connecting pad. The device layer in the substrate is brought out through the contact between the first conductive structure and the connecting pad. The size of the first conductive structure is larger than that of the second conductive structure. This arrangement increases the distance between the isolation structure and the second conductive structure on both sides, thereby increasing the isolation effect of the isolation structure in a third direction parallel to the substrate, which intersects with the second direction.
[0059] like Figures 2-7 As shown, in one embodiment, the step of forming an isolation structure 114, a second conductive structure 116, and a first conductive structure 120 in the stacked structure 104 includes steps S202-S208.
[0060] S202, an isolation structural material layer 105 is formed in the stacked structure 104.
[0061] like Figure 2As shown, a stacked structure 104 is formed on a substrate 102. The stacked structure 104 includes an insulating layer 202 and a conductive layer 204 alternately stacked along a first direction X perpendicular to the substrate 102. The bottom layer of the stacked structure 104 near the substrate 102 and the top layer of the stacked structure 104 away from the substrate 102 can be the same, both being an insulating layer 202 or a conductive layer 204, or they can be different, one being an insulating layer 202 and the other being a conductive layer 204. This application does not limit this. In the accompanying drawings, the bottom layer of the stacked structure 104 near the substrate 102 and the top layer of the stacked structure 104 away from the substrate 102 are both insulating layers 202 for illustrative purposes.
[0062] like Figure 3 , Figure 4 As shown, an isolation groove 302 is formed in the stacked structure 104. The isolation groove 302 extends through the stacked structure 104 along the first direction X and extends along the second direction Y. Then, a second isolation material layer 103 and a third isolation material layer 220 are sequentially formed in the isolation groove 302. The third isolation material layer 220 is located on the top surface of the second isolation material layer 103 away from the substrate 102 and is in contact with the second isolation material layer 103. The third isolation material layer 220 fills the isolation groove 302. The isolation structure material layer 105 includes the second isolation material layer 103 and the third isolation material layer 220 stacked along the first direction X. For example, the second isolation material layer 103 is made of silicon dioxide, and the third isolation material layer 220 is made of silicon nitride.
[0063] S204, a first signal filling hole 222 is formed in the isolation structure material layer 105 and the stacked structure 104 to form an isolation structure 114 composed of the remaining isolation structure material layer 105.
[0064] like Figure 4 , Figure 5As shown, firstly, a hard mask layer 208 and a photoresist pattern layer 210 are sequentially formed on the stacked structure 104. The hard mask layer 208 extends to cover the top surface of the isolation structure material layer 105 away from the substrate 102. The photoresist pattern layer 210 defines the shape and position of the first signal filling hole 222. As an example, the material of the hard mask layer 208 includes silicon nitride. Next, using the photoresist pattern layer 210 as a mask, the isolation structure material layer 105 and the stacked structure 104 are patterned, forming a first signal filling hole 222 at the interface between the stacked structure 104 and the isolation structure material layer 105, thus forming an isolation structure 114 composed of the remaining isolation structure material layer 105. The first signal filling hole 222 includes an integrally formed third filling hole 306 and a fourth filling hole 308. Along the first direction X, the third filling hole 306 penetrates the stacked structure 104 near the isolation structure material layer 105, and the fourth filling hole 308 extends from a portion of the top surface of the isolation structure material layer 105 into the isolation structure material layer 105, with its bottom remaining within the isolation structure material layer 105. Therefore, the opening size of the first signal filling hole 222 is larger than the bottom size of the first signal filling hole 222.
[0065] In one embodiment, along the first direction X, the fourth filling hole 308 extends from a portion of the top surface of the third isolation material layer 220 into the third isolation material layer 220. At this time, the second isolation material layer 103 in the isolation groove 302 serves as the second isolation layer 110, and the remaining third isolation material layer 220 in the isolation groove 302 serves as the third isolation layer 112.
[0066] In one embodiment, along the first direction X, the fourth filling hole 308 extends from a portion of the top surface of the third isolation material layer 220 to expose the second isolation material layer 103. At this time, the remaining second isolation material layer 103 in the isolation groove 302 serves as the second isolation layer 110, and the remaining third isolation material layer 220 in the isolation groove 302 serves as the third isolation layer 112.
[0067] S206, a second signal filling hole 223 is formed in the stacked structure 104.
[0068] like Figure 5As shown, a second signal filling via 223 is formed in the stacked structure 104 away from the isolation structure 114. The second signal filling via 223 penetrates the stacked structure 104 along the first direction X, exposing the connecting pad 122. In a plane parallel to the substrate 102, the second signal filling via 223 is spaced apart from the first signal filling via 222. As an example, the second signal filling via 223 is formed simultaneously with the first signal filling via 222 using the photoresist patterning layer 210, simplifying the process steps. As an example, the semiconductor structure fabrication method also includes the step of removing the photoresist patterning layer 210 and the hard mask layer 208.
[0069] Continue to refer to Figure 5 In one embodiment, before forming the stacked structure 104 on the connection pad 122, the method for fabricating the semiconductor structure further includes: forming a device isolation layer 118 on the substrate 102, wherein the top surface of the device isolation layer 118 away from the substrate 102 contacts the bottom surface of the stacked structure 104 near the substrate 102; wherein the third filling via 306 and the second signal filling via 223 penetrate the device isolation layer 118 and expose the connection pad 122. As an example, the material of the device isolation layer 118 includes aluminum oxide.
[0070] S208, fill the first signal filling hole 222 and the second signal filling hole 223 with metal material to form a second conductive structure 116 located in the first signal filling hole 222 and a first conductive structure 120 located in the second signal filling hole 223.
[0071] like Figure 6 , Figure 7 As shown, metal material is filled into the first signal filling hole 222 and the second signal filling hole 223 to form a second conductive structure 116 in the first signal filling hole 222 and a first conductive structure 120 in the second signal filling hole 223. The second conductive structure 116 completely fills the first signal filling hole 222, including a first portion 224 filled in the third filling hole 306 and a second portion 226 filled in the fourth filling hole 308. The first conductive structure 120 completely fills the second signal filling hole 223. The size CD1 of the second conductive structure 116 is smaller than the size CD2 of the first conductive structure 120. As an example, the metal material includes tungsten. As an example, the first conductive structure 120 is a word line in a semiconductor structure.
[0072] Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the second conductive structure in some other embodiments, such as... Figure 8As shown, in one embodiment, the method for fabricating the semiconductor structure further includes: forming a plurality of stacked structures 104 spaced apart along the first direction X on the substrate 102; wherein, before forming the next stacked structure 104, the method includes the steps of forming an isolation structure 114, a second conductive structure 116, and a first conductive structure 120 in the stacked structure 104 respectively; the second conductive structures 116 in each stacked structure 104 are sequentially contacted along the first direction X, and the isolation structures 114 in each stacked structure 104 are sequentially arranged along the first direction X.
[0073] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0074] This disclosure provides a semiconductor structure, the parts of which are the same as or corresponding to those in the embodiments of the above-described semiconductor structure preparation method, and will not be repeated below. Figure 6 , Figure 7 As shown, in this embodiment, a semiconductor structure is provided, including: a substrate 102, a connection pad 122, a stacked structure 104, an isolation structure 114, a first conductive structure 120, and a second conductive structure 116; the connection pad 122 is located on the substrate 102; the stacked structure 104 is located on the connection pad 122, including an insulating layer 202 and a conductive layer 204 alternately stacked along a first direction X; the isolation structure 114 is located in the stacked structure 104, penetrates the stacked structure 104 along the first direction X, and extends along a second direction Y, the second direction being perpendicular to the first direction; the first conductive structure 120 and the second conductive structure 116 are spaced apart and located in the stacked structure 104, the first conductive structure 120 is in direct contact with the connection pad 122, and the second conductive structure 116 is in direct contact with the isolation structure 114; the size CD2 of the first conductive structure 120 is larger than the size CD1 of the second conductive structure 116.
[0075] In the above semiconductor structure, the size of the first conductive structure is larger than the size of the second conductive structure. This arrangement increases the distance between the isolation structure and the second conductive structure and the first conductive structure on both sides, or between the second conductive structure and the second conductive structure, thereby increasing the isolation effect of the isolation structure in a third direction parallel to the substrate.
[0076] like Figure 6 , Figure 7 As shown, in one embodiment, the isolation structure 114 includes a second isolation layer 110 and a third isolation layer 112 stacked along the first direction X, wherein the third isolation layer 112 is located on the top surface of the second isolation layer 110 away from the substrate 102.
[0077] like Figure 6 , Figure 7 As shown, in one embodiment, the second conductive structure 116 includes a first portion 224 located on the sidewall of the isolation structure 114 and a second portion 226 covering the top surface of the portion of the isolation structure 114.
[0078] like Figure 6 , Figure 7 As shown, in one embodiment, the first portion 224 and the second portion 226 are integrally connected, and the bottom surface of the second portion 226 is higher than the bottom surface of the second insulating layer 110. Furthermore, the bottom surface of the second portion 226 is higher than the bottom surface of the third insulating layer 112.
[0079] like Figure 6 , Figure 7 As shown, in one embodiment, the semiconductor structure further includes: a device isolation layer 118 located at the bottom of the stacked structure 104 near the substrate 102, wherein the top surface of the device isolation layer 118 away from the substrate 102 contacts the bottom surface of the stacked structure 104 near the substrate 102; wherein the first portion 224 penetrates the device isolation layer 118 and directly contacts the connection pad 122, and the first conductive structure 120 penetrates the device isolation layer 118 and contacts the connection pad 122.
[0080] This disclosure also provides an electronic device including the semiconductor structure described in any of the preceding embodiments. This electronic device may include a smartphone, computer, tablet computer, artificial intelligence, wearable device, or smart mobile terminal. This application does not impose any special limitations on the specific form of the described electronic device.
[0081] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0082] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A semiconductor structure, characterized in that, include: Base; Connecting pad, located on the substrate; A multilayer structure located on a connecting pad includes an insulating layer and a conductive layer alternately stacked along a first direction; An isolation structure is located in the stacked structure, penetrates the stacked structure along the first direction, and extends along the second direction, which is perpendicular to the first direction; A first conductive structure and a second conductive structure are spaced apart and located in the stacked structure. The first conductive structure is in direct contact with the connecting pad and both sides of the first conductive structure are in direct contact with the stacked structure. The second conductive structure is located between the first conductive structure and the isolation structure and one side of the second conductive structure is in direct contact with the isolation structure. The other side of the second conductive structure is in direct contact with the stacked structure; the size of the first conductive structure is larger than the size of the second conductive structure.
2. The semiconductor structure according to claim 1, characterized in that, The isolation structure includes a second isolation layer and a third isolation layer stacked along the first direction, wherein the third isolation layer is located on the top surface of the second isolation layer away from the substrate.
3. The semiconductor structure according to claim 2, characterized in that, The second conductive structure includes a first portion located on the sidewall of the isolation structure and a second portion covering the top surface of the isolation structure portion, wherein the bottom surface of the second portion is higher than the bottom surface of the third isolation layer.
4. The semiconductor structure according to claim 3, characterized in that, The first part and the second part are connected as a single unit.
5. The semiconductor structure according to claim 3, characterized in that, The semiconductor structure also includes: A device isolation layer is located at the bottom of the stacked structure near the substrate, and the top surface of the device isolation layer away from the substrate is in contact with the bottom surface of the stacked structure near the substrate; The first portion penetrates the device isolation layer and is in direct contact with the connection pad.
6. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided on which a connecting pad is formed; A stacked structure is formed on the connecting pad, the stacked structure comprising an insulating layer and a conductive layer alternately stacked along a first direction; An isolation structure, a second conductive structure, and a first conductive structure are respectively formed in the stacked structure; Wherein, the second conductive structure is located between the first conductive structure and the isolation structure, the isolation structure and one side of the second conductive structure are in direct contact, and the other side of the second conductive structure is in direct contact with the stacked structure; The isolation structure penetrates the stacked structure along the first direction and extends along the second direction, which is perpendicular to the first direction; the second conductive structure is spaced apart from the first conductive structure, the first conductive structure is in direct contact with the connecting pad, both sides of the first conductive structure are in direct contact with the stacked structure, and the size of the first conductive structure is larger than the size of the second conductive structure.
7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The formation of an isolation structure, a second conductive structure, and a first conductive structure in the stacked structure includes: An isolation structural material layer is formed in the stacked structure. The isolation structural material layer includes a second isolation material layer and a third isolation material layer stacked along the first direction. The third isolation material layer is located on the top surface of the second isolation material layer away from the substrate. A first signal filling hole is formed in the isolation structure material layer and the stacked structure to form an isolation structure composed of the remaining isolation structure material layer. The first signal filling hole includes an integrally formed third filling hole and a fourth filling hole. Along the first direction, the third filling hole penetrates the stacked structure, and the fourth filling hole extends from a portion of the top surface of the isolation structure material layer into the isolation structure material layer. A second signal filling hole is formed in the stacked structure, the second signal filling hole penetrates the stacked structure along the first direction, and is spaced apart from the first signal filling hole; Metal material is filled into the first signal filling hole and the second signal filling hole to form a second conductive structure located in the first signal filling hole and a first conductive structure located in the second signal filling hole.
8. The method for preparing a semiconductor structure according to claim 7, characterized in that, Along the first direction, the fourth filling hole extends from a portion of the top surface of the third insulating material layer into the third insulating material layer.
9. The method for preparing a semiconductor structure according to claim 7, characterized in that, Before the laminated structure is formed on the connecting pad, the preparation method further includes: A device isolation layer is formed on the substrate, wherein the top surface of the device isolation layer away from the substrate contacts the bottom surface of the stacked structure near the substrate; The third filling hole and the second signal filling hole penetrate the device isolation layer and expose the connection pad.
10. The method for preparing a semiconductor structure according to claim 6, characterized in that, The method for preparing the semiconductor structure further includes: A plurality of stacked structures spaced apart along the first direction are formed on the substrate; The process includes forming an isolation structure, a second conductive structure, and a first conductive structure in the stacked structure before forming the next stacked structure; the second conductive structures in each stacked structure are sequentially contacted along the first direction, and the isolation structures in each stacked structure are sequentially arranged along the first direction.
11. A semiconductor structure, characterized in that, include: Base; Connecting pad, located on the substrate; A multilayer structure located on a connecting pad includes an insulating layer and a conductive layer alternately stacked along a first direction; An isolation structure is located in the stacked structure, extends through the stacked structure along a first direction, and extends along a second direction perpendicular to the first direction; the isolation structure includes a second isolation layer and a third isolation layer stacked along the first direction, the third isolation layer being located on the top surface of the second isolation layer away from the substrate; A first conductive structure and a second conductive structure are spaced apart and located in the stacked structure. The first conductive structure is in direct contact with the connecting pad, and the second conductive structure is in direct contact with the isolation structure. The second conductive structure includes a first part in direct contact with the second isolation layer and a second part in direct contact with the third isolation layer. The size of the second part is larger than the size of the first part. The size of the first conductive structure is larger than the size of the second conductive structure.
12. A semiconductor structure, characterized in that, include: Base; Connecting pad, located on the substrate; A multilayer structure located on a connecting pad includes an insulating layer and a conductive layer alternately stacked along a first direction; An isolation structure is located in the stacked structure, penetrates the stacked structure along the first direction, and extends along the second direction, which is perpendicular to the first direction; The first conductive structure is located in the stacked structure and has two opposing side walls, which are in direct contact with the stacked structure. The second conductive structure is located between the stacked structure and the isolation structure, and has two opposing side walls, one of which is in direct contact with the stacked structure and the other side wall is in direct contact with the isolation structure; the size of the first conductive structure is larger than the size of the second conductive structure.