A data reading and writing method, product, data accelerator and medium

By converting the sending address of data in the data accelerator and filling the matrix dimension, the problem of inappropriate data storage order when the matrix multiplication unit and the non-matrix multiplication unit are adjacent is solved, and the effect of reducing the speech recognition time is achieved.

CN119045776BActive Publication Date: 2025-04-25LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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Patent Information

Application Number
CN202411534508.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-10-31
Publication Date
2025-04-25
Estimated Expiration
2044-10-31

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Abstract

This invention discloses a data read / write method, product, data accelerator, and medium, relating to the field of data processing technology. Data from matrix multiplication acceleration units, which is not in complete row order, is stored in a cache in complete row order. The output order of the matrix multiplication acceleration units' results needs to be converted by matching the size of the partitions and the row and column dimensions to accommodate the write order of non-matrix multiplication units, avoiding the high-latency operation of writing data from matrix multiplication acceleration units back to off-chip memory and then reading it. The data storage order of non-matrix multiplication units is padded so that the matrix dimension of the padded third data is the same as that of the matrix multiplication acceleration units. This achieves the function of generating data with the required dimensions of the matrix multiplication acceleration units for the actual calculation results, avoiding the high-latency operation of writing data from non-matrix multiplication acceleration units back to off-chip memory and then reading it.
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Citation Information

Patent Citations

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  • Method for realizing local caching of data in systolic array calculation

    CN118012340A