Semiconductor structure and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The second dielectric layer on a second transistor is removed by controlling an etching endpoint of a first dielectric layer and a grinding endpoint of a second dielectric layer, and the second dielectric layer on a gate structure of the first transistor is retained. The top surface of the second dielectric layer on the gate structure of the first transistor is flush with the top surface of the gate structure of the second transistor, thereby solving the problem of a height difference between the first transistor and the second transistor. The transistors of the semiconductor structure have uniform heights, which is beneficial to the execution and control of subsequent processes.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In the process of advanced semiconductor manufacturing, it is often necessary to form NMOS transistors and PMOS transistors on the same wafer. However, due to the difference in the manufacturing processes of NMOS transistors and PMOS transistors, the height of PMOS transistors is often lower than that of NMOS transistors, and the overall height uniformity of transistors is poor, which affects the execution of subsequent manufacturing processes of other devices. Summary of the invention

[0003] Based on this, the present disclosure provides a semiconductor structure and a method for manufacturing the same.

[0004] In order to achieve the above object, on the one hand, the present disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0005] Providing a substrate, on which a first transistor and a second transistor are formed, wherein a top surface of a gate structure of the first transistor has a height lower than a top surface of a gate structure of the second transistor;

[0006] forming a first dielectric layer, wherein the first dielectric layer covers the first transistor and the second transistor, and a top surface of the first dielectric layer is higher than a top surface of a gate structure of the second transistor;

[0007] Etching the first dielectric layer on the first transistor with the top surface of the gate structure of the first transistor as an etching end point to expose the top surface of the gate structure of the first transistor;

[0008] forming a second dielectric layer, wherein the second dielectric layer covers a top surface of the gate structure of the first transistor and the first dielectric layer;

[0009] Grinding and removing the second dielectric layer on the second transistor to expose the gate structure of the second transistor, wherein the top surface of the gate structure of the second transistor is flush with the top surface of the second dielectric layer on the gate structure of the first transistor;

[0010] The second dielectric layer and the entire first dielectric layer between the gate structures of the first transistor are removed.

[0011] In one embodiment, after forming the first dielectric layer, a photoresist layer is formed on the second transistor, wherein the photoresist layer covers the first dielectric layer on the second transistor;

[0012] The first dielectric layer on the first transistor is etched to expose the top surface of the gate structure of the first transistor, and then the photoresist layer is removed.

[0013] In one embodiment, removing the second dielectric layer and the entire first dielectric layer between the gate structures of the first transistor includes:

[0014] Etching and removing a portion of the second dielectric layer to expose the first dielectric layer between the first transistors, and etching and retaining the second dielectric layer to cover the top surface of the gate structure of the first transistor;

[0015] The first dielectric layer is completely removed by etching.

[0016] In one embodiment, the gate structure of the first transistor includes a first gate electrode disposed on the substrate and an insulating stack covering the first gate electrode;

[0017] The gate structure of the second transistor includes a second gate electrode disposed on the substrate and the insulating stack covering the second gate electrode;

[0018] The insulating stack includes a first insulating layer, a second insulating layer and a third insulating layer stacked in sequence. The third insulating layer on the top of the first transistor and a portion of the second insulating layer are etched away during the manufacturing process so that the height of the top surface of the gate structure of the first transistor is lower than the height of the top surface of the gate structure of the second transistor.

[0019] In one embodiment, grinding and removing the second dielectric layer on the second transistor to expose the gate structure of the second transistor includes:

[0020] The second dielectric layer and the third insulating layer on the second insulating layer are ground with the top surface of the second insulating layer as a grinding end point.

[0021] In one embodiment, the material of the second dielectric layer is the same as the material of the second insulating layer.

[0022] In one embodiment, the manufacturing method further comprises:

[0023] The second dielectric layer is oxidized, and the material of the oxidized second dielectric layer is the same as the material of the second insulating layer.

[0024] In one embodiment, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

[0025] In a second aspect, the present disclosure provides a semiconductor structure, comprising:

[0026] substrate;

[0027] A first transistor is disposed on the substrate, wherein the gate structure of the first transistor comprises a first gate electrode disposed on the substrate and a first insulating sidewall covering the first gate electrode;

[0028] a second transistor, disposed on the substrate, wherein the gate structure of the second transistor comprises a second gate electrode disposed on the substrate and a second insulating sidewall covering the second gate electrode, and the top surface of the first insulating sidewall is flush with the top surface of the second insulating sidewall;

[0029] The first insulating sidewall comprises a first insulating layer, a second insulating layer and a third insulating layer sequentially covering the first gate electrode, wherein the third insulating layer is disconnected at the top of the first gate electrode to expose the top surface of the second insulating layer;

[0030] The second insulating sidewall includes the first insulating layer, the second insulating layer, the third insulating layer and the second dielectric layer which sequentially cover the second gate electrode, the third insulating layer is disconnected at the top of the second gate electrode, and the second dielectric layer covers the top surfaces of the second insulating layer and the third insulating layer.

[0031] In one embodiment, the material of the second dielectric layer is the same as the material of the second insulating layer;

[0032] The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

[0033] The semiconductor structure and the manufacturing method thereof disclosed in the present invention control the etching endpoint of the first dielectric layer and the grinding endpoint of the second dielectric layer to remove the second dielectric layer on the second transistor and retain the second dielectric layer on the gate structure of the first transistor. The top surface of the second dielectric layer on the gate structure of the first transistor is flush with the top surface of the gate structure of the second transistor, thereby solving the problem of height difference between the first transistor and the second transistor. The transistor height of the semiconductor structure is uniform, which is beneficial to the execution and control of subsequent processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 is a process flow chart of a method for manufacturing a semiconductor provided in an embodiment;

[0036] Figure 2 A schematic diagram of a substrate provided in an embodiment, on which a first transistor and a second transistor are formed;

[0037] Figure 3 A schematic diagram of a structure after forming a first dielectric layer provided in an embodiment;

[0038] Figure 4 is a schematic diagram of a structure after a photoresist layer is formed provided in an embodiment;

[0039] Figure 5 A schematic diagram of a structure after etching the first dielectric layer on the first transistor using the top surface of the gate structure of the first transistor as an etching endpoint provided in an embodiment;

[0040] Figure 6 is a schematic diagram of a structure after forming a second dielectric layer provided in an embodiment;

[0041] Figure 7 A schematic diagram of a structure after the second dielectric layer is ground with the top surface of the second insulating layer as the grinding end point provided in an embodiment;

[0042] Figure 8 A schematic diagram of a structure after etching the second dielectric layer to form an opening to expose the first dielectric layer provided in an embodiment;

[0043] Fig. 9 A schematic diagram of a semiconductor structure formed in accordance with an embodiment;

[0044] Fig.10 A schematic structural diagram of a semiconductor structure formed according to another embodiment.

[0045] Description of reference numerals:

[0046] 10. substrate; 21. first transistor; 211. gate structure of the first transistor; 212. first source; 213. first drain; 22. second transistor; 221. gate structure of the second transistor; 223. first gate electrode; 24. second gate electrode; 25. insulating stack; 251. first insulating layer; 252. second insulating layer; 253. third insulating layer; 26. second insulating sidewall; 27. first insulating sidewall; 30. first dielectric layer; 40. second dielectric layer; 41. opening; 50. photoresist layer. DETAILED DESCRIPTION

[0047] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0049] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0050] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0051] As described in the background art, due to the difference in manufacturing processes between NMOS transistors and PMOS transistors, the height of the PMOS transistor is often lower than that of the NMOS transistor.

[0052] In advanced semiconductor manufacturing processes, stress is becoming increasingly important to the electrical properties of devices. Stress can change the energy gap and carrier mobility of silicon materials. The driving current of MOS transistors can be increased by controlling stress, thereby improving the performance of MOS transistors. At present, the production of PMOS transistors uses embedded SiGe technology to form a SiGe stress layer in the source and drain regions of the PMOS transistor, and the compressive stress formed by the lattice mismatch between silicon and SiGe is used to improve the performance of the PMOS transistor. However, in the process of forming the SiGe stress layer using the embedded SiGe technology, the insulating sidewall on the gate of the PMOS transistor is etched and consumed, resulting in the height of the gate of the PMOS transistor being lower than the height of the gate of the NMOS transistor, which affects the execution of subsequent steps of the semiconductor structure.

[0053] According to an exemplary embodiment, the present disclosure provides a method for manufacturing a semiconductor structure, referring to Figure 1 As shown, the method for manufacturing a semiconductor structure includes the following steps:

[0054] Step S10: providing a substrate, on which a first transistor and a second transistor are formed, wherein a top surface of a gate structure of the first transistor is lower than a top surface of a gate structure of the second transistor;

[0055] Step S20: forming a first dielectric layer, the first dielectric layer covering the first transistor and the second transistor, the top surface of the first dielectric layer being higher than the top surface of the gate structure of the second transistor;

[0056] Step S30: etching the first dielectric layer on the first transistor with the top surface of the gate structure of the first transistor as an etching end point to expose the top surface of the gate structure of the first transistor;

[0057] Step S40: forming a second dielectric layer, wherein the second dielectric layer covers the top surface of the gate structure of the first transistor and the first dielectric layer;

[0058] Step S50: grinding and removing the second dielectric layer on the second transistor to expose the gate structure of the second transistor, wherein the top surface of the gate structure of the second transistor is flush with the top surface of the second dielectric layer on the gate structure of the first transistor;

[0059] Step S60: removing the second dielectric layer between the gate structures of the first transistor and the entire first dielectric layer.

[0060] The method for manufacturing the semiconductor structure of the present embodiment controls the etching endpoint of the first dielectric layer and the grinding endpoint of the second dielectric layer to remove the second dielectric layer on the second transistor and retain the second dielectric layer on the gate structure of the first transistor. The top surface of the second dielectric layer on the gate structure of the first transistor is flush with the top surface of the gate structure of the second transistor, thereby solving the problem of height difference between the first transistor and the second transistor. The transistors of the semiconductor structure have uniform height, which is beneficial to the execution and control of subsequent processes.

[0061] In step S10, referring to Figure 2 As shown, a substrate 10 is provided, and the substrate 10 may be a semiconductor substrate, and the material of the semiconductor substrate may include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP) or other III / V semiconductor materials or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate may be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator.

[0062] A first transistor 21 and a second transistor 22 are formed on the substrate 10. The first transistors 21, the second transistors 22, and the first transistor 21 and the second transistor 22 are spaced apart from each other.

[0063] In some embodiments, the first transistor 21 is a PMOS transistor, and the second transistor 22 is an NMOS transistor.

[0064] The first transistor 21 includes a gate structure 211 disposed on the substrate 10 , and a first source 212 and a first drain 213 disposed on both sides of the gate structure 211 .

[0065] The second transistor 22 includes a gate structure 221 disposed on the substrate 10 and a second source (not shown in the figure) and a second drain (not shown in the figure) disposed on both sides of the gate structure 221. The second source and the second drain are formed by doping the substrate 10 on both sides of the gate structure 221 of the second transistor 22.

[0066] Among them, refer to Figure 2 As shown, the first source 212 and the first drain 213 are formed by etching the substrate 10 on both sides of the gate structure 211 of the first transistor 21 to form a source trench and a drain trench, and then a germanium silicon layer is epitaxially formed on the surface of the substrate 10 exposed by the source trench and the drain trench, and the germanium silicon layer in the source trench and the drain trench is used as the first source 212 and the first drain 213 of the first transistor 21 to increase the driving current of the first transistor 21 and to improve the performance of the first transistor 21.

[0067] In the process of etching the substrate 10 on both sides of the gate structure 211 of the first transistor 21 to form a source trench and a drain trench, the top of the gate structure 211 of the first transistor 21 is etched away, resulting in the height of the gate structure 211 of the first transistor 21 being lower than the height of the gate structure 221 of the second transistor 22.

[0068] In step S20, referring to Figure 3 As shown, a first dielectric layer 30 may be deposited by a chemical vapor deposition process (CVD) or an atomic layer deposition process (ALD), and the first dielectric layer 30 covers the first transistor 21 and the second transistor 22, and fills the trenches between the first transistors 21, between the second transistors 22, and between the first transistor 21 and the second transistor 22. The top surface of the first dielectric layer 30 is higher than the top surface of the gate structure 221 of the second transistor 22.

[0069] For example, the material of the first dielectric layer 30 may include silicon oxide, silicon oxynitride, silicon oxycarbide, or the like.

[0070] In this embodiment, the material of the first dielectric layer 30 includes silicon oxide.

[0071] In step S30, referring to Figure 4 As shown, after the first dielectric layer 30 is formed, a photoresist layer 50 is formed on the second transistor 22 , and the photoresist layer 50 covers the first dielectric layer 30 on the second transistor 22 .

[0072] Then, refer to Figure 4 , Figure 5 As shown, the first dielectric layer 30 not covered by the photoresist layer 50 is etched using a dry process until the top surface of the gate structure 211 of the first transistor 21 is exposed.

[0073] After the first dielectric layer 30 on the first transistor 21 is etched to expose the top surface of the gate structure 211 of the first transistor 21 , the photoresist layer 50 is removed.

[0074] In step S40, referring to Figure 6 As shown, a second dielectric layer 40 is formed by deposition, and the second dielectric layer 40 covers the top surface of the gate structure 211 of the first transistor 21 and the first dielectric layer 30 .

[0075] The material of the second dielectric layer 40 has a high etching ratio with the material of the first dielectric layer 30 .

[0076] For example, the material of the second dielectric layer 40 may include at least one of silicon or silicon oxide.

[0077] In one example, the material of the first dielectric layer 30 includes silicon oxide, and the material of the second dielectric layer 40 includes silicon; in another example, the material of the first dielectric layer 30 includes silicon oxycarbide, and the material of the second dielectric layer 40 includes silicon oxide.

[0078] In this embodiment, the material of the second dielectric layer 40 includes silicon, and the second dielectric layer 40 may be formed by depositing silicon in a furnace.

[0079] In step S50, referring to Figure 7 As shown, the second dielectric layer 40 is ground by a chemical mechanical polishing (CMP) process, and the second dielectric layer 40 on the second transistor 22 is completely ground away, and only a portion of the second dielectric layer 40 located on the first transistor 21 is retained, so that the top surface of the second dielectric layer 40 retained on the gate structure 211 of the first transistor 21 is flush with the top surface of the gate structure 221 of the second transistor 22, and the height difference between the gate structure 211 of the first transistor 21 and the gate structure 221 of the second transistor 22 is eliminated by the second dielectric layer 40 retained on the gate structure 211 of the first transistor 21.

[0080] In one embodiment, referring to Figure 2 The gate structure 211 of the first transistor 21 includes a first gate electrode 23 disposed on the substrate 10 and an insulating stack 25 covering the first gate electrode 23, and the first gate electrode 23 includes a first gate conductive layer and a first gate isolation layer stacked in sequence on the substrate 10; the gate structure 221 of the second transistor 22 includes a second gate electrode 24 disposed on the substrate 10 and an insulating stack 25 covering the second gate electrode 24, and the second gate electrode 24 includes a second gate conductive layer and a second gate isolation layer stacked in sequence on the substrate 10.

[0081] The insulating stack 25 includes a first insulating layer 251, a second insulating layer 252 and a third insulating layer 253 stacked in sequence. The third insulating layer 253 on the top of the first transistor 21 and a portion of the second insulating layer 252 are etched away during the process so that the height of the top surface of the gate structure 211 of the first transistor 21 is lower than the height of the top surface of the gate structure 221 of the second transistor 22.

[0082] The first insulating layer 251 and the third insulating layer 253 may include nitride materials, the second insulating layer 252 may include oxide materials, and the insulating stack 25 is a NON stack. For example, the materials of the first insulating layer 251 and the third insulating layer 253 include silicon nitride, and the material of the second insulating layer 252 includes silicon oxide.

[0083] It can be understood that in the process of etching the substrate 10 on both sides of the gate structure 211 of the first transistor 21 to form the source trench and the drain trench, a photoresist material is first coated to cover the second transistor 22, and then the insulating stack 25 covering the surface of the substrate 10 is etched away to expose the substrate 10, and then the substrate 10 can be etched to form the source trench and the drain trench. When etching the insulating stack 25 on the surface of the substrate 10, the third insulating layer 253 and part of the second insulating layer 252 of the insulating stack 25 on the first gate electrode 23 are etched away, resulting in the height of the top surface of the gate structure 211 of the first transistor 21 being lower than the height of the top surface of the gate structure 221 of the second transistor 22, and in particular, the thickness of the second insulating layer 252 on the top surface of the first gate electrode 23 is less than the thickness of the insulating layer on the second gate electrode 24.

[0084] In one embodiment, referring to Figure 7 Step S50 is to grind away the second dielectric layer 40 on the second transistor 22 to expose the gate structure 221 of the second transistor 22, including: grinding the second dielectric layer 40 and the third insulating layer 253 on the second insulating layer 252 with the top surface of the second insulating layer 252 as the grinding end point.

[0085] The second dielectric layer 40 is polished by chemical mechanical polishing process to expose the third insulating layer 253 of the second transistor 22, and then the third insulating layer 253 and the second dielectric layer 40 are polished until the second insulating layer 252 of the second transistor 22 is exposed and the polishing is stopped. The top surface of the second dielectric layer 40 retained on the first transistor 21 is flush with the top surface of the second insulating layer 252 of the second transistor 22.

[0086] Reference Figure 8 The insulating stack 25 retained by etching the gate structure 221 of the second transistor 22 is formed into a second insulating sidewall 26 of the second transistor 22, and the third insulating layer 253 of the second insulating sidewall 26 is disconnected at the top of the gate structure 221 of the second transistor 22, exposing the top surface of the second insulating layer 252.

[0087] In one embodiment, removing the second dielectric layer 40 between the gate structures 211 of the first transistor 21 and the entire first dielectric layer 30 includes:

[0088] Step S61 : etching and removing a portion of the second dielectric layer 40 to expose the first dielectric layer 30 between the first transistors 21 , and etching the remaining second dielectric layer 40 to cover the top surface of the gate structure 211 of the first transistor 21 .

[0089] Reference Figure 8As shown, a mask layer (not shown in the figure) is formed, the mask layer covers the top surface of the gate structure 221 of the second transistor 22, the first dielectric layer 30 between the second transistors 22, and a portion of the top surface of the second dielectric layer 40, the mask layer has a mask pattern, and the mask pattern exposes a portion of the second dielectric layer 40.

[0090] The second dielectric layer 40 is etched according to the mask layer to remove the second dielectric layer 40 exposed by the mask layer, and an opening 41 is formed in the second dielectric layer 40 . The opening 41 exposes the first dielectric layer 30 between the first transistors 21 .

[0091] For example, the second dielectric layer 40 is etched using a dry process.

[0092] Step S62: etching and removing the entire first dielectric layer 30 .

[0093] Reference Fig. 9 As shown, the entire first dielectric layer 30 can be etched away by a wet process, and an etching solution can be sprayed onto the exposed first dielectric layer 30 to remove the first dielectric layer 30, thereby releasing the grooves between the first transistors 21, between the second transistors 22, and between the first transistor 21 and the second transistor 22, so as to facilitate the execution of subsequent processes of the semiconductor structure.

[0094] The remaining second dielectric layer 40 is etched to cover the top surface of the insulating stack 25 of the first transistor 21 .

[0095] In one embodiment, the material of the second dielectric layer 40 is the same as the material of the second insulating layer 252. For example, the materials of the second dielectric layer 40 and the second insulating layer 252 both include silicon oxide. Fig. 9 As shown, the remaining second dielectric layer 40 on the first transistor 21 and the insulating stack 25 of the first transistor 21 together form the first insulating sidewall 27 of the first transistor 21, and the thickness of the silicon oxide on the top surface of the first gate electrode 23 is the same as the thickness of the silicon oxide on the top surface of the second gate electrode 24.

[0096] In one embodiment, the material of the second insulating layer 252 includes silicon oxide, and the material of the second dielectric layer 40 includes silicon. After step S70 , the manufacturing method further includes: oxidizing the second dielectric layer 40 , wherein the material of the oxidized second dielectric layer 40 is the same as that of the second insulating layer 252 .

[0097] For example, the second dielectric layer 40 can be oxidized by a diffusion furnace or a rapid thermal process to oxidize the silicon in the second dielectric layer 40 into silicon oxide, as shown in FIG. Fig.10As shown, the oxidized second dielectric layer 40 and the insulating stack 25 of the first transistor 21 together form the first insulating sidewall 27 of the first transistor 21 , and the thickness of silicon oxide on the top surface of the first gate electrode 23 is the same as the thickness of silicon oxide on the top surface of the second gate electrode 24 .

[0098] The method for manufacturing the semiconductor structure of the present embodiment compensates for the height difference between the gate structure 211 of the first transistor 21 and the gate structure 221 of the second transistor 22 through the second dielectric layer 40, so that the height of the gate structure 211 of the first transistor 21 is flush with the height of the gate structure 221 of the second transistor 22, which is beneficial to adjusting the height accuracy of the gate structure 211 of the first transistor 21 and the gate structure 221 of the second transistor 22, and is of great significance to the process control and product yield of the semiconductor structure; at the same time, the method for manufacturing the semiconductor structure of the present embodiment has a simple process and is easy to operate, which is beneficial to reducing the manufacturing cost and improving the product yield.

[0099] According to an exemplary embodiment, this embodiment provides a semiconductor structure, referring to Fig. 9 or Fig.10 As shown, the semiconductor structure includes a substrate 10 and a first transistor 21 and a second transistor 22 disposed on the substrate 10; the gate structure 211 of the first transistor 21 includes a first gate electrode 23 disposed on the substrate 10 and a first insulating sidewall 27 covering the first gate electrode 23, wherein the first gate electrode 23 includes a first gate conductive layer and a first gate isolation layer sequentially stacked on the substrate 10; the gate structure 221 of the second transistor 22 includes a second gate electrode 24 disposed on the substrate 10 and a second insulating sidewall 26 covering the second gate electrode 24, wherein the second gate electrode 24 includes a second gate conductive layer and a second gate isolation layer sequentially stacked on the substrate 10, wherein the first insulation layer The height of the top surface of the side wall 27 is flush with the height of the top surface of the second insulating side wall 26; the first insulating side wall 27 includes a first insulating layer 251, a second insulating layer 252 and a third insulating layer 253 that sequentially cover the first gate electrode 23, and the third insulating layer 253 is disconnected at the top of the first gate electrode 23 to expose the top surface of the second insulating layer 252; the second insulating side wall 26 includes a first insulating layer 251, a second insulating layer 252, a third insulating layer 253 and a second dielectric layer 40 that sequentially cover the second gate electrode 24, the third insulating layer 253 is disconnected at the top of the second gate electrode 24, and the second dielectric layer 40 covers the top surfaces of the second insulating layer 252 and the third insulating layer 253.

[0100] The first insulating layer 251 and the third insulating layer 253 may include nitride materials, the second insulating layer 252 may include oxide materials, and the insulating stack 25 is a NON stack. For example, the materials of the first insulating layer 251 and the third insulating layer 253 include silicon nitride, and the material of the second insulating layer 252 includes silicon oxide.

[0101] In the semiconductor structure of this embodiment, the top surfaces of the gate structure 211 of the first transistor 21 and the gate structure 221 of the second transistor 22 are flush with each other, thereby solving the problem of height difference between the first transistor 21 and the second transistor 22. The transistor height of the semiconductor structure is uniform, which is beneficial to the execution and control of subsequent processes.

[0102] In one embodiment, referring to Fig. 9 or Fig.10 As shown, the material of the second dielectric layer 40 is the same as the material of the second insulating layer 252; in this embodiment, the material of the second insulating layer 252 is silicon oxide, the material of the second dielectric layer 40 is silicon oxide, and the thickness of the silicon oxide on the top surface of the first gate electrode 23 is the same as the thickness of the silicon oxide on the top surface of the second gate electrode 24.

[0103] In one embodiment, referring to Fig. 9 or Fig.10 As shown, the first transistor 21 is a PMOS transistor, and the second transistor 22 is an NMOS transistor.

[0104] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: Providing a substrate, on which a first transistor and a second transistor are formed, wherein a top surface of a gate structure of the first transistor has a height lower than a top surface of a gate structure of the second transistor; forming a first dielectric layer, wherein the first dielectric layer covers the first transistor and the second transistor, and a top surface of the first dielectric layer is higher than a top surface of a gate structure of the second transistor; Etching the first dielectric layer on the first transistor with the top surface of the gate structure of the first transistor as an etching end point to expose the top surface of the gate structure of the first transistor; forming a second dielectric layer, wherein the second dielectric layer covers a top surface of the gate structure of the first transistor and the first dielectric layer; Grinding and removing the second dielectric layer on the second transistor to expose the gate structure of the second transistor, wherein the top surface of the gate structure of the second transistor is flush with the top surface of the second dielectric layer on the gate structure of the first transistor; The second dielectric layer and the entire first dielectric layer between the gate structures of the first transistor are removed.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: After forming the first dielectric layer, forming a photoresist layer on the second transistor, wherein the photoresist layer covers the first dielectric layer on the second transistor; The first dielectric layer on the first transistor is etched to expose the top surface of the gate structure of the first transistor, and then the photoresist layer is removed.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Removing the second dielectric layer and the entire first dielectric layer between the gate structures of the first transistor, comprising: Etching and removing a portion of the second dielectric layer to expose the first dielectric layer between the first transistors, and etching and retaining the second dielectric layer to cover the top surface of the gate structure of the first transistor; The first dielectric layer is completely removed by etching.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The gate structure of the first transistor includes a first gate electrode disposed on the substrate and an insulating stack covering a sidewall of the first gate electrode; The gate structure of the second transistor includes a second gate electrode disposed on the substrate and the insulating stack covering the second gate electrode; The insulating stack includes a first insulating layer, a second insulating layer and a third insulating layer stacked in sequence. The third insulating layer on the top of the first transistor and a portion of the second insulating layer are etched away during the manufacturing process so that the height of the top surface of the gate structure of the first transistor is lower than the height of the top surface of the gate structure of the second transistor.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: Grinding and removing the second dielectric layer on the second transistor to expose the gate structure of the second transistor includes: The second dielectric layer and the third insulating layer on the second insulating layer are ground with the top surface of the second insulating layer as a grinding end point.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The material of the second dielectric layer is the same as that of the second insulating layer.

7. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The production method further comprises: The second dielectric layer is oxidized, and the material of the oxidized second dielectric layer is the same as the material of the second insulating layer.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

9. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1 to 8, wherein the semiconductor structure comprises: substrate; A first transistor is disposed on the substrate, wherein the gate structure of the first transistor comprises a first gate electrode disposed on the substrate and a first insulating sidewall covering the first gate electrode; a second transistor, disposed on the substrate, wherein the gate structure of the second transistor comprises a second gate electrode disposed on the substrate and a second insulating sidewall covering the second gate electrode, and the top surface of the first insulating sidewall is flush with the top surface of the second insulating sidewall; The first insulating sidewall comprises a first insulating layer, a second insulating layer and a third insulating layer sequentially covering the first gate electrode, wherein the third insulating layer is disconnected at the top of the first gate electrode to expose the top surface of the second insulating layer; The second insulating sidewall includes the first insulating layer, the second insulating layer, the third insulating layer and the second dielectric layer which sequentially cover the second gate electrode, the third insulating layer is disconnected at the top of the second gate electrode, and the second dielectric layer covers the top surfaces of the second insulating layer and the third insulating layer.

10. The semiconductor structure according to claim 9, characterized in that: The material of the second dielectric layer is the same as the material of the second insulating layer; The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

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