Semiconductor structure and method of manufacturing the same

Abstract

The embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a multilayer sealing ring; a plurality of multilayer dummy structures, the number of dummy structures in each layer includes a plurality, the plurality of dummy structures are arranged in an array, the array contains a plurality of rows, and the plurality of dummy structures at least include a part located on at least one side of the sealing ring. A plurality of multilayer first connection structures, in at least part of the rows of each layer, the first connection structures are arranged alternately with the dummy structures, and at least part of the dummy structures in the same row are connected to each other; at the same time, the first connection structures also connect one end of the mutually connected dummy structures and the sealing ring. A plurality of multilayer second connection structures, the second connection structures connect the sealing rings located in different layers to each other.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for preparing the same. Background Technology

[0002] With the development of semiconductor technology, the vertical thermal resistance of multi-wafer stacks gradually increases with the number of stacked layers, and the heat dissipation path lengthens, making internal thermal management particularly important. For example, in multi-stacked, highly integrated, and high-power products like HBMs, heat is difficult to dissipate in time under high loads, causing it to accumulate inside the chip and affecting the device's performance and stability. Summary of the Invention

[0003] This disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0004] Multi-layer sealing ring;

[0005] The multi-layered dummy structure includes multiple dummy structures in each layer, which are arranged in an array containing multiple rows. Each dummy structure includes at least one portion located on at least one side of the sealing ring.

[0006] In a multi-layered first connection structure, in at least a portion of the rows of each layer, the first connection structure and the dummy structure are arranged alternately, and at least a portion of the dummy structures located in the same row are interconnected; at the same time, the first connection structure also connects one end of the interconnected dummy structures to the sealing ring;

[0007] A multi-layered second connection structure connects the sealing rings located in different layers to each other.

[0008] In some embodiments, the sealing ring includes: a multi-layer first sealing ring and a multi-layer discontinuously distributed heat dissipation structure, wherein the heat dissipation structure is located between the first sealing ring and the dummy structure and is not connected to the first sealing ring; wherein, the first connecting structure connects one end of the dummy structure to the heat dissipation structure, and the second connecting structure connects the heat dissipation structures located in different layers to each other.

[0009] In some embodiments, the ratio of the size of the heat dissipation structure to the size of the dummy structure in the extending direction of the heat dissipation structure ranges from 2.5 to 4.5.

[0010] In some embodiments, one end of one of the multiple interconnected dummy structures is connected to the same section of the heat dissipation structure.

[0011] In some embodiments, each of the virtual structures in the same row is interconnected by the first connection structure, or some of the virtual structures in the same row are interconnected by the first connection structure.

[0012] In some embodiments, the projections of the heat dissipation structures located in different layers in the thickness direction of the dummy structure at least partially overlap.

[0013] In some embodiments, the semiconductor structure further includes a third connection structure that connects at least a portion of the first connection structure between the dummy structures located on the same layer but in different rows.

[0014] This disclosure also provides a method for fabricating a semiconductor structure, the method comprising:

[0015] A multi-layer sealing ring and a multi-layer dummy structure are formed, wherein the number of dummy structures in each layer includes multiple dummy structures, the multiple dummy structures are arranged in an array, the array includes multiple rows, and the multiple dummy structures include at least a portion located on at least one side of the sealing ring;

[0016] A multi-layered first connection structure is formed, wherein in at least a portion of the rows of each layer, the first connection structure and the dummy structure are arranged alternately, and at least a portion of the dummy structures located in the same row are interconnected; at the same time, the first connection structure also connects one end of the interconnected dummy structures to the sealing ring;

[0017] A multi-layered second connection structure is formed, which connects the sealing rings located in different layers to each other.

[0018] In some embodiments, forming multiple layers of the sealing ring includes:

[0019] A multi-layered first sealing ring and a multi-layered discontinuously distributed heat dissipation structure are formed. The heat dissipation structure is located between the first sealing ring and the dummy structure, and the heat dissipation structure is not connected to the first sealing ring. The first connecting structure connects one end of the dummy structure to the heat dissipation structure, and the second connecting structure connects the heat dissipation structures located in different layers.

[0020] In some embodiments, the preparation method further includes:

[0021] A third connection structure is formed, which interconnects at least a portion of the first connection structures between the virtual structures located on the same layer but in different rows.

[0022] The semiconductor structure and its fabrication method provided in this disclosure include: a multilayer sealing ring; a multilayer dummy structure, each layer containing multiple dummy structures arranged in an array, the array comprising multiple rows, each dummy structure including at least one portion located on at least one side of the sealing ring; a multilayer first connecting structure, in at least a portion of the rows of each layer, the first connecting structure and the dummy structures are alternately arranged, and at least a portion of the dummy structures located in the same row are interconnected; simultaneously, the first connecting structure also connects one end of the interconnected dummy structures to the sealing ring; and a multilayer second connecting structure, the second connecting structure connecting the sealing rings located in different layers. In this disclosure, at least a portion of the dummy structures in some rows of each layer are connected in a plane parallel to the pattern of each layer through the first connecting structure, and then one end of the interconnected dummy structures in the same row is connected to the sealing ring, thus providing a dissipation path for heat in the semiconductor structure in a plane parallel to the pattern of each layer. Building upon this, the connection between the multi-layered sealing rings via a second connecting structure further provides a vertical heat dissipation path for the semiconductor structure. This effectively removes heat from the multi-layered semiconductor structure to its surface, improving its performance and stability.

[0023] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and drawings. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0026] Figure 2 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0027] Figure 3 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0028] Figure 4 This is a schematic diagram illustrating a connection between virtual structures provided in an embodiment of the present disclosure;

[0029] Figure 5 A schematic diagram illustrating another connection between virtual structures provided in an embodiment of this disclosure;

[0030] Figure 6 A schematic diagram illustrating another method for connecting virtual structures according to an embodiment of this disclosure;

[0031] Figure 7 Schematic diagrams of the dummy structures provided in different embodiments of this disclosure;

[0032] Figure 8 This is a schematic diagram of the interconnected structure of the multi-layer sealing rings provided in the embodiments of this disclosure;

[0033] Figure 9 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure.

[0034] Figure 10 This is one of the process flow diagrams for a method of fabricating a semiconductor structure provided in this disclosure;

[0035] Figure 11 A second process flow diagram of the method for fabricating a semiconductor structure provided in this disclosure;

[0036] Figure 12 The third process flow diagram for the fabrication method of the semiconductor structure provided in this disclosure;

[0037] Figure 13 The semiconductor structure provided in the embodiments of this disclosure is fabricated along the following process: Figure 11 Detailed sectional view along the B1-B2 direction;

[0038] Figure 14 The semiconductor structure provided in the embodiments of this disclosure is fabricated along the following process: Figure 11 Detailed sectional views in the A1-A2 and B1-B2 directions;

[0039] Figure 15 The semiconductor structure provided in the embodiments of this disclosure is fabricated along the following process: Figure 12 Detailed sectional views in the A1-A2 and B1-B2 directions. Detailed Implementation

[0040] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0041] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0042] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0043] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0044] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0046] In the application of semiconductor structures, as users' requirements for integration and functionality continue to increase, the heat dissipation problem of semiconductor structures has become a major concern. In multi-wafer or stacked chip structures, there is often an increase in vertical thermal resistance and a longer heat dissipation path, which leads to severe heat generation inside the chip, especially under high load conditions. This can easily cause heat to accumulate inside the chip, affecting performance and stability, and thus potentially causing thermal problems during use.

[0047] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0048] This disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0049] Multi-layer sealing ring;

[0050] The multi-layered dummy structure includes multiple dummy structures in each layer, which are arranged in an array containing multiple rows. Each dummy structure includes at least one portion located on at least one side of the sealing ring.

[0051] In a multi-layered first connection structure, in at least a portion of the rows of each layer, the first connection structure and the dummy structure are arranged alternately, and at least a portion of the dummy structures located in the same row are interconnected; at the same time, the first connection structure also connects one end of the interconnected dummy structures to the sealing ring;

[0052] A multi-layered second connection structure connects the sealing rings located in different layers to each other.

[0053] In this embodiment, at least some dummy structures in some rows of each layer are connected by a first connecting structure in a plane parallel to the pattern of each layer. Then, one end of each interconnected dummy structure in the same row is connected to a sealing ring, providing a heat dissipation path in the plane parallel to the pattern of each layer for the semiconductor structure. Furthermore, the connection between the multiple sealing rings via a second connecting structure further provides a vertical heat dissipation path for the semiconductor structure. In this way, heat in the multi-layered stacked semiconductor structure can be effectively dissipated to the surface of the semiconductor structure, improving the various performance characteristics and stability of the semiconductor structure.

[0054] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, the schematic diagrams may be partially enlarged off-scale for ease of explanation, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0055] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figure 3 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figure 4 This is a schematic diagram illustrating a connection between virtual structures provided in an embodiment of the present disclosure; Figure 5 A schematic diagram illustrating another connection between virtual structures provided in an embodiment of this disclosure; Figure 6 A schematic diagram illustrating another method for connecting virtual structures according to an embodiment of this disclosure; Figure 7 Schematic diagrams of the dummy structures provided in different embodiments of this disclosure; Figure 8 This is a schematic diagram of the interconnected structure of the multi-layer sealing rings provided in an embodiment of this disclosure.

[0056] The semiconductor structure provided in the embodiments of this disclosure will now be described in further detail with reference to the accompanying drawings.

[0057] like Figures 1 to 3 as well as Figure 8 As shown, the semiconductor structure includes:

[0058] Multi-layer sealing ring 11;

[0059] The multi-layer dummy structure 12 includes multiple dummy structures 12 in each layer, and the multiple dummy structures 12 are arranged in an array, the array containing multiple rows R, and the multiple dummy structures 12 include at least one portion located on at least one side of the sealing ring 11.

[0060] In the multi-layer first connection structure 13, in at least a portion of the rows R of each layer, the first connection structure 13 and the dummy structure 12 are arranged alternately, and at least a portion of the dummy structures 12 located in the same row are connected to each other; at the same time, the first connection structure 13 also connects one end of the interconnected dummy structures 12 to the sealing ring 11.

[0061] The second connection structure 14 is a multi-layered structure that connects the sealing rings 44 located in different layers to each other.

[0062] In some embodiments, the semiconductor structure includes a device region (not shown) and a peripheral region (not shown), with a sealing ring disposed around the device region (not shown).

[0063] In some embodiments, a chip, semiconductor device, or semiconductor structure with device functionality may be disposed on the device region, and a sealing ring is used to protect the structure on the semiconductor structure from damage during wafer dicing. Here, the semiconductor structure may include, but is not limited to, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Phase-Change Memory (PCM), NAND flash memory, or Nor Flash memory. Furthermore, it can also be used in processors, GPUs, etc.

[0064] The sealing ring of this embodiment can be applied to both wafer bonding structures and non-bonded structures to improve the wafer's resistance to crack intrusion during the dicing process, improve the yield of the wafer dicing process, and reduce the risk of debonding of the bonding structure during the dicing process.

[0065] In some embodiments, the semiconductor structure may be a bonded multilayer wafer or a multilayer bonded chipset structure, each chipset structure containing multiple chips that are not yet separated.

[0066] In some embodiments, the sealing ring may be located on the peripheral area.

[0067] In other embodiments, the sealing ring may also be located on the cleaving channel between chips, or may be set at both of the above locations or at any other required location.

[0068] Understandably, sealing rings can absorb stress during wafer dicing or chip-to-chip separation, reducing defects such as fractures and cracks in semiconductor structures caused by dicing stress.

[0069] In some embodiments, the dummy structure can be located at a position where there is no normal pattern structure or the spacing between normal pattern structures is large, thereby reducing the problem of uneven pattern density distribution at various positions. This can effectively prevent or reduce the inconsistency in process speed caused by uneven pattern density distribution at various positions during the process, and help to obtain the desired structure and a good surface morphology.

[0070] It should be noted that, in addition to balancing uneven pattern density as described above, dummy structures in semiconductor structures can also perform other functions, which will not be listed here. Furthermore, in any embodiment of this disclosure, the dummy structure is a physical structure located within the semiconductor structure; that is, the dummy structure is a structure that truly exists in the region where it is set. In practice, these dummy structures can be obtained through processes such as material deposition, etching, and filling.

[0071] like Figure 7 As shown, in some embodiments, the dummy structure can be a pattern structure of any shape, including but not limited to any one or a combination of squares, rectangles, circles, ellipses, parallelograms, polygons and irregular shapes.

[0072] In some embodiments, the number of layers of sealing ring 11 may be the same as the number of wafers or the number of chipsets of multiple chips that have not yet been separated, but is not limited thereto. Multiple layers of sealing rings stacked in the vertical direction may also be provided on a single wafer or a chipset of multiple chips that have not yet been separated.

[0073] The number of layers of the sealing ring 11 provided in this embodiment is denoted as n, where n is a positive integer greater than or equal to 2. For example, n can be 2, 3, 4, 5, 6, 7, 8, 9, 10, a dozen, several dozen, hundreds, or even more; 2≤i≤n. In this embodiment, the arrangement, connection relationship, and relationship between the virtual structure and the sealing ring will be described using the i-th layer as an example.

[0074] It should be noted that, in the embodiments disclosed herein... Figures 1 to 6 In this example, the first sealing ring and the dummy structure of the i-th layer are selected to illustrate the technical solution provided in this disclosure embodiment. This is merely an illustrative example and is not the only limitation on the application scenarios of this disclosure embodiment. In fact, the sealing ring 11, the dummy structure 12, and the connection relationship between the two from the 1st layer to the nth layer can all be obtained by using the processing method of the i-th layer or by slight modifications.

[0075] In some embodiments, such as Figure 1As shown, the sealing ring 11 includes multiple layers of first sealing rings 111, at least a portion of the first sealing rings 111 extending along the second direction. When the first sealing rings 111 are disposed around the device area, the first sealing rings 111 may also include portions extending along the first direction, or even portions extending along other directions, without specific limitations here.

[0076] In this embodiment, there are multiple first sealing rings 111. One of the first sealing rings 111 adjacent to the side of the dummy structure 12 is connected to one end of each of the multiple rows of interconnected dummy structures 12, providing a horizontal heat dissipation path for the semiconductor structure located in this layer. When combined with the interconnection of the multi-layer second connection structure, the semiconductor structure can also obtain a vertical heat dissipation path at the same time, which can effectively improve the heat dissipation effect of the multi-layer semiconductor structure.

[0077] Meanwhile, in this embodiment, since there are multiple first sealing rings in the region far from the first sealing ring 111 connected to the dummy structure 12, the stress in the semiconductor structure during the fabrication process or other processes can be effectively reduced. In this embodiment, although there is a case where the first sealing ring 111 is connected to the end of the row, the semiconductor structure will not experience stress concentration during the fabrication process. In other words, this embodiment increases the heat dissipation effect without causing a decrease in the performance of the semiconductor structure.

[0078] Here, the first direction and the second direction intersect and are perpendicular to each other. One end of the dummy knot 12, which is located in the same row and connected to each other, can be directly connected to the first sealing ring 111.

[0079] Although Figure 1 The diagram shows a case where the first sealing ring 111 contains three rings, but it is not limited to this. The first sealing ring 111 can also be any other suitable number, such as two, five, ten, a dozen or even more rings. There are no specific restrictions here, and the choice can be made flexibly according to the actual situation.

[0080] In some embodiments, the arrangement direction of the virtual structures 12 in the same row and the arrangement direction of the virtual structures 12 in the same column may have a certain angle with the first direction and the second direction, respectively. The specific angle can be flexibly selected according to the actual situation (e.g., process requirements).

[0081] In this embodiment, at least some dummy structures in some rows of each layer are interconnected via a first connecting structure in a plane parallel to the pattern of each layer. This provides a heat dissipation path in the semiconductor structure parallel to the pattern of each layer. Simultaneously, in this embodiment, connecting one end of the interconnected dummy structures in the same row to a sealing ring provides favorable conditions for the semiconductor structure to form a heat dissipation path parallel to the pattern of each layer. Furthermore, a second connecting structure 14 connects the sealing rings 11 in different layers, further providing the semiconductor structure with a vertical heat dissipation path. In other words, in this embodiment, the multi-layered stacked wafer or chipset structure has the ability to dissipate heat in multiple directions, which helps the semiconductor structure obtained after the dicing process to achieve better heat dissipation even with a large number of stacked layers, thereby improving the performance and stability of these semiconductor structures.

[0082] In other embodiments, such as Figure 2 and Figure 3 As shown, the sealing ring 11 includes: multiple layers of first sealing rings 111 and multiple layers of discontinuously distributed heat dissipation structures 112. The heat dissipation structures 112 are located between the first sealing rings 111 and the dummy structures 12, and are not connected to the first sealing rings 111. The first connecting structure 13 connects one end of the interconnected dummy structures 12 to the heat dissipation structures 112, and the second connecting structure 12 connects the heat dissipation structures 112 located in different layers to each other.

[0083] In some embodiments, in addition to the first connection structure 13 connecting one end of the interconnected dummy structure 12 to the heat dissipation structure 112, it can also connect the dummy structure 12 located at the end and adjacent to the heat dissipation structure 112 to the heat dissipation structure 112. Specifically, it can be selected or determined according to the actual layout, and no specific limitation is made here.

[0084] In some embodiments, the heat dissipation structure 112 on each layer may have multiple segments, and any one of the multiple segments of the heat dissipation structure 112 is not connected to the first sealing ring 111, nor are the multiple first sealing rings 111 connected to each other.

[0085] Compared with the previous embodiment, this embodiment not only achieves the effects of the previous embodiment, but also adds a discontinuously distributed heat dissipation structure 112. In this embodiment, the heat dissipation structure 112 not only performs the purpose of heat dissipation, but also helps to prevent the cutting stress generated during the semiconductor structure cutting process from being conducted over a large range because no section of the heat dissipation structure 112 is connected to the first sealing ring 111. This helps to disperse and absorb stress, and further prevents defects such as cracks and fissures from occurring during the cutting process.

[0086] like Figure 2 and Figure 3 As shown, in some embodiments, the heat dissipation structure 112 may be located on one or both sides of the first sealing ring 111.

[0087] When the heat dissipation structure 112 can be located on both sides of the first sealing ring 111, the array structure composed of the dummy structure 12 can also be located on both sides of the first sealing ring 111. At this time, the semiconductor structure can have better heat dissipation effects in the plane direction and vertical direction parallel to the pattern of each layer.

[0088] In some embodiments, the number of layers of the first sealing ring 111 can be the same as the number of layers of the heat dissipation structure 112.

[0089] In some embodiments, the ratio of the size of the heat dissipation structure 112 to the size of the dummy structure 12 in the extending direction of the heat dissipation structure 112 is between 2.5 and 4.5 (including the endpoint values), for example, 2.8, 3.0, 3.2, 3.4, 3.6, 3.8, 4.0, 4.2, 4.4, etc.

[0090] Continue to refer to Figures 1 to 6 In some embodiments, one end of multiple interconnected dummy structures 12 is connected to the same heat dissipation structure 112.

[0091] In some embodiments, the number of interconnected dummy structures 12 connected to the same heat dissipation structure 112 can be two. However, this is not the case; in some other embodiments, the number of interconnected dummy structures 12 connected to the same heat dissipation structure 112 can be greater than two. Specifically, it can be determined according to the actual situation, and no specific limitation is made here.

[0092] Understandably, when the number is 2, the semiconductor structure can achieve a better cutting stress dispersion effect, and the final semiconductor structure can also have a better heat dissipation effect.

[0093] In some embodiments, the row containing multiple interconnected dummy structures 12 connected to the same heat dissipation structure 112 can include various cases:

[0094] In some embodiments, multiple interconnected virtual structures 12 are located in adjacent behaviors (see details). Figure 6 ).

[0095] In other embodiments, the behavior intervals of multiple interconnected dummy structures 12 are set (see details). Figures 1 to 4 ).

[0096] In some other embodiments, the behavior of multiple interconnected dummy structures 12 includes both intermittent and continuous settings (see details). Figure 5 ).

[0097] Continue to refer to Figures 1 to 6 In any of the above embodiments, each dummy structure 12 in the same row is interconnected by the first connection structure 13, or some dummy structures 12 in the same row are interconnected by the first connection structure 13.

[0098] It should be noted that, in any of the above embodiments, the arrangement of the virtual structures 12, the interrelationship between the rows where the virtual structures 12 are connected, and the degree to which the virtual structures 12 in the same row participate in the connection are also applicable to the situation where the above settings can be made in different positions on the same layer. The specific settings can be flexibly selected according to the actual situation, and no specific limitations are made here.

[0099] However, this is not the only limitation. In any of the above embodiments, the interrelationship between rows where the interconnected virtual structures 12 are located and the degree to which the virtual structures 12 in the same row participate in the connection are also applicable to the setting in different layers. The specific choice can be made flexibly according to the actual situation, and no specific limitation is made here.

[0100] In some embodiments, the arrangement, connection relationship, and setting at different positions of the first sealing ring 111 and heat dissipation structure 12 located in different layers and the dummy structure can be the same or different. The specific selection can be made flexibly according to the actual situation, and no specific limitation is made here.

[0101] In some embodiments, the semiconductor structure further includes a third connection structure 15 that connects at least a portion of the first connection structure 13 between dummy structures 12 located on the same layer but in different rows.

[0102] In this embodiment, it helps to increase the uniformity of heat dissipation, so that areas with more heat generation and areas with less heat generation can conduct heat, which helps the heat dissipation effect of structures in the same layer or even different layers.

[0103] Understandably, the number of first and third connection structures in the same region should not be too high or too low. Too many structures can lead to a much higher structure density in that region compared to other regions, which can negatively impact the performance of the semiconductor structure and the fabrication process. Too few structures result in a smaller proportion of virtual structures that provide connectivity, limiting the improvement in heat dissipation. In practice, the specific number should be determined based on the actual region size and the arrangement of virtual structures; no specific limitations are set here.

[0104] In some embodiments, the dummy structure 12, the first connection structure 13, and the third connection structure 15 can be formed in the same process step, which helps to increase the heat dissipation performance of the semiconductor structure without increasing the number of process steps, thus improving the performance of the semiconductor structure while also having high production efficiency.

[0105] In some embodiments, the material of the sealing ring may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon, or any combination thereof. The materials of the dummy structure 12, the first connecting structure 13, the second connecting structure 14, and the third connecting structure 15 may be the same as or different from the material of the sealing ring, for example, they may be tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc.

[0106] In some specific embodiments, the materials of the dummy structure 12, the first connecting structure 13, the second connecting structure 14, and the third connecting structure 15 can all be copper.

[0107] Understandably, the thermal conductivity of oxides is around 1.1 W / (m·K), that of SiN is around 0.24 W / (m·K), and that of Cu is around 401 W / (m·K). In semiconductor structures, because the thermal conductivity of Cu is much greater than that of oxides and SiN, the semiconductor structure provided in this disclosure allows heat to be conducted along the Cu trace path parallel to the plane of the pattern in each layer, and simultaneously, when flowing through vias, it can be conducted vertically. This disclosure, through the design of relevant structures and interconnections in the chip's back-end processing, effectively improves the thermal conductivity of the chip in both the plane and vertical directions parallel to the pattern in each layer.

[0108] In some embodiments, the projections of the heat dissipation structures 112 located in different layers onto the thickness direction of the dummy structure 12 at least partially overlap.

[0109] Figure 8 Figure (1) shows the route along Figure 1The detailed cross-sectional view in the A1-A2 direction shows the case where the multi-layered first sealing rings 111 distributed along the third direction are connected in the vertical direction by the second connecting structure 14. Figure 8 Figure (2) shows the route along Figure 2 The detailed cross-sectional view along the B1-B2 direction shows the multi-layer heat dissipation structures 112 distributed along the third direction, connected vertically by the second connecting structure 14. The third direction is perpendicular to the first and second directions. When the interconnected dummy structures 12 are directly connected to the first sealing ring 111, the semiconductor structure achieves heat dissipation in the vertical direction through the connections between the multiple layers of the first sealing rings 111. When the interconnected dummy structures 12 are connected to the heat dissipation structure 112, the semiconductor structure achieves heat dissipation in the vertical direction through the connections between the multiple layers of the heat dissipation structures 112.

[0110] It should be noted that, in order to clearly illustrate the structures included in each of the accompanying drawings and the connections between them, the accompanying drawings... Figure 1-7 Some structures are omitted and not shown. For example, an isolation layer is provided between the dummy structures, between the first sealing rings, and between the heat dissipation structures. The material can be at least one or a combination of silicon oxide, silicon nitride, or silicon oxynitride.

[0111] This disclosure also provides a method for fabricating a semiconductor structure, such as... Figure 9 As shown, the preparation method includes the following steps:

[0112] Step S101: Form a multi-layer sealing ring and a multi-layer dummy structure. Each layer contains multiple dummy structures, which are arranged in an array. The array contains multiple rows, and each dummy structure includes at least one part located on at least one side of the sealing ring.

[0113] Step S102: Form a multi-layer first connection structure, in which the first connection structure and the dummy structure are arranged alternately in at least a portion of the rows of each layer, and at least a portion of the dummy structures located in the same row are connected to each other; at the same time, the first connection structure also connects one end of the interconnected dummy structures to the sealing ring.

[0114] Step S103: Form a multi-layered second connection structure, which connects the sealing rings located in different layers to each other.

[0115] In some embodiments, forming a multilayer sealing ring includes:

[0116] A multi-layered first sealing ring and a multi-layered discontinuously distributed heat dissipation structure are formed. The heat dissipation structure is located between the first sealing ring and the dummy structure, and there is no connection between the heat dissipation structure and the first sealing ring. The first connecting structure connects one end of the dummy structure to the heat dissipation structure, and the second connecting structure connects the heat dissipation structures located in different layers to each other.

[0117] In some embodiments, the preparation method further includes:

[0118] A third connection structure is formed, which connects at least a portion of the first connection structures between dummy structures located on the same level but in different rows.

[0119] It should be understood that, although Figure 9 The steps are shown sequentially as indicated by the arrows, but they are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 9 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0120] Figures 10 to 12 A process flow diagram of the method for fabricating a semiconductor structure provided in this disclosure embodiment; Figure 13 The semiconductor structure provided in the embodiments of this disclosure is fabricated along the following process: Figure 11 Detailed sectional view along the B1-B2 direction; Figure 14 The semiconductor structure provided in the embodiments of this disclosure is fabricated along the following process: Figure 11 Detailed sectional views in the A1-A2 and B1-B2 directions; Figure 15 The semiconductor structure provided in the embodiments of this disclosure is fabricated along the following process: Figure 12 Detailed sectional views in the A1-A2 and B1-B2 directions.

[0121] The preparation method provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0122] To clearly describe the fabrication method provided in the embodiments of this disclosure, the fabrication process of the semiconductor structure is illustrated below using a single-layer wafer or chipset as an example. The fabrication process of other layers can be obtained by referring to the following method.

[0123] First, such as Figure 10As shown, an isolation layer L is provided, which may be located on a substrate, the substrate including a device region and a peripheral region.

[0124] In some embodiments, the substrate may be a silicon substrate, or may include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0125] Next, as Figure 11 , Figure 13 and Figure 14 As shown, an etching process is performed on the isolation layer L to remove part of the isolation layer, in order to obtain multiple structures in the isolation layer L, wherein:

[0126] Figure 13 The semiconductor structure provided in the embodiments of this disclosure is fabricated along the following process: Figure 11 A detailed cross-sectional view in the B1-B2 direction; in this step, on the opposite side of the isolation layer L used to form the subsequent sealing ring 11, the second connection structure 14 is pre-formed by first forming the third groove T3 and then filling it with material.

[0127] Figure 14 Figure (1) shows the route along Figure 11 (2) The figure shows a detailed sectional view along the A1-A2 direction; Figure 13 After the steps, along Figure 11 A detailed cross-sectional view along the B1-B2 direction; here, by performing an etching process on the isolation layer L to remove part of the isolation layer, a first trench T1, a second trench T2 located above the third trench T3 and exposing the second connection structure 14, a first groove P1, a second groove P2, and a third groove P3 (see [reference to first groove P1, second groove P2, and third groove P3]) are obtained in the isolation layer L. Figure 11 ); wherein, the first trench T1 is used to form the following appendix Figure 12 The first sealing ring 111 shown is a non-continuously distributed structure for forming the following appendix. Figure 12 The heat dissipation structure 112 shown has a first groove P1, a second groove P2, and a third groove P3, which are respectively used to form the heat dissipation structure as shown in the appendix. Figure 12 The virtual structure 12, the first connection structure 13, and the third connection structure 15 are shown.

[0128] In some embodiments, the processes of obtaining the first groove T1, the second groove T2 located above the third groove T3, the first recess P1, the second recess P2 and the third recess P3 can be formed in the same process step.

[0129] Then, in Figure 11 and Figure 14 Based on the structure shown, a filling process is performed to fill the first groove T1, the second groove T2, the first recess P1, the second recess P2, and the third recess P3 with filling material to obtain the desired results. Figure 12 and Figure 15 The diagram shows the first sealing ring 111, the heat dissipation structure 112, the dummy structure 12, the first connecting structure 13, and the third connecting structure 15. Among them, Figure 15 Figure (1) shows the route along Figure 12 Detailed sectional view along the A1-A2 direction, Figure 15 Figure (2) shows the route along Figure 12 Detailed sectional view along the B1-B2 direction.

[0130] Thus, a single-layer semiconductor structure has been obtained, including a sealing ring 11, a dummy structure 12, and multiple connection structures. By vertically stacking or bonding multiple single-layer structures, a semiconductor structure containing at least multiple sealing rings and multiple dummy structures, multiple first connection structures, multiple second connection structures, and multiple third connection structures can be obtained. For example, a semiconductor structure such as... Figures 1 to 3 The structure shown.

[0131] In some embodiments, the arrangement of the dummy structures 12 in each layer, their interconnections, the configuration of the first sealing ring 111, the heat dissipation structure 112, and their vertical connections can all refer to the content provided in any of the above embodiments.

[0132] It should be noted that the semiconductor device and its fabrication method provided in this disclosure can be applied to any semiconductor structure that requires the dispersion of cutting stress and improvement of heat dissipation, and are not limited in any way here. The embodiments of the semiconductor structure fabrication method provided in this disclosure and the embodiments of the semiconductor structure belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0133] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: A multi-layer sealing ring, comprising multiple first sealing rings and multiple discontinuously distributed heat dissipation structures, wherein there are multiple first sealing rings, and the heat dissipation structures are located between the first sealing rings and the dummy structures, and the heat dissipation structures are not connected to the first sealing rings. The multi-layered dummy structure includes multiple dummy structures in each layer, which are arranged in an array containing multiple rows. Each dummy structure includes at least one portion located on at least one side of the sealing ring. In a multi-layered first connection structure, in at least a portion of the rows of each layer, the first connection structure and the dummy structure are arranged alternately, and at least a portion of the dummy structures located in the same row are interconnected; at the same time, the first connection structure also connects one end of the interconnected dummy structure to the heat dissipation structure, and multiple first sealing rings exist in the area away from the area connected to the dummy structure. A multi-layer second connection structure, wherein the heat dissipation structures located on different layers are interconnected.

2. The semiconductor structure according to claim 1, characterized in that, In the extending direction of the heat dissipation structure, the ratio of the size of the heat dissipation structure to the size of the dummy structure ranges from 2.5 to 4.

5.

3. The semiconductor structure according to claim 1, characterized in that, One end of each of the multiple interconnected dummy structures is connected to the same section of the heat dissipation structure.

4. The semiconductor structure according to any one of claims 1-3, characterized in that, Each of the virtual structures in the same row is interconnected through the first connection structure, or some of the virtual structures in the same row are interconnected through the first connection structure.

5. The semiconductor structure according to any one of claims 2, characterized in that, The projections of the heat dissipation structures located in different layers in the thickness direction of the dummy structure at least partially overlap.

6. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure further includes a third connection structure that connects at least a portion of the first connection structure between the dummy structures located on the same layer but in different rows.

7. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A multi-layer sealing ring and a multi-layer dummy structure are formed. The multi-layer sealing ring includes multiple first sealing rings and multiple discontinuously distributed heat dissipation structures. There are multiple first sealing rings. The heat dissipation structures are located between the first sealing rings and the dummy structures, and the heat dissipation structures are not connected to the first sealing rings. There are multiple dummy structures in each layer. The multiple dummy structures are arranged in an array. The array contains multiple rows. The multiple dummy structures include at least a portion located on at least one side of the sealing ring. A multi-layered first connection structure is formed, in which the first connection structure and the dummy structure are alternately arranged in at least a portion of the rows of each layer, and at least a portion of the dummy structures located in the same row are interconnected; at the same time, the first connection structure also connects one end of the interconnected dummy structure to the heat dissipation structure, and multiple first sealing rings exist in the area away from the area connected to the dummy structure. A multi-layered second connection structure is formed, which connects the heat dissipation structures located on different layers to each other.

8. The preparation method according to claim 7, characterized in that, The preparation method further includes: A third connection structure is formed, which interconnects at least a portion of the first connection structures between the virtual structures located on the same layer but in different rows.

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