Semiconductor structure

Abstract

The present application discloses a semiconductor structure, including: a substrate; a U-shaped channel formed on the substrate, having two parallel channels and a connecting channel located at one end of the parallel channels and connecting the two parallel channels; a source electrode and a drain electrode, respectively located at the two ends of the opening side of the U-shaped channel; and a gate electrode, located above the U-shaped channel and spanning the two parallel channels of the U-shaped channel. By forming a U-shaped channel on the substrate, the gate electrode spanning the two parallel channels of the U-shaped channel can realize a simultaneous secondary control channel, which increases the gate control capability and can also effectively reduce the leakage current.

Description

Technical Field

[0001] The present invention relates generally to the field of semiconductors. More specifically, the present invention relates to a semiconductor structure, especially a field effect transistor structure. Background Art

[0002] Figure 1 The figure shows the current mainstream planar MOSFET (metal-oxide-semiconductor field effect transistor) structure. As shown in the figure, the gate 110, drain 120 and source 130 of the N-channel lateral conductive double diffused field effect transistor are all on the upper surface of the silicon wafer, and the lower part is the substrate 140. The gate 110 is an electrode that controls the switch of the transistor, usually made of polysilicon 101 and covered with a thin layer of silicon oxide as an insulating layer. The gate oxide layer 102 prevents the gate current from flowing directly into the channel, while allowing the gate voltage to control the channel 150 through the electric field. The channel 150 is a conductive area connecting the source 130 and the drain 120, and its formation depends on the gate voltage. The source 130 and the drain 120 are the two main current terminals of the transistor, and are usually formed into low resistance areas by heavy doping. When the transistor is turned on, the current flows from the source to the drain through the channel 150.

[0003] In semiconductor device design, heavy doping and reducing the thickness of the gate oxide are two common technical means for improving device performance. However, the application of these technologies may also bring some side effects, such as leakage current effects and weakened gate control capabilities, which in turn limit the continuous miniaturization of devices. For example, heavy doping is often used in the source and drain regions to reduce their resistance. At high doping levels, the distance between the source and drain is shortened, increasing the possibility of direct tunneling, thereby increasing leakage current. The high electric field in the heavily doped region may cause hot carrier injection into the gate oxide layer, increasing the gate current, which is also a leakage current. For another example, when the gate oxide layer becomes thinner, the electric field strength increases, increasing the probability of electron tunneling through the gate oxide layer, resulting in an increase in gate leakage current. The thinning of the gate oxide layer will also reduce the gate's ability to control the channel because the gate voltage has a weakened effect on the channel charge, which may lead to a lower threshold voltage and a decrease in device performance. The corresponding changes may also cause narrow channel effects (NCE) and short channel effects (SCE).

[0004] In view of this, there is an urgent need to provide a semiconductor structure, especially a field effect transistor solution, which can reduce leakage current while improving gate control capability, thereby achieving the purpose of improving integration to a certain extent. Summary of the invention

[0005] In order to at least solve one or more of the above-mentioned technical problems, the present application proposes a semiconductor structure.

[0006] In a first aspect, the present application provides a semiconductor structure, comprising: a substrate; a U-shaped channel formed on the substrate, having two parallel channels and a connecting channel located at one end of the parallel channels and connecting the two parallel channels; a source and a drain, respectively located at two ends of an opening side of the U-shaped channel; and a gate, located above the U-shaped channel and spanning the two parallel channels of the U-shaped channel.

[0007] In some embodiments, the closed end of the U-shaped channel is doped with ions to adjust the equivalent resistance of the U-shaped channel to meet different requirements.

[0008] In some embodiments, the closed end of the U-shaped channel is covered with a self-aligned silicide barrier layer to increase the equivalent resistance of the U-shaped channel so as to be used in a high voltage (HV) device.

[0009] In some embodiments, the lateral position of the gate along the channel direction of the U-shaped channel does not exceed two ends of the inner groove of the U-shaped channel.

[0010] In some embodiments, the semiconductor structure further includes a gate insulating layer located in a region between the gate and the U-shaped channel and covered by the gate.

[0011] In some embodiments, the gate insulating layer is a high-k dielectric film, and the gate is a metal gate.

[0012] In some embodiments, the gate insulating layer is a silicon oxide dielectric film, and the gate is polysilicon.

[0013] In some embodiments, the semiconductor structure further includes an insulating layer located between the gate and the U-shaped channel, filling between and outside the two parallel channels of the U-shaped channel. In some embodiments, the semiconductor structure further includes a plurality of U-shaped channels formed on the substrate and distributed in parallel, and the gate is located above the U-shaped channel and spans across the parallel channels of the plurality of U-shaped channels. In some embodiments, the U-shaped channel protrudes on the substrate to form a fin structure, and the gate spans and wraps the sidewalls and top of the two parallel channels of the U-shaped channel.

[0014] The unexpected beneficial technical effect of the present application is: according to the semiconductor structure provided above, by forming a U-shaped channel on the substrate, the gate crosses the two parallel channels of the U-shaped channel to realize the simultaneous secondary control channel. This secondary control increases the gate control capability and can also effectively reduce the leakage current. Further, compared with the traditional design, while maintaining the original channel length, the occupied length of this U-shaped channel design along the channel direction can be reduced to half of the previous one. That is, this nearly square MOS design is more compact than the long strip design and can be more flexibly embedded in other structures. In some embodiments, the equivalent resistance part of the channel can select doping ions to adjust the channel equivalent resistance to match different requirements; or it can cover a self-aligned silicide barrier (SAB) to increase the channel equivalent resistance, so that it can be applied to high-voltage devices. In some embodiments, this design can be well utilized in designs that require repeated structures, for example, it can be easily extended to occasions where multiple field effect transistors need to be connected in parallel. In addition, this design can also be easily applied to fin field effect transistors (FinFETs). BRIEF DESCRIPTION OF THE DRAWINGS

[0015] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present application will become easy to understand. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0016] Figure 1 The current mainstream planar MOSFET structure is shown;

[0017] Figure 2 A top view of a semiconductor structure according to some embodiments of the present application is shown;

[0018] Figure 3 A cross-sectional view of a semiconductor structure along a dotted line AA according to some embodiments of the present application is shown;

[0019] Figure 4 A cross-sectional view of a semiconductor structure along a dotted line BB according to some embodiments of the present application is shown;

[0020] Figure 5 shows a top view of a semiconductor structure according to some other embodiments of the present application;

[0021] Figure 6 Schematic diagrams showing semiconductor structures according to some further embodiments of the present application;

[0022] Figure 7 A process flow chart for preparing a semiconductor structure according to some embodiments of the present application is shown. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0024] It should be understood that the terms "include" and "comprising" used in the specification and claims of the present application indicate the presence of described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0025] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in this application specification and claims, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to include plural forms. It should also be further understood that the term "and / or" used in this application specification and claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0026] It should also be understood that, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," "on," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. When an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0027] The specific implementation of the present application is described in detail below with reference to the accompanying drawings.

[0028] Figure 2-Figure 4 A schematic diagram of a semiconductor structure 200 according to some embodiments of the present application is shown, wherein Figure 2 is a top view, Figure 3 is a cross-sectional view along the dotted line AA, Figure 4 It is a cross-sectional view along the dotted line BB.

[0029] As shown, the semiconductor structure 200 includes a substrate 210. The substrate 210 may be a silicon substrate, a silicon germanium substrate, a III-V group element compound substrate, or other semiconductor material substrates known to those skilled in the art. In some embodiments, the substrate 210 may be a lightly doped silicon substrate, and the doping type of the substrate determines the type of the transistor, such as N-type or P-type, and the embodiments of the present application are not limited in this regard.

[0030] A U-shaped channel 220 is formed on the substrate 210. Figure 2 It can be seen from the top view that the U-shaped channel 220 has two parallel channels and a connecting channel located at one end of the parallel channels and connecting the two parallel channels.

[0031] The source 230 and the drain 240 are respectively located at the two ends of the opening side of the U-shaped channel 220. The source 230 and the drain 240 can be formed by doping ions into the two end regions of the U-shaped channel. For example, on a p-type substrate, two n+ regions, namely the source region and the drain region, are formed by ion implantation or diffusion process.

[0032] The gate 250 is located above the U-shaped channel 220 and spans across two parallel channels of the U-shaped channel. Figure 2 As shown, the gate 250 can be a rectangular layer covering the U-shaped channel 220. The lateral position of the gate 250 along the channel direction of the U-shaped channel (the X direction in the figure) does not exceed the two ends of the internal groove of the U-shaped channel. The specific position can be selected according to the device requirements, for example, closer to the open side of the U-shaped channel, or closer to the closed side of the U-shaped channel, or located between the two. The width of the gate 250 in the X direction and / or the length in the Y direction can also be designed according to the needs of the actual device. Generally, the width of the gate 250 in the X direction does not exceed the length of the internal groove of the U-shaped channel. In some embodiments, the length of the gate 250 in the Y direction can at least cover the two parallel channels of the U-shaped channel.

[0033] A gate insulating layer is also included between the gate 250 and the U-shaped channel 220. Figure 4 As shown in the cross-sectional view of , the gate insulating layer 260 is located in the area between the gate 250 and the U-shaped channel 220 covered by the gate 250 , that is, the area where the gate contacts the two parallel channels of the U-shaped channel 220 .

[0034] The semiconductor structure 200 also includes an insulating layer. Figure 2-Figure 4 As shown, the insulating layer 270 is located between the gate 250 and the U-shaped channel 220, and fills between and outside the two parallel channels of the U-shaped channel 220. The insulating layer 270 may be an oxide, such as SiO2.

[0035] According to the semiconductor structure with a U-shaped channel provided above, since the gate spans across two parallel channels of the U-shaped channel, it is possible to achieve simultaneous secondary control of the channel. This secondary control increases the gate control capability and can also effectively reduce leakage current. Furthermore, compared to the traditional design, while maintaining the original channel length, the occupied length of this U-shaped channel design along the channel direction can be reduced to half of the previous one, for example, from L to L / 2. That is, this nearly square MOS design is more compact than the long strip design and can be more flexibly embedded in other structures.

[0036] In some embodiments, the gate insulating layer 260 may be a silicon oxide dielectric film, such as SiO 2 , and the gate 250 may be polysilicon.

[0037] In other embodiments, the gate insulating layer 260 may be a high-k dielectric film (HK), and the gate may be a metal gate (MG). HKMG can be used to increase the physical thickness of the gate insulating layer by increasing the dielectric constant of the gate insulating medium while maintaining the same gate capacitance per unit area to ensure the same control over the channel, thereby greatly reducing the direct tunneling current between the gate and the channel.

[0038] In some embodiments, the closed end of the U-shaped channel 220 (e.g., the area shown in the box 280 in the figure) can be doped with ions. The closed end is the equivalent resistance part of the channel, and the channel equivalent resistance can be adjusted to match different requirements by selecting the doping ions. For example, doping n-type impurities, such as phosphorus (P) or arsenic (As), in a p-type semiconductor can increase the concentration of free electrons. Since electrons generally have a higher mobility, this doping can reduce the equivalent resistance of the channel. For another example, doping p-type impurities, such as boron (B) or aluminum (Al), in an n-type semiconductor (such as silicon or germanium), can form holes, but the mobility of these holes is generally lower than that of electrons. Therefore, p-type doping reduces the electron concentration of the n-type semiconductor, thereby increasing the equivalent resistance of the channel.

[0039] Alternatively or additionally, in some other embodiments, the closed end of the U-shaped channel 220 may be covered with a self-aligned silicide blocking layer (SAB). The SAB layer is used to prevent the generation of silicide to obtain a diffusion region with a higher resistance value, which can be used to increase resistance and withstand voltage. By covering the SAB layer to increase the channel equivalent resistance, the semiconductor structure can be applied to high-voltage devices.

[0040] The U-shaped channel design of the present application can be well utilized in designs that require repeated structures, for example, it can be easily extended to situations that require multiple field effect transistors to be connected in parallel.

[0041] Figure 5 FIG. 5 shows a top view of a semiconductor structure 500 according to some other embodiments of the present application. As shown in the figure, in these embodiments, a plurality of U-shaped channels 220 distributed in parallel are formed on the substrate, and three U-shaped channels are shown in the figure as an example. The gate 250 is located above these U-shaped channels 220 and spans the parallel channels of these U-shaped channels. In these embodiments, the structure and properties of the U-shaped channels 220 are combined with the above Figure 2-Figure 4 The description is the same and will not be repeated here.

[0042] By extending the length of the gate 250 in the Y direction so that it spans across the parallel channels of multiple U-shaped channels, the gates of these U-shaped channels can be interconnected to share a gate control signal. The U-shaped channel design proposed in the present application can be easily applied to occasions where gates need to be connected in parallel, and its structure is simple, which facilitates the realization of device density.

[0043] Furthermore, the U-shaped channel design of the present application can also be conveniently applied to fin field effect transistors (FinFETs).

[0044] Figure 6 Schematic diagrams of semiconductor structures 600 according to other embodiments of the present application are shown. As shown in the figure, in these embodiments, the U-shaped channel 220 has a certain height, and the protrusion forms a fin structure on the substrate 210, and the horizontal cross-section of the fin structure is U-shaped. The gate 250 spans and wraps the sidewalls and top of the two parallel channels of the U-shaped channel 220. In these embodiments, the other structures and properties of the U-shaped channel 220 are combined with the above Figure 2-Figure 4 The description is the same and will not be repeated here.

[0045] The source 230 and the drain 240 are respectively located at the two ends of the opening side of the U-shaped channel 220. The insulating layer 270 is located between the gate 250 and the U-shaped channel 220, filling between and outside the two parallel channels of the U-shaped channel 220. However, in this embodiment, the height of the insulating layer 270 is lower than the height of the U-shaped channel. The gate insulating layer (not shown in the figure) is located between the gate 250 and the U-shaped channel 220 in the area covered by the gate 250, that is, the area where the gate contacts the two parallel channels of the U-shaped channel 220. In this embodiment, the gate insulating layer can be an "n" type thin layer covering the sidewalls and top of the parallel channels.

[0046] By applying the U-shaped channel of the present application to FinFET, the performance of FinFET can be further improved, the gate control capability can be increased, and the leakage current can be effectively reduced.

[0047] The semiconductor structure of the embodiment of the present application can be prepared in a variety of ways. Those skilled in the art can form it by using a suitable process based on the structure disclosed above without developing a new process. For example, when implemented as a planar MOS tube, the existing planar MOS tube preparation process can be used, including but not limited to furnace tube, thin film (TF), photolithography (PH), etching (ETCH), chemical-mechanical polishing (CMP), wet etching (WET), etc. More specifically, the formation of the U-shaped channel can adopt the traditional shallow trench isolation (STI) process, but the shape of the trench is different. For another example, when implemented as a FinFET, the existing FinFET process can be used, but the shape of the fin structure formed is different. For another example, when the gate insulation layer adopts a high-K material, the HKMG process can also be applied.

[0048] Figure 7 A process flow chart for preparing a semiconductor structure according to some embodiments of the present application is shown. In this embodiment, a planar silicon-gate nMOS transistor is used as an example to describe its preparation process. Those skilled in the art can also manufacture the semiconductor structure described in other embodiments of the present application based on existing processes.

[0049] like Figure 7 As shown, first, in step 701, a pad oxide layer and a hard mask layer are sequentially deposited on a substrate. For example, p-type silicon is selected as the substrate material, and then an isolation oxide layer is grown on the surface of the substrate to protect the active area from chemical contamination in subsequent processes. A hard mask layer, such as silicon nitride, is deposited on the pad oxide layer as a strong mask material, which helps to protect the active area and acts as a barrier material during CMP.

[0050] Then, in step 702, the hard mask layer, the pad oxide layer and the semiconductor substrate of a certain depth are sequentially etched by photolithography and etching processes to form a groove. In this step, it is noted that the shape of the etched groove corresponds to the shape of the previously combined Figure 2-Figure 4 Describes the area between the two parallel channels of a U-shaped channel.

[0051] Next, in step 703, an insulating material such as silicon oxide is deposited in the trench until the trench is filled with the insulating material, for example, using chemical vapor deposition (CVD) technology to fill the trench with CVD oxide.

[0052] Next, in step 704, excess oxide, hard mask layer and pad oxide layer are removed. For example, chemical mechanical polishing (CMP) is used to remove excess oxide to ensure a flat surface. After that, the hard mask layer and pad oxide layer are further removed. Thus, a U-shaped channel is formed on the substrate.

[0053] Next, in step 705, a gate is formed on the U-shaped channel by oxidation, photolithography, etching, deposition and other processes.

[0054] Finally, in step 706, a source and a drain are formed at both ends of the opening side of the U-shaped channel by ion implantation or diffusion process. The following process can be continued according to the conventional MOS tube process, and the description thereof is omitted here.

[0055] Therefore, an exemplary method for preparing the semiconductor structure of the embodiment of the present application is described above in conjunction with a specific manufacturing process flow. Those skilled in the art can understand that the semiconductor structure of the embodiment of the present application can also be prepared by using the process flow described above, and some of the processes can also be replaced by other processes, and the present application has no limitation in this regard.

[0056] It can be seen from the above description that the unexpected technical effect of the embodiment of the present invention is that by forming a U-shaped channel on the substrate, the gate crosses the two parallel channels of the U-shaped channel to realize the simultaneous secondary control channel. This secondary control increases the gate control capability and can also effectively reduce the leakage current. In this case, it is not necessary to reduce the size, such as reducing the thickness of the gate oxide layer to cause leakage, to achieve the purpose of improving performance. Further, compared with the traditional design, while maintaining the original channel length, the occupied length of this U-shaped channel design along the channel direction can be reduced to half of the previous one. That is, this nearly square MOS design is more compact than the long strip design and can be more flexibly embedded in other structures. In some embodiments, the equivalent resistance part of the channel can select doping ions to adjust the channel equivalent resistance to match different requirements; or it can cover the self-aligned silicide barrier (SAB) to increase the channel equivalent resistance, so that it can be applied to high-voltage devices. In some embodiments, this design can be well utilized in designs that require repeated structures, for example, it can be easily extended to occasions where multiple field effect transistors need to be connected in parallel. In addition, this design can also be easily applied to fin field effect transistors (FinFET).

[0057] Although multiple embodiments of the present application have been shown and described herein, it is obvious to those skilled in the art that such embodiments are provided only by way of example. Those skilled in the art can think of many changes, modifications and alternatives without departing from the thought and spirit of the present application. It should be understood that in the process of practicing the present application, various alternatives to the embodiments of the present application described herein can be adopted. The attached claims are intended to limit the scope of protection of the present application, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A U-shaped channel formed on the substrate, having two parallel channels and a connecting channel located at one end of the parallel channels and connecting the two parallel channels; A source electrode and a drain electrode, respectively located at two ends of the opening side of the U-shaped channel; as well as A gate is located above the U-shaped channel and spans across two parallel channels of the U-shaped channel, wherein the lateral position of the gate along the channel direction of the U-shaped channel does not exceed two ends of the inner groove of the U-shaped channel; in, The closed end of the U-shaped channel is doped with ions to adjust the equivalent resistance of the U-shaped channel; and The closed end of the U-shaped channel is covered with a salicide barrier layer.

2. The semiconductor structure according to claim 1, characterized in that: Also includes: A gate insulating layer is located in a region between the gate and the U-shaped channel and covered by the gate.

3. The semiconductor structure according to claim 2, characterized in that: The gate insulating layer is a high dielectric constant dielectric film, and the gate is a metal gate.

4. The semiconductor structure according to claim 2, characterized in that: The gate insulating layer is a silicon oxide dielectric film, and the gate is polysilicon.

5. The semiconductor structure according to claim 1, characterized in that: Also includes: The insulating layer is located between the gate and the U-shaped channel, and fills between and outside the two parallel channels of the U-shaped channel.

6. The semiconductor structure according to claim 1, wherein: Also includes: A plurality of U-shaped channels are formed on the substrate and distributed in parallel, and The gate is located above the U-shaped channel and spans across a plurality of parallel channels of the U-shaped channels.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The U-shaped channel protrusion forms a fin structure on the substrate, and The gate crosses and wraps the sidewalls and top of the two parallel channels of the U-shaped channel.

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