Power semiconductor device and method for manufacturing the same

Abstract

The present application relates to the field of semiconductor technology, and specifically to a power semiconductor device and a preparation method thereof, wherein the power semiconductor device comprises: a semiconductor material layer, comprising a first doped region and a drift region; a plurality of gate grooves extending from the upper surface through the first doped region to the drift region, and a gate is arranged in at least one gate groove; the first doped region comprises a first conductive type base region and a first conductive type controllable region; a second conductive type emitter region, located at the surface layer of the first conductive type base region; adjacently arranged first conductive type doped regions and second conductive type doped regions, located in the first conductive type controllable region and / or located on the first conductive type controllable region; the first conductive type doped region, the first conductive type base region and the second conductive type emitter region are connected to an emitter metal layer together, and the second conductive type doped region and the gate are connected to the gate metal layer together; in this way, EMI noise is reduced, and a large amount of carrier loss is avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power semiconductor device and a method for preparing the same. Background Art

[0002] As one of the most important power semiconductor devices in the semiconductor field, the Insulated Gate Bipolar Transistor (IGBT) has the advantages of high operating frequency and low on-state voltage drop. The IGBT structure with a P-type floating region significantly reduces the conduction loss through the high carrier injection enhancement effect. At the same time, the introduction of the P-type floating region also reduces the channel density, so that the device has a lower saturation current density, thus having better short-circuit capability. Therefore, the P-type floating region structure has become one of the conventional structures of current IGBT devices.

[0003] However, during the device startup phase, holes are injected from the back of the device, and holes continue to accumulate in the P-type floating region, which will cause the potential to rise, thereby generating a displacement current flowing from the P-type floating region to the gate. When the displacement current is greater than the gate current, the gate resistor Rg has poor control over the current change rate di / dt of the IGBT when the device is turned on, which ultimately causes more serious electromagnetic interference (EMI) noise problems in the system. The current change rate di / dt of the IGBT device when it is turned on with zero current is the main reason for excessive EMI noise in the system. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a power semiconductor device and a method for manufacturing the same in order to solve at least one problem existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a power semiconductor device, comprising: a semiconductor material layer, comprising an upper surface and a lower surface opposite to each other, the semiconductor material layer comprising a first doped region located on the upper surface side and a drift region located below the first doped region, the first doped region having a first conductivity type, and the drift region having a second conductivity type different from the first conductivity type; a plurality of gate trenches extending from the upper surface through the first doped region to the drift region, a gate being arranged in at least one of the gate trenches; wherein the first doped region comprises at least one first conductivity type base region and at least one first conductivity type controllable region separated by a plurality of the gate trenches; a second conductivity type emitter region, located on the surface layer of the first conductivity type base region; adjacently arranged first conductivity type doped regions and second conductivity type doped regions, located in and / or on the first conductivity type controllable region; wherein the first conductivity type doped region, the first conductivity type base region and the second conductivity type emitter region are commonly connected to an emitter metal layer, and the second conductivity type doped region and the gate are commonly connected to the gate metal layer.

[0006] In combination with the first aspect of the present application, in an optional implementation, the net doping concentration of the first conductive type ions in the first conductive type doping region is lower than the net doping concentration of the first conductive type ions in the first conductive type controllable region.

[0007] In combination with the first aspect of the present application, in an optional implementation manner, the second conductive type doping region is arranged around the first conductive type doping region.

[0008] In combination with the first aspect of the present application, in an optional implementation manner, the first conductivity type doping region and the second conductivity type doping region are adjacently arranged along a direction parallel to the upper surface.

[0009] In combination with the first aspect of the present application, in an optional implementation manner, the first conductivity type doping region and the second conductivity type doping region have the same size in a direction perpendicular to the upper surface.

[0010] In combination with the first aspect of the present application, in an optional embodiment, it also includes: a first contact hole, exposing the first conductive type doped region from the upper surface side and extending into the first conductive type doped region, the side wall of the first contact hole and the second conductive type doped region and the bottom of the first contact hole and the first conductive type controllable region are separated by the first conductive type doped region; a first conductive type contact region, at least located in the surface layer of the first conductive type doped region exposed by the bottom of the first contact hole, the first conductive type contact region having a higher first conductive type carrier concentration than the first conductive type doped region; a conductive plug, filling the first contact hole and conductively connected to the first conductive type contact region.

[0011] In combination with the first aspect of the present application, in an optional embodiment, the dimensions of the first conductive type doped region and the second conductive type doped region in a direction perpendicular to the upper surface are both greater than the dimension of the second conductive type emitter region in a direction perpendicular to the upper surface.

[0012] In combination with the first aspect of the present application, in an optional implementation manner, the second conductivity type doped region and the gate trench adjacent thereto are separated by the first conductivity type controllable region.

[0013] In combination with the first aspect of the present application, in an optional embodiment, it also includes a carrier storage region, which is located between the first doped region and the drift region; the first doped region also includes at least one first conductive type floating region, and the first conductive type floating regions and the first conductive type floating regions, the first conductive type base region and the first conductive type controllable region are separated by the gate trench; a dummy gate structure is arranged in at least one of the gate trenches; the carrier storage region is located on both sides of the gate trench in which the gate is arranged; the first doped region and the drift region are in direct contact below the first conductive type floating region, below the first conductive type doped region, and at the side wall of the gate trench in which the dummy gate structure is arranged.

[0014] In a second aspect, an embodiment of the present application provides a method for preparing a power semiconductor device, the method comprising: providing a semiconductor material layer having a second conductivity type, the semiconductor material layer comprising an upper surface and a lower surface opposite to each other; forming a plurality of gate grooves extending from the upper surface of the semiconductor material layer to the interior of the semiconductor material layer, at least one of the gate grooves being used to set a gate; doping the semiconductor material layer to form a first doped region having a first conductivity type on the upper surface side of the semiconductor material layer, a portion of the semiconductor material layer located below the first doped region forming a drift region, the first conductivity type being different from the second conductivity type; wherein the first doped region comprises a first doped region having a first conductivity type and a second conductivity type being different from each other; wherein the first doped region comprises a first doped region having a first conductivity type and a second conductivity type being different from each other; wherein the first doped region comprises a first doped region having a first conductivity type and a second conductivity type being different from each other; wherein the first doped region comprises a first doped region having a first conductivity type and a second conductivity type being different from each other; wherein the first doped region comprises a first doped region having a first conductivity type and a second conductivity type being different from each other; wherein the first doped region comprises a first doped region having a first conductivity type and a second conductivity type being different from each other; wherein the first doped region comprises a first doped region having a first conductivity type and a second conductivity type being different from each other; wherein the first doped region comprises a first doped region having a first conductivity type and a first ... At least one first conductive type base region and at least one first conductive type controllable region separated by a plurality of gate grooves; a second conductive type emitter region is formed on the surface layer of the first conductive type base region, and a first conductive type doped region and a second conductive type doped region are formed in and / or on the first conductive type controllable region, and the first conductive type doped region and the second conductive type doped region are arranged adjacent to each other; an emitter metal layer and a gate metal layer are formed, the emitter metal layer is conductively connected to the first conductive type doped region, the first conductive type base region and the second conductive type emitter region, and the gate metal layer is conductively connected to the second conductive type doped region and the gate.

[0015] In combination with the second aspect of the present application, in an optional embodiment, a second conductive type emitter region is formed on the surface layer of the first conductive type base region, and a second conductive type doped region is formed in the first conductive type controllable region, including: firstly performing second conductive type ion doping and annealing on the area in the first conductive type controllable region where the second conductive type doped region is to be formed, and then performing second conductive type ion doping and annealing on the area in the surface layer of the first conductive type base region where the second conductive type emitter region is to be formed.

[0016] In combination with the second aspect of the present application, in an optional embodiment, a first conductive type doped region is formed in the first conductive type controllable region, including: doping the area in the first conductive type controllable region where the first conductive type doped region is to be formed with second conductive type ions to reduce the net doping concentration of the first conductive type ions, thereby forming the first conductive type doped region in which the net doping concentration of the first conductive type ions is lower than the net doping concentration of the first conductive type ions in the first conductive type controllable region.

[0017] In combination with the second aspect of the present application, in an optional implementation manner, the second conductive type doping region is arranged around the first conductive type doping region.

[0018] In combination with the second aspect of the present application, in an optional implementation manner, the first conductivity type doping region and the second conductivity type doping region are adjacently arranged along a direction parallel to the upper surface.

[0019] In combination with the second aspect of the present application, in an optional implementation manner, the first conductivity type doping region and the second conductivity type doping region have the same size in a direction perpendicular to the upper surface.

[0020] In combination with the second aspect of the present application, in an optional embodiment, before forming the emitter metal layer and the gate metal layer, the method also includes: forming a first contact hole, the first contact hole exposing the first conductive type doped region from the upper surface side and extending into the first conductive type doped region, the side wall of the first contact hole and the second conductive type doped region and the bottom of the first contact hole and the first conductive type controllable region are separated by the first conductive type doped region; performing first conductive type ion doping on the surface layer of the first conductive type doped region exposed by the bottom of the first contact hole to form a first conductive type contact region; filling the first contact hole with a conductive material to form a conductive plug, and the conductive plug is conductively connected to the first conductive type contact region.

[0021] In combination with the second aspect of the present application, in an optional embodiment, the dimensions of the first conductive type doped region and the second conductive type doped region in a direction perpendicular to the upper surface are both greater than the dimension of the second conductive type emitter region in a direction perpendicular to the upper surface.

[0022] In combination with the second aspect of the present application, in an optional implementation manner, the second conductivity type doped region and the gate trench adjacent thereto are separated by the first conductivity type controllable region.

[0023] In combination with the second aspect of the present application, in an optional embodiment, before forming a first doped region with a first conductivity type on the upper surface side of the semiconductor material layer, the method also includes forming a carrier storage region; the first doped region is located above the carrier storage region; the first doped region also includes at least one first conductivity type floating region, and each of the first conductivity type floating regions and the first conductivity type floating region, the first conductivity type base region and the first conductivity type controllable region are separated by the gate trench; at least one of the gate trenches is used to set a dummy gate structure; the carrier storage region is located on both sides of a gate trench in which a gate is set; below the first conductivity type floating region, below the first conductivity type doped region, and at the side wall of the gate trench in which a dummy gate structure is set, the first doped region and the drift region are in direct contact.

[0024] The power semiconductor device and the preparation method thereof provided in the embodiment of the present application are provided by setting a first conductive type controllable region, and the adjacently arranged first conductive type doped region and the second conductive type doped region are provided in the first conductive type controllable region and / or located on the first conductive type controllable region; wherein the first conductive type doped region and the first conductive type base region and the second conductive type emitter region are commonly connected to the emitter metal layer, and the second conductive type doped region and the gate are commonly connected to the gate metal layer; thus, on the one hand, at the initial stage of device startup, the first conductive type carriers gradually enter the first doped region, and since the first conductive type doped region is provided in the first conductive type controllable region, and the first conductive type doped region is connected to the emitter metal layer, the first conductive type doped region can directly extract the first conductive type carriers in the first conductive type controllable region into the emitter metal layer, and at the same time clamp the potential of the first conductive type controllable region to a low potential, suppress the displacement current, and reduce the current change rate di / dt when the zero current is turned on, thereby reducing E MI noise; since the gate reaches the turn-on voltage but is still at a relatively low potential, the second conductive type doping region with the same potential as the gate is also at a relatively low potential, and the second conductive type doping region will not affect the extraction of the first conductive type carrier by the first conductive type doping region; the first conductive type carrier passes through the drift region from the back of the device into the first conductive type controllable region, and is then extracted from the first conductive type controllable region to the emitter metal layer via the first conductive type doping region. It can be seen that the embodiment of the present application increases the extraction path of the first conductive type carrier, alleviates the problem of accumulation of the first conductive type carrier in the first doping region, enhances gate control, and thus reduces EMI noise; on the other hand, in the later stage of device turn-on, the gate reaches a relatively high potential, and the second conductive type doping region with the same potential as the gate is also at a relatively high potential, so that the second conductive type doping region and the first conductive type doping region are completely exhausted, and the increased extraction path is completely cut off, thereby avoiding a large amount of carrier loss, ensuring the carrier concentration on the emitter side of the device, and enhancing the conductivity modulation effect.

[0025] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0027] Figure 1 A schematic cross-sectional structure diagram of a power semiconductor device provided in an embodiment of the present application;

[0028] Figure 2is a schematic diagram of a cross-sectional structure of a power semiconductor device in a ratio;

[0029] Figure 3 A comparison diagram of simulation results of the power semiconductor device in the embodiment and the power semiconductor device in the comparative example;

[0030] Figure 4 A schematic diagram of a process for preparing a power semiconductor device provided in an embodiment of the present application;

[0031] Figures 5 to 10 A schematic diagram of the cross-sectional structure of a power semiconductor device during the preparation process provided in an embodiment of the present application;

[0032] Fig.11 A schematic cross-sectional structure diagram of a power semiconductor device provided in another embodiment of the present application.

[0033] Description of reference numerals:

[0034] 110, semiconductor material layer; 1101, upper surface; 1102, lower surface; 111, second conductivity type doping region; 112, first conductivity type doping region; 113, second conductivity type emitter region; 114, first doping region; 1141, first conductivity type base region; 1142, first conductivity type controllable region; 1143, first conductivity type floating region; 115, carrier storage region; 116, drift region; 117, first conductivity type contact region; 120, Gate trench; 1201, side wall; 1202, bottom wall; 121, gate dielectric material layer; 1211, gate dielectric layer; 1212, dummy gate dielectric layer; 122, gate material layer; 1221, gate; 1222, dummy gate; 1210, gate structure; 1220, dummy gate structure; 130, interlayer dielectric layer; 140, first contact hole; 141, conductive plug; 151, emitter metal layer; 310, first mask layer; 320, second mask layer. DETAILED DESCRIPTION

[0035] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0036] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0037] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0038] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0039] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0040] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0042] The embodiment of the present application provides a power semiconductor device, which may be an IGBT device, or other MOS gated power devices, or other types of power semiconductor devices having a similar structure to the IGBT. In the following, the power semiconductor device will be described by taking the structure of the IGBT as an example.

[0043] Please refer to Figure 1The power semiconductor device provided by the embodiment of the present application includes: a semiconductor material layer 110, the semiconductor material layer 110 includes an upper surface 1101 and a lower surface 1102 opposite to each other, the semiconductor material layer 110 includes a first doping region 114 located on the side of the upper surface 1101 and a drift region 116 located below the first doping region 114, the first doping region 114 has a first conductivity type, and the drift region 116 has a second conductivity type different from the first conductivity type; a plurality of gate trenches 120 extending from the upper surface 1101 through the first doping region 114 to the drift region 116, at least one gate trench 120 is provided with a gate 1221; wherein the first doping region 114 includes at least one first conductivity type base region 1141 and at least one first conductivity type base region 1142 separated by the plurality of gate trenches 120. At least one first conductive type controllable region 1142; a second conductive type emitter region 113, located on the surface of the first conductive type base region 1141; adjacently arranged first conductive type doped regions 112 and second conductive type doped regions 111, located in the first conductive type controllable region 1142 and / or located on the first conductive type controllable region; wherein the first conductive type doped region 112 and the first conductive type base region 1141 and the second conductive type emitter region 113 are commonly connected to the emitter metal layer 151, and the second conductive type doped region 111 and the gate 1221 are commonly connected to the gate metal layer (not shown in the figure, because the cross-section in the figure does not cut through the gate metal layer, Vg and the black line indicate that gate voltage is applied to both the second conductive type doped region 111 and the gate 1221).

[0044] It can be understood that through the embodiments of the present application, on the one hand, at the initial stage of device startup, the first conductive type carriers gradually enter the first doped region 114. Since the first conductive type doped region 112 is provided in the first conductive type controllable region 1142, and the first conductive type doped region 112 is connected to the emitter metal layer 151, the first conductive type doped region 112 can directly extract the first conductive type carriers in the first conductive type controllable region 1142 into the emitter metal layer 151, and at the same time clamp the potential of the first conductive type controllable region 1142 to a low potential, thereby suppressing the displacement current and reducing the current change rate di / dt when the zero current is turned on, thereby The EMI noise is reduced; since the gate 1221 is still at a relatively low potential even though it has reached the turn-on voltage, the second conductive type doping region 111 having the same potential as the gate 1221 is also at a relatively low potential, and the second conductive type doping region 111 will not affect the extraction of the first conductive type carrier by the first conductive type doping region 112; the first conductive type carrier passes through the drift region 116 from the back of the device into the first conductive type controllable region 1142, and is then extracted from the first conductive type controllable region 1142 to the emitter metal layer 151 via the first conductive type doping region 112. It can be seen that the embodiment of the present application adds an extraction path for the first conductive type carrier (please refer to Fig.10 , adding path ①), alleviating the problem of first conductivity type carrier accumulation in the first doped region 114, enhancing the control of the gate 1221, and thus reducing EMI noise; on the other hand, in the later stage of device startup, the gate 1221 reaches a higher potential, and the second conductivity type doped region 111 with the same potential as the gate 1221 is also at a higher potential, so that the second conductivity type doped region 111 and the first conductivity type doped region 112 are completely exhausted, and the added extraction path (path ①) is completely cut off, thereby avoiding a large amount of carrier loss, ensuring the carrier concentration on the emitter side of the device, and enhancing the conductivity modulation effect.

[0045] Please continue to refer to Figure 1 The upper surface 1101 of the semiconductor material layer 110 is specifically an operation surface in the process of forming the gate trench 120. When the flatness of the upper surface 1101 and the lower surface 1102 are ignored, the direction perpendicular to the upper surface 1101 and the lower surface 1102 of the semiconductor material layer 110 is defined as the thickness direction of the semiconductor material layer 110, or the thickness direction of the device.

[0046] The power semiconductor device may further include a growth substrate (not shown in the figure), and the semiconductor material layer 110 may be an epitaxial layer grown on the growth substrate. The growth substrate may be a base of the power semiconductor device and a carrier for adding subsequent material layers. The semiconductor material layer 110 is located above the growth substrate in a manner that the lower surface 1102 is close to the growth substrate.

[0047] A buffer layer and a collector (not shown) may also be included below the drift region 116. The buffer layer is located between the drift region 116 and the collector. The buffer layer has the second conductivity type; and the collector has the first conductivity type.

[0048] In various embodiments of the present application, the first conductivity type may be N-type, and thus the second conductivity type is P-type; or, the first conductivity type is P-type, and correspondingly, the second conductivity type is N-type.

[0049] In some embodiments, the first conductivity type is P-type, and the second conductivity type is N-type. Thus, the collector is a P-type collector; the buffer layer is an N-type buffer layer. The drift region 116 is an N-type drift region; the first doped region 114 is a P-type doped region. The first conductivity type carrier is specifically a hole. However, it should be understood that in some other embodiments, the first conductivity type may also be N-type, so that the first conductivity type carrier is an electron; accordingly, the embodiment of the present application can obviously also alleviate the problem of electron accumulation in the N-type first doped region 114, thereby reducing EMI noise.

[0050] Hereinafter, the power semiconductor device will be described by taking the case where the first conductivity type is P type as an example.

[0051] The first doped region 114 may also be referred to as a P-type well region (P well, PW) or a P-type base region; however, in the device provided in the embodiment of the present application, only a portion of the first doped region 114 is used as a P-type base region. To avoid confusion, hereinafter only the first conductive type base region 1141 used as a P-type base region is referred to as a base region, and the entire region is referred to as the first doped region 114.

[0052] The first doping region 114 is located in the semiconductor material layer 110 and extends to a preset depth from the upper surface 1101 to the lower surface 1102. In the actual preparation process, the first doping region 114 can be formed by doping the semiconductor material layer 110, wherein the doping can be specifically achieved by an ion implantation process. The portion of the semiconductor material layer 110 located below the first doping region 114 is not doped to form a drift region 116.

[0053] The gate trench 120 can be formed by etching the semiconductor material layer 110 . This process is well known to those skilled in the art and will not be described in detail herein. The gate trench 120 includes a sidewall 1201 and a bottom wall 1202 , wherein the bottom wall 1202 is located in the drift region 116 .

[0054] The gate trench 120 is filled with a gate dielectric material layer 121 and a gate material layer 122. The gate dielectric material layer 121 covers the sidewalls 1201 and the bottom wall 1202 of the gate trench 120; the gate material layer 122 is located in the gate dielectric material layer 121 and is separated from the semiconductor material layer 110 by the gate dielectric material layer 121. The gate dielectric material layer 121 located in a portion of the gate trench 120 is used to form a gate dielectric layer 1211, and the gate dielectric material layer 121 located in a portion of the gate trench 120 is used to form a dummy gate dielectric layer 1212; accordingly, the gate material layer 122 located in the gate dielectric layer 1211 is used to form a gate 1221, and the gate material layer 122 located in the dummy gate dielectric layer 1212 is used to form a dummy gate 1222. The gate dielectric layer 1211 and the gate 1221 together constitute a gate structure 1210, and the dummy gate dielectric layer 1212 and the dummy gate 1222 together constitute a dummy gate structure 1220.

[0055] The gate dielectric material layer 121 and the gate material layer 122 may be formed using materials and processes well known to those skilled in the art, which will not be described in detail herein.

[0056] The first doped region 114 is divided into a plurality of regions by a plurality of gate trenches 120. Specifically, the first doped region 114 includes at least one first conductive type base region 1141 and at least one first conductive type controllable region 1142; in addition, it also includes at least one first conductive type floating region 1143. The first conductive type base regions 1141, the first conductive type controllable regions 1142, the first conductive type floating regions 1143, and the first conductive type base regions 1141, the first conductive type controllable regions 1142, and the first conductive type floating regions 1143 are separated by gate trenches 120.

[0057] The second conductive type emitter region 113 is arranged in the first conductive type base region 1141. The portion of the first conductive type base region 1141 located below the second conductive type emitter region 113 and close to the gate trench 120 is used to form a channel. It can be understood that the gate structure 1210 and the dummy gate structure 1220 can be distinguished according to whether the gate trench 120 is adjacent to the second conductive type emitter region 113; in the case of being adjacent to the second conductive type emitter region 113, since the portion of the first conductive type base region 1141 located below the second conductive type emitter region 113 can form a channel, the gate structure 1210 is arranged in the gate trench 120; otherwise, Figure 1 The pseudo gate structure 1220, in which the gate trench 120 is located, is not adjacent to any second conductive type emitter region 113. Therefore, even though the pseudo gate 1222 and the gate 1221 included in the pseudo gate structure 1220 are not different in material, a channel cannot be formed around the pseudo gate structure 1220 due to their different functions. Therefore, the structure arranged in the gate trench 120 is called a pseudo gate structure 1220.

[0058] exist Figure 1 In the illustrated embodiment, the first conductivity type doping region 112 and the second conductivity type doping region 111 are located in the first conductivity type controllable region 1142. In actual preparation, the first conductivity type doping region 112 and the second conductivity type doping region 111 can be formed by doping the first doping region 114 in which the first conductivity type doping region 112 is to be formed and the second conductivity type doping region 111 is to be formed.

[0059] exist Fig.11In another embodiment shown, the first conductive type doping region 112 and the second conductive type doping region 111 are located on the first conductive type controllable region 1142. In actual preparation, a semiconductor material layer of a certain thickness (hereinafter referred to as the "second semiconductor material layer" in order to distinguish it from the semiconductor material layer 110) can be deposited on the first conductive type controllable region 1142, and the second semiconductor material layer is specifically, for example, a polysilicon layer, etc.; and then the second semiconductor material layer is doped to form the first conductive type doping region 112 and the second conductive type doping region 111, respectively.

[0060] The doping is achieved, for example, by using an ion implantation process well known in the art.

[0061] It should be understood that, although not shown in the figure, the first conductive type doping region 112 and the second conductive type doping region 111 may also be partially located on the first conductive type controllable region 1142 and partially located in the first conductive type controllable region 1142. Specifically, for example, an ion implantation process is performed on the second semiconductor material layer, and the implantation depth exceeds the thickness of the second semiconductor material layer so that the doped ions enter the first conductive type controllable region 1142, so that the second semiconductor material layer and the first semiconductor material layer 110 as a whole can be considered as an ion-doped substrate.

[0062] In other words, the first conductive type doped region 112 and the second conductive type doped region 111 may be located within the first conductive type controllable region 1142 , or on the first conductive type controllable region 1142 , or within and on the first conductive type controllable region 1142 .

[0063] As an optional specific example, the first conductive type doping region 112 and the second conductive type doping region 111 are arranged adjacent to each other in a direction parallel to the upper surface 1101. This not only facilitates the conductive extraction of the first conductive type doping region 112 and the second conductive type doping region 111, but also facilitates the formation of path ① (the first conductive type carriers pass through the drift region 116 from the back of the device into the first conductive type controllable region 1142, and then are extracted from the first conductive type controllable region 1142 to the emitter metal layer 151 via the first conductive type doping region 112).

[0064] It should be noted that the embodiments of the present application are not limited to this, and the first conductive type doping region 112 and the second conductive type doping region 111 may also be arranged adjacently along other directions; for example, arranged adjacently along a direction perpendicular to the upper surface 1101, or arranged adjacently along multiple different directions.

[0065] As an optional specific example, the net doping concentration of the first conductive type ions of the first conductive type doping region 112 is lower than the net doping concentration of the first conductive type ions of the first conductive type controllable region 1142. The net doping concentration can be calculated based on the difference between the concentration of the first conductive type dopant and the concentration of the second conductive type dopant. In an actual device, the first conductive type controllable region 1142 is a P-type controllable region, the first conductive type doping region 112 is a P-region, and the net doping concentration of the P-region is lower than the net doping concentration of the P-type controllable region.

[0066] It can be understood that in the later stage of device startup, in order to prevent a large amount of loss of the first conductive type carriers, it is necessary to quickly increase the extraction path (i.e. Fig.10 The path ① shown in the figure is completely cut off, and the first conductive type doped region 112 is set to have a first conductive type carrier concentration lower than the first conductive type carrier concentration of the first conductive type controllable region 1142, so that the first conductive type doped region 112 is more easily depleted, thereby accelerating the cutoff speed of path ① and increasing the carrier concentration on the emitter side.

[0067] In the specific preparation, the second conductive type ion doping can be performed on the area of ​​the first conductive type controllable region 1142 where the first conductive type doped region 112 is to be formed to reduce the concentration of the first conductive type carriers. In this way, the net doping concentration of the first conductive type ions in the first conductive type doped region 112 obtained is equal to the net doping concentration of the first conductive type ions in the original first conductive type controllable region 1142 minus the concentration of the second conductive type dopant introduced when the second conductive type ion doping is performed, thereby forming a first conductive type doped region 112 in which the net doping concentration of the first conductive type ions is lower than the net doping concentration of the first conductive type ions in the first conductive type controllable region 1142.

[0068] In order to reduce the contact resistance, a first conductive type contact region 117 may be provided on the surface layer of the first conductive type doping region 112, and the first conductive type carrier concentration of the first conductive type contact region 117 is higher than the first conductive type carrier concentration of the first conductive type doping region 112. The first conductive type contact region 117 may also be referred to as a first conductive type carrier heavily doped region, specifically, for example, a P+ region.

[0069] As an optional specific example, the second conductivity type doped region 111 is a second conductivity type carrier heavily doped region, for example, a N+ region.

[0070] As an optional specific example, the second conductive type doping region 111 is arranged around the first conductive type doping region 112. Here, "surrounding" includes both partial surrounding and complete surrounding. Figure 1The second conductive type doping region 111 may be disposed along the side of the first conductive type doping region 112 and surround the first conductive type doping region 112 ( Figure 1 The middle cross-section shows two portions of the second conductive type doping region 111 located on the left and right sides of the first conductive type doping region 112); and exposes the top and bottom surfaces of the first conductive type doping region 112, so as not to affect path ①.

[0071] It can be understood that in the later stage of device startup, the gate 1221 reaches a higher potential, so the second conductive type doping region 111 also reaches a higher potential. The second conductive type doping region 111 can simultaneously deplete the first conductive type doping region 112 from different sides of the first conductive type doping region 112, thereby accelerating the cutoff speed of path ① and increasing the carrier concentration on the emitter side.

[0072] As an optional specific example, the first conductive type doping region 112 and the second conductive type doping region 111 have the same size in a direction perpendicular to the upper surface 1101. Thus, the bottom surface of the first conductive type doping region 112 contacts the first conductive type controllable region 1142, forming an extraction path for the first conductive type carriers at the initial stage of device startup; the side surface of the first conductive type doping region 112 contacts the second conductive type doping region 111, making it easier to be completely depleted at the later stage of device startup.

[0073] As an optional specific example, the second conductive type doped region 111 is not adjacent to any gate trench 120, but is spaced between adjacent gate trenches 120. Specifically, the second conductive type doped region 111 and the adjacent gate trench 120 are separated by the first conductive type controllable region 1142.

[0074] It can be understood that if the second conductive type doping region 111 is adjacent to the gate trench 120, since the second conductive type doping region 111 and the second conductive type emitter region 113 are both second conductive type regions, specifically, they can both be N+ regions; thus, the portion of the first conductive type controllable region 1142 located below the second conductive type doping region 111 and close to the gate trench 120 also has the risk of forming a channel. In order to avoid the erroneous formation of a channel, the second conductive type doping region 111 and the gate trench 120 adjacent thereto are spaced apart to ensure the normal operation of the device.

[0075] Please continue to refer to Figure 1As an optional specific example, the power semiconductor device may further include: a first contact hole 140, exposing the first conductive type doped region 112 from the upper surface 1101 side and extending into the first conductive type doped region 112, the side wall of the first contact hole 140 and the second conductive type doped region 111 and the bottom of the first contact hole 140 and the first conductive type controllable region 1142 are separated by the first conductive type doped region 112; a conductive plug 141, filled in the first contact hole 140.

[0076] The first contact hole 140 can be formed by etching the semiconductor material layer 110; this process is well known to those skilled in the art and will not be described in detail here. The conductive plug 141 can be formed by filling the first contact hole 140 with a conductive material, such as metal tungsten. The conductive plug 141 is used to conductively lead out the first conductive type doping region 112, specifically to conductively connect the first conductive type doping region 112 to the emitter metal layer 151.

[0077] In addition to forming the first contact hole 140 in the first conductive type controllable region 1142 (specifically, the first conductive type doped region 112), a second contact hole exposing the first conductive type base region 1141 and the second conductive type emitter region 113 may be simultaneously formed in the first conductive type base region 1141. Similarly, a corresponding conductive plug is also filled in the second contact hole, so as to realize common connection between the first conductive type base region 1141 and the second conductive type emitter region 113 and the emitter metal layer 151.

[0078] It should be understood that the power semiconductor device may further include an interlayer dielectric layer 130 . The interlayer dielectric layer 130 covers the upper surface 1101 of the semiconductor material layer 110 ; the first contact hole 140 and the second contact hole penetrate the interlayer dielectric layer 130 .

[0079] To reduce contact resistance, the first conductive type contact region 117 may be located at least on the surface of the first conductive type doped region 112 exposed by the bottom of the first contact hole 140 ; ​​the conductive plug 141 is conductively connected to the first conductive type contact region 117 .

[0080] In this way, the conductive plug 141 penetrates deep into the first conductive type doping region 112 to extract the first conductive type carriers from the first conductive type doping region 112 ; and the conductive plug 141 does not contact the second conductive type doping region 111 .

[0081] In the first conductive type base region 1141, the second contact hole exposes the first conductive type base region 1141 and the second conductive type emitter region 113, so that the corresponding conductive plug is in contact with the first conductive type base region 1141 and the second conductive type emitter region 113 at the same time. It can be understood that in order to reduce the contact resistance in the second contact hole, a first conductive type contact region 117 can also be provided on the surface layer of the first conductive type base region 1141 exposed by the bottom of the second contact hole.

[0082] Optionally, the dimensions of the first conductive type doping region 112 and the second conductive type doping region 111 in a direction perpendicular to the upper surface 1101 are both greater than the dimensions of the second conductive type emitter region 113 in a direction perpendicular to the upper surface 1101, thereby ensuring the effects of the first conductive type doping region 112 and the second conductive type doping region 111.

[0083] Please continue to refer to Figure 1 , the power semiconductor device may further include an emitter metal layer 151. The first conductive type doped region 112 is connected to the emitter metal layer 151 together with the first conductive type base region 1141 and the second conductive type emitter region 113. Specifically, the emitter metal layer 151 may be directly connected to the conductive plug 141, and at the same time directly connected to the conductive plug filled in the second contact hole. The emitter metal layer 151 may be formed by a top metal layer (Top Metal, TM) formation process commonly used in the art; the material of the emitter metal layer 151 includes, for example, aluminum copper, etc.

[0084] In addition to the emitter metal layer 151, the power semiconductor device may further include a gate metal layer. It is understandable that the gate metal layer and the emitter metal layer 151 may be the same metal layer, but are located in different regions in the plane layout and isolated by a dielectric layer.

[0085] The second conductive type doping region 111 and the gate 1221 are commonly connected to the gate metal layer.

[0086] The dummy gate 1222 may be in a floating state and not conductively connected to the gate metal layer.

[0087] Please continue to refer to Figure 1 As an optional specific example, the power semiconductor device may further include a carrier storage region 115, which is located between the first doped region 114 and the drift region 116; the carrier storage region 115 is located on both sides of a gate trench 120 in which a gate 1221 is arranged; the first doped region 114 and the drift region 116 are in direct contact below the first conductive type floating region 1143, below the first conductive type doped region 112, and at the side wall 1201 of the gate trench 120 in which a dummy gate structure 1220 is arranged.

[0088] The carrier storage region 115 is also called a CS region; the carrier storage region 115 has the second conductivity type, and specifically may be a high-concentration second conductivity type doping region, such as a high-concentration N-type doping region (N+ region). By setting the carrier storage region 115, a potential barrier (for example, a hole barrier) can be formed near the gate structure 1210, thereby further improving the carrier density on the emitter side and enhancing the conductivity of the drift region 116. At the same time, by setting the carrier storage region 115 only outside the side wall 1201 of the gate trench 120 in which the gate 1221 is set, that is, setting the carrier storage region 115 on both sides of the gate structure 1210, and below the first conductive type floating region 1143, below the first conductive type doped region 112, and at the side wall 1201 of the gate trench 120 in which the dummy gate structure 1220 is set, the first doped region 114 and the drift region 116 are in direct contact, thereby effectively adjusting the distribution of the carrier extraction path, thereby effectively improving the hole accumulation on the gate side, reducing the displacement current, and reducing EMI noise.

[0089] Figure 2 is a schematic diagram of the cross-sectional structure of a power semiconductor device in a pair of ratios. Figure 1 The difference between the illustrated embodiments is that, on the one hand, the first conductive type doping region 112 and the second conductive type doping region 111 are not provided, thereby not forming the first conductive type controllable region 1142, but the first conductive type floating region 1143 is retained at the corresponding position of the first doping region 114; on the other hand, the carrier storage region 115 is located between the first doping region 114 and the drift region 116, and the bottom surface of the first doping region 114 is entirely formed with the carrier storage region 115.

[0090] Through Figure 1 The power semiconductor device and Figure 2 The power semiconductor device in the comparative example shown is simulated, and the simulation conditions are controlled to be the same, and the threshold voltage Vth is aligned (both are Vth corresponding to 15mA), so that a comparison chart of the simulation results of the two schemes can be obtained (as shown in Figure 3 as shown). Figure 3 The horizontal axis is time T (Times), and the vertical axis is current Ic. Figure 3 Specifically, the current variation curves of the two different schemes at zero current turn-on are shown. The gate voltage Vg, collector-emitter voltage Vce, gate resistance Rg, threshold voltage Vth, current change rate di / dt_on, current peak Icpeak, turn-on loss Eon, turn-off loss Eoff, and total switching loss Ets of the two different schemes are shown in Table 1.

[0091] Table 1

[0092]

[0093] From Table 1, we can see that Figure 1 The power semiconductor device in the embodiment of the present application shown in FIG. Figure 2 In the power semiconductor device of the comparative example shown, the current change rate di / dt_on decreases by 6.4%, the current peak Icpeak of zero current turn-on decreases by 59.7%, and the turn-on loss Eon and turn-off loss Eoff also decrease, so that the total switching loss Ets decreases by 12.9%. The embodiment of the present application effectively improves the EMI noise problem of the system and reduces the dynamic loss.

[0094] The present application also provides a method for preparing a power semiconductor device. Figure 4 , the method comprising:

[0095] Step S401, providing a semiconductor material layer having a second conductivity type, wherein the semiconductor material layer includes an upper surface and a lower surface opposite to each other;

[0096] Step S402, forming a plurality of gate trenches extending from the upper surface of the semiconductor material layer to the interior of the semiconductor material layer, at least one gate trench is used to set a gate;

[0097] Step S403, doping the semiconductor material layer to form a first doped region with a first conductivity type on the upper surface side of the semiconductor material layer, a portion of the semiconductor material layer located below the first doped region forms a drift region, and the first conductivity type is different from the second conductivity type; wherein the first doped region includes at least one first conductivity type base region and at least one first conductivity type controllable region separated by a plurality of gate trenches;

[0098] Step S404, forming a second conductivity type emitter region on the surface layer of the first conductivity type base region, and forming a first conductivity type doped region and a second conductivity type doped region in and / or on the first conductivity type controllable region, the first conductivity type doped region and the second conductivity type doped region being arranged adjacent to each other;

[0099] Step S405, forming an emitter metal layer and a gate metal layer, the emitter metal layer is conductively connected to the first conductive type doping region, the first conductive type base region and the second conductive type emitter region, and the gate metal layer is conductively connected to the second conductive type doping region and the gate.

[0100] In this way, by setting at least one first conductive type controllable region, and forming adjacently arranged first conductive type doped regions and second conductive type doped regions in the first conductive type controllable region, and making the second conductive type doped region and the gate at the same potential, and the first conductive type doped region and the second conductive type emitter region at the same potential, thereby, on the one hand, reducing EMI noise, and on the other hand, avoiding a large amount of carrier loss, ensuring the carrier concentration on the emitter side of the device, and enhancing the conductivity modulation effect.

[0101] It should be noted that although Figure 4 The various steps in the flowchart are displayed in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows; the execution sequence between the steps should still be determined according to the specific logical relationship.

[0102] Next, combine Figures 5 to 10 The method for preparing the power semiconductor device provided in the embodiment of the present application is further described in detail.

[0103] First, please refer to Figure 5 Step S401 is performed to provide a semiconductor material layer 110 having a second conductivity type. The semiconductor material layer 110 includes an upper surface 1101 and a lower surface 1102 opposite to each other.

[0104] As an optional specific example, a carrier storage area 115 may be formed in the semiconductor material layer 110. Specifically, a patterned first mask layer 310 may be formed on the semiconductor material layer 110. The first mask layer 310 may specifically be a hard mask (HM) layer; the patterning process of the first mask layer 310 may include HM material layer deposition, photoresist spin coating, exposure, development, etching and other processes well known in the art. The pattern of the first mask layer 310 exposes a preset formation area of ​​the carrier storage area 115; next, the second conductive type ions are implanted into the semiconductor material layer 110 through an ion implantation process to form a carrier storage area 115 with a high ion doping concentration.

[0105] Next, please refer to Figure 6. Step S402 is performed to form a plurality of gate trenches 120 extending from the upper surface 1101 of the semiconductor material layer 110 to the inside of the semiconductor material layer 110. Specifically, a patterned second mask layer 320 may be first formed on the semiconductor material layer 110, and the pattern of the second mask layer 320 exposes a preset formation area of ​​the gate trench 120; next, the semiconductor material layer 110 is etched using the second mask layer 320 as a mask to form the gate trench 120. The gate trench 120 includes a sidewall 1201 and a bottom wall 1202. The depth of the bottom wall 1202 of the gate trench 120 is lower than the depth of the bottom surface of the carrier storage area 115 to ensure that the gate trench 120 extends into the offset area. The gate trench 120 used to form a gate structure in a subsequent process passes through the carrier storage area 115, thereby ensuring that the carrier storage area 115 is located on both sides of the gate trench 120 in which the gate structure is disposed.

[0106] Next, please refer to Figure 7 . A gate dielectric material layer 121 is filled in the gate trench 120, and the gate dielectric material layer 121 covers the sidewalls 1201 and the bottom wall 1202 of the gate trench 120; a gate material layer 122 is filled in the gate dielectric material layer 121. The gate dielectric material layer 121 located in part of the gate trench 120 is used to form a gate dielectric layer 1211, and the gate dielectric material layer 121 located in part of the gate trench 120 is used to form a dummy gate dielectric layer 1212; accordingly, the gate material layer 122 located in the gate dielectric layer 1211 is used to form a gate 1221, and the gate material layer 122 located in the dummy gate dielectric layer 1212 is used to form a dummy gate 1222. The gate dielectric layer 1211 and the gate 1221 together constitute a gate structure 1210, and the dummy gate dielectric layer 1212 and the dummy gate 1222 together constitute a dummy gate structure 1220.

[0107] Next, please refer to Figure 8 Step S403 is performed to dope the semiconductor material layer 110 to form a first doping region 114 having a first conductivity type on the upper surface 1101 side of the semiconductor material layer 110, and a portion of the semiconductor material layer 110 located below the first doping region 114 forms a drift region 116; wherein the first doping region 114 includes at least one first conductivity type base region 1141 separated by a plurality of gate trenches 120, at least one first conductivity type controllable region 1142, and at least one first conductivity type floating region 1143.

[0108] Please continue to refer to Figure 8Next, step S402 is performed to form a second conductive type emitter region 113 on the surface of the first conductive type base region 1141, and to form a first conductive type doping region 112 and a second conductive type doping region 111 in the first conductive type controllable region 1142. The first conductive type doping region 112 and the second conductive type doping region 111 are adjacently arranged in a direction parallel to the upper surface 1101.

[0109] It should be understood that the first conductive type doped region 112 and the second conductive type doped region 111 may also be formed on the first conductive type controllable region 1142 or partially on the first conductive type controllable region 1142 and partially in the first conductive type controllable region 1142. In actual preparation, a second semiconductor material layer of a certain thickness may be deposited on the first conductive type controllable region 1142; and then the second semiconductor material layer may be doped, and the doping depth may be less than or equal to the thickness of the second semiconductor material layer, or may be greater than the thickness of the second semiconductor material layer, so as to form the first conductive type doped region 112 and the second conductive type doped region 111, respectively.

[0110] The doping is achieved, for example, by using an ion implantation process well known in the art.

[0111] In addition, the first conductive type doping region 112 and the second conductive type doping region 111 may also be arranged adjacently along other directions. During specific preparation, the doping position and doping sequence may be adjusted according to design requirements.

[0112] As an optional specific example, forming the second conductive type emitter region 113 on the surface layer of the first conductive type base region 1141, and forming the second conductive type doped region 111 in the first conductive type controllable region 1142, includes: firstly performing second conductive type ion doping and annealing on the region in the first conductive type controllable region 1142 where the second conductive type doped region 111 is to be formed, and then performing second conductive type ion doping and annealing on the region in the surface layer of the first conductive type base region 1141 where the second conductive type emitter region 113 is to be formed. In this way, the formation process of the second conductive type doped region 111 (especially the annealing process after ion implantation) is prevented from affecting the second conductive type emitter region 113.

[0113] As an optional specific example, forming a first conductive type doped region 112 in a first conductive type controllable region 1142 includes: performing second conductive type ion doping on an area in the first conductive type controllable region 1142 where the first conductive type doped region 112 is to be formed, so as to reduce the net doping concentration of the first conductive type ions, thereby forming a first conductive type doped region 112 in which the net doping concentration of the first conductive type ions is lower than the net doping concentration of the first conductive type ions in the first conductive type controllable region 1142.

[0114] As an optional specific example, the second conductive type doping region 111 is arranged around the first conductive type doping region 112 .

[0115] As an optional specific example, the first conductivity type doping region 112 and the second conductivity type doping region 111 have the same size in a direction perpendicular to the upper surface 1101. Further, in the case where the first conductivity type doping region 112 and the second conductivity type doping region 111 are within the first conductivity type controllable region 1142, the first conductivity type doping region 112 and the second conductivity type doping region 111 have the same extension depth within the first conductivity type controllable region 1142.

[0116] As an optional specific example, the dimensions of the first conductive type doping region 112 and the second conductive type doping region 111 in a direction perpendicular to the upper surface 1101 are both greater than the dimension of the second conductive type emitter region 113 in a direction perpendicular to the upper surface 1101, thereby ensuring the effects of the first conductive type doping region 112 and the second conductive type doping region 111.

[0117] As an optional specific example, the second conductivity type doped region 111 and the gate trench 120 adjacent thereto are separated by the first conductivity type controllable region 1142 .

[0118] As an optional specific example, the first doped region 114 is located above the carrier storage region 115; the first doped region 114 also includes at least one first conductive type floating region 1143, and each first conductive type floating region 1143 and the first conductive type floating region 1143, the first conductive type base region 1141 and the first conductive type controllable region 1142 are separated by a gate trench 120; at least one gate trench 120 is used to set a dummy gate structure 1220; the carrier storage region 115 is located on both sides of the gate trench 120 in which the gate 1221 is set; the first doped region 114 and the drift region 116 are in direct contact below the first conductive type floating region 1143, below the first conductive type doped region 112, and at the side wall 1201 of the gate trench 120 in which the dummy gate structure 1220 is set.

[0119] Next, please refer to Fig. 9A first contact hole 140 is formed, the first contact hole 140 exposes the first conductive type doping region 112 from the upper surface 1101 side and extends into the first conductive type doping region 112, the sidewall of the first contact hole 140 and the second conductive type doping region 111 and the bottom of the first contact hole 140 and the first conductive type controllable region 1142 are separated by the first conductive type doping region 112; the surface layer of the first conductive type doping region 112 exposed by the bottom of the first contact hole 140 is doped with the first conductive type ions to form a first conductive type contact region 117. In addition, a second contact hole exposing the first conductive type base region 1141 and the second conductive type emitter region 113 can be formed in the first conductive type base region 1141 simultaneously; and, further, the surface layer of the first conductive type base region 1141 exposed by the bottom of the second contact hole can be doped with the first conductive type ions, so that the first conductive type contact region 117 is also formed in the second contact hole.

[0120] Next, please refer to Fig.10 A conductive material is filled in the first contact hole 140 to form a conductive plug 141, and the conductive plug 141 is conductively connected to the first conductive type contact area 117. In addition, a corresponding conductive plug can be formed in the second contact hole simultaneously, so as to realize conductive extraction of the first conductive type contact area 117 in the second contact hole.

[0121] Next, please continue to refer to Fig.10 Step S402 is performed to form an emitter metal layer 151 and a gate metal layer. The emitter metal layer 151 is conductively connected to the first conductive type doping region 112 , the first conductive type base region 1141 , and the second conductive type emitter region 113 . The gate 1221 metal layer is conductively connected to the second conductive type doping region 111 and the gate 1221 .

[0122] It should be noted that the embodiment of the method for preparing the power semiconductor device provided in the present application and the embodiment of the power semiconductor device belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the combination of the various technical features of the power semiconductor device provided in the embodiment of the present application can already solve the technical problem to be solved by the present application; therefore, the power semiconductor device provided in the embodiment of the present application may not be limited by the method for preparing the power semiconductor device provided in the embodiment of the present application, and any power semiconductor device prepared by the preparation method that can form the structure of the power semiconductor device provided in the embodiment of the present application is within the scope of protection of the present application.

[0123] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A power semiconductor device, characterized in that: include: A semiconductor material layer, comprising an upper surface and a lower surface opposite to each other, wherein the semiconductor material layer comprises a first doped region located on the upper surface side and a drift region located below the first doped region, wherein the first doped region has a first conductivity type, and the drift region has a second conductivity type different from the first conductivity type; A plurality of gate trenches extending from the upper surface through the first doped region to the drift region, a gate being disposed in at least one of the gate trenches; wherein the first doped region comprises at least one first conductive type base region and at least one first conductive type controllable region separated by the plurality of gate trenches; A second conductive type emitter region, located on a surface layer of the first conductive type base region; The first conductivity type doped region and the second conductivity type doped region are adjacently arranged and located in the first conductivity type controllable region and / or on the first conductivity type controllable region; The first conductive type doping region, the first conductive type base region and the second conductive type emitter region are connected to the emitter metal layer, and the second conductive type doping region and the gate are connected to the gate metal layer. Also included is a carrier storage region, the carrier storage region being located between the first doped region and the drift region; The first doped region further includes at least one first conductive type floating region, and each of the first conductive type floating regions and the first conductive type floating regions, the first conductive type base region and the first conductive type controllable region are separated by the gate trench; A dummy gate structure is disposed in at least one of the gate trenches; The carrier storage region is located on both sides of a gate trench in which a gate is arranged, the gate trench includes a side wall and a bottom wall, the depth of the bottom wall of the gate trench is lower than the depth of the bottom surface of the carrier storage region, and the gate trench in which the gate is arranged passes through the carrier storage region; The first doped region is in direct contact with the drift region below the first conductive type floating region, below the first conductive type doped region, and at a sidewall of a gate trench in which a dummy gate structure is disposed.

2. The power semiconductor device according to claim 1, characterized in that: A net doping concentration of the first conductivity type ions in the first conductivity type doping region is lower than a net doping concentration of the first conductivity type ions in the first conductivity type controllable region.

3. The power semiconductor device according to claim 1, characterized in that: The second conductive type doping region is disposed around the first conductive type doping region.

4. The power semiconductor device according to claim 1, characterized in that: The first conductive type doping region and the second conductive type doping region are adjacently arranged along a direction parallel to the upper surface.

5. The power semiconductor device according to claim 4, characterized in that: The first conductive type doping region and the second conductive type doping region have the same size in a direction perpendicular to the upper surface.

6. The power semiconductor device according to claim 4, characterized in that: Also includes: a first contact hole, exposing the first conductive type doped region from the upper surface side and extending into the first conductive type doped region, wherein the sidewall of the first contact hole and the second conductive type doped region and the bottom of the first contact hole and the first conductive type controllable region are separated by the first conductive type doped region; A first conductive type contact region, at least located at a surface layer of the first conductive type doped region exposed by the bottom of the first contact hole, wherein a first conductive type carrier concentration of the first conductive type contact region is higher than a first conductive type carrier concentration of the first conductive type doped region; A conductive plug is filled in the first contact hole and is conductively connected to the first conductive type contact area.

7. The power semiconductor device according to claim 4, characterized in that: The sizes of the first conductive type doping region and the second conductive type doping region in the direction perpendicular to the upper surface are both greater than the size of the second conductive type emission region in the direction perpendicular to the upper surface.

8. The power semiconductor device according to claim 1, characterized in that: The second conductive type doped region and the gate trench adjacent thereto are separated by the first conductive type controllable region.

9. A method for preparing a power semiconductor device, characterized in that: The method comprises: providing a semiconductor material layer having a second conductivity type, the semiconductor material layer comprising an upper surface and a lower surface opposite to each other; Forming a plurality of gate trenches extending from the upper surface of the semiconductor material layer to the interior of the semiconductor material layer, at least one of the gate trenches being used to set a gate; Doping the semiconductor material layer to form a first doped region with a first conductivity type on the upper surface side of the semiconductor material layer, a portion of the semiconductor material layer located below the first doped region forms a drift region, and the first conductivity type is different from the second conductivity type; wherein the first doped region includes at least one first conductivity type base region and at least one first conductivity type controllable region separated by a plurality of the gate trenches; forming a second conductive type emitter region on the surface layer of the first conductive type base region, and forming a first conductive type doped region and a second conductive type doped region in and / or on the first conductive type controllable region, wherein the first conductive type doped region and the second conductive type doped region are arranged adjacent to each other; forming an emitter metal layer and a gate metal layer, wherein the emitter metal layer is conductively connected to the first conductive type doped region, the first conductive type base region and the second conductive type emitter region, and the gate metal layer is conductively connected to the second conductive type doped region and the gate; Before forming a first doped region having a first conductivity type on the upper surface side of the semiconductor material layer, the method further includes forming a carrier storage region; The first doped region is located above the carrier storage region; The first doped region further includes at least one first conductive type floating region, and each of the first conductive type floating regions and the first conductive type floating regions, the first conductive type base region and the first conductive type controllable region are separated by the gate trench; At least one of the gate trenches is used to set a dummy gate structure; The carrier storage region is located on both sides of a gate trench in which a gate is arranged, the gate trench includes a side wall and a bottom wall, the depth of the bottom wall of the gate trench is lower than the depth of the bottom surface of the carrier storage region, and the gate trench in which the gate is arranged passes through the carrier storage region; The first doped region is in direct contact with the drift region below the first conductive type floating region, below the first conductive type doped region, and at a sidewall of a gate trench in which a dummy gate structure is disposed.

10. The method for preparing a power semiconductor device according to claim 9, characterized in that: Forming a second conductive type emitter region on the surface layer of the first conductive type base region, and forming a second conductive type doped region in the first conductive type controllable region, including: First, the area in the first conductive type controllable region where the second conductive type doped region is to be formed is doped with second conductive type ions and annealed, and then the area in the surface layer of the first conductive type base region where the second conductive type emitter region is to be formed is doped with second conductive type ions and annealed.

11. The method for preparing a power semiconductor device according to claim 9, characterized in that: Forming a first conductivity type doped region in the first conductivity type controllable region, comprising: The area of ​​the first conductive type controllable region where the first conductive type doped region is to be formed is doped with second conductive type ions to reduce the net doping concentration of the first conductive type ions, thereby forming the first conductive type doped region in which the net doping concentration of the first conductive type ions is lower than the net doping concentration of the first conductive type ions in the first conductive type controllable region.

12. The method for preparing a power semiconductor device according to claim 9, characterized in that: The second conductive type doping region is disposed around the first conductive type doping region.

13. The method for preparing a power semiconductor device according to claim 9, characterized in that: The first conductive type doping region and the second conductive type doping region are adjacently arranged along a direction parallel to the upper surface.

14. The method for preparing a power semiconductor device according to claim 13, characterized in that: The first conductive type doping region and the second conductive type doping region have the same size in a direction perpendicular to the upper surface.

15. The method for preparing a power semiconductor device according to claim 13, characterized in that: Before forming the emitter metal layer and the gate metal layer, the method further comprises: forming a first contact hole, wherein the first contact hole exposes the first conductive type doped region from the upper surface side and extends into the first conductive type doped region, and the sidewall of the first contact hole and the second conductive type doped region and the bottom of the first contact hole and the first conductive type controllable region are separated by the first conductive type doped region; Performing first conductivity type ion doping on a surface layer of the first conductivity type doping region exposed by the bottom of the first contact hole to form a first conductivity type contact region; A conductive material is filled in the first contact hole to form a conductive plug, and the conductive plug is conductively connected to the first conductive type contact region.

16. The method for preparing a power semiconductor device according to claim 13, characterized in that: The sizes of the first conductive type doping region and the second conductive type doping region in the direction perpendicular to the upper surface are both greater than the size of the second conductive type emission region in the direction perpendicular to the upper surface.

17. The method for preparing a power semiconductor device according to claim 9, characterized in that: The second conductive type doped region and the gate trench adjacent thereto are separated by the first conductive type controllable region.

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