Semiconductor structure and method for forming the same

Abstract

The present invention provides a semiconductor structure and a method for forming the same, wherein the method for forming the semiconductor structure comprises: providing a substrate; forming a plurality of first gate structures, wherein the plurality of first gate structures are arranged at intervals on the substrate; forming a drift region and a body region in the substrate, wherein the drift region is adjacent to the body region, wherein a portion of the structure of the first gate structure is located in the body region; forming a source region and a drain region in the substrate, wherein the source region is located in the body region, the drain region is located in the drift region, and the source region and the drain region are located on both sides of the first gate structure. The above technical solution can reduce the on-resistance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Voltage-controlled power devices are electronic devices that achieve power control by controlling voltage. They are commonly used in AC / DC (Alternating Curren / Direct Current) conversion, DC / DC (Direct Current / Direct Current) conversion, and voltage regulation in power supply.

[0003] How to reduce the on-resistance of voltage-controlled power devices is an issue worth discussing. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, which can reduce the on-resistance of the semiconductor structure.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure. The method for forming a semiconductor structure includes:

[0006] providing a substrate;

[0007] forming a plurality of first gate structures, wherein the plurality of first gate structures are disposed on the substrate at intervals;

[0008] forming a drift region and a body region in the substrate, wherein the drift region is adjacent to the body region, and a portion of the first gate structure is located in the body region;

[0009] A source region and a drain region are formed in the substrate, wherein the source region is located in the body region, the drain region is located in the drift region, and the source region and the drain region are located at two sides of the first gate structure.

[0010] Optionally, before forming the plurality of first gate structures, the method further includes:

[0011] Etching a first groove on the surface of the substrate;

[0012] A plurality of first gate structures are formed, including:

[0013] A first gate dielectric layer covering the first gate structure on the sidewall surface and the bottom surface of the first trench;

[0014] Filling the first trench to form a first gate body of the first gate structure;

[0015] A first gate extension portion of the first gate structure is covered on the surface of the first gate body and the first gate dielectric layer.

[0016] Optionally, before covering the first gate extension portion, the method further includes:

[0017] Performing ion implantation on the substrate to form a first gate dielectric extension of the first gate structure;

[0018] The first gate dielectric extension is adjacent to the first gate dielectric layer and is located on a side of the first gate dielectric layer adjacent to the drain region, and one end of the first gate dielectric extension adjacent to the drain region is located in the drift region.

[0019] Optionally, before covering the first gate extension portion, the method further includes:

[0020] The semiconductor structure is subjected to annealing treatment.

[0021] Optionally, a distance is provided between the first gate dielectric extension portion of each first gate structure and the drain region, wherein the distances corresponding to adjacent first gate structures are different.

[0022] Optionally, the first gate extension also covers the first gate dielectric extension, and an end of the first gate extension adjacent to the drain region is located above the drift region.

[0023] Optionally, the distances between the first gate extensions of adjacent first gate structures and the drain region are different.

[0024] Optionally, before etching the substrate surface to form the first groove, the method further comprises:

[0025] A second trench is formed by etching on the surface of the substrate. The second trench is located on a side of the source region away from the drain region. The depth of the bottom of the second trench is greater than the depth of the bottom surface of the source region. The second trench is adjacent to the source region.

[0026] Optionally, during the process of forming the first gate structure, the method further includes:

[0027] A second gate dielectric layer covering the second gate structure on the sidewall surface and the bottom surface of the second trench;

[0028] The second trench is filled to form a second gate body of the second gate structure to obtain the second gate structure.

[0029] Optionally, before forming the body region in the substrate, the method further comprises:

[0030] forming a deep well doping region in the substrate, wherein the doping type of the deep well doping region is consistent with that of the drift region and the doping concentration is greater than that of the drift region, and the deep well doping region is adjacent to the second gate structure and the drift region respectively;

[0031] The body region and the deep well doping region have different doping types, and the body region covers the deep well doping region, and the source region and the deep well doping region are spaced apart.

[0032] Optionally, the method for forming the semiconductor structure further includes:

[0033] An extraction region is formed in the source region, the bottom surface of the extraction region covers the body region, the doping type of the extraction region is consistent with that of the body region, and the doping concentration of the extraction region is greater than that of the body region.

[0034] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes:

[0035] substrate;

[0036] A plurality of first gate structures, wherein the plurality of first gate structures are disposed on the substrate at intervals;

[0037] a drift region, the drift region being located within the substrate;

[0038] a body region, the body region being located in the drift region and adjacent to the drift region, wherein a portion of the first gate structure is located in the body region;

[0039] a source region, the source region being located within the body region;

[0040] A drain region is located in the drift region, and the source region and the drain region are located at two sides of the first gate structure.

[0041] Optionally, the substrate surface has a first groove;

[0042] The first gate structure comprises:

[0043] a first gate dielectric layer, the first gate dielectric layer covering the sidewall surface and the bottom surface of the first trench;

[0044] a first gate body, the first gate body being located in the first trench;

[0045] A first gate extension portion covers the first gate body and a surface of the first gate dielectric layer.

[0046] Optionally, the first gate structure further includes:

[0047] A first gate dielectric extension portion is adjacent to the first gate dielectric layer and is located at a side of the first gate dielectric layer adjacent to the drain region, and an end of the first gate dielectric extension portion adjacent to the drain region is located in the drift region.

[0048] Optionally, a distance is provided between the first gate dielectric extension portion of each first gate structure and the drain region, wherein the distances corresponding to adjacent first gate structures are different.

[0049] Optionally, the first gate extension also covers the first gate dielectric extension, and an end of the first gate extension adjacent to the drain region is located above the drift region.

[0050] Optionally, the distances between the first gate extensions of adjacent first gate structures and the drain region are different.

[0051] Optionally, the substrate surface has a second groove, the second groove is located at a side of the source region away from the drain region, the depth of the second groove bottom is greater than the depth of the bottom surface of the source region, and the second groove is adjacent to the source region;

[0052] The semiconductor structure further includes a second gate structure, wherein the second gate structure includes:

[0053] A second gate dielectric layer, wherein the second gate dielectric layer is located on the sidewalls and bottom surface of the second trench;

[0054] A second gate body is located in the second trench.

[0055] Optionally, the semiconductor structure further includes:

[0056] A deep well doped region, wherein the deep well doped region is located in the substrate;

[0057] The doping type of the deep well doping region is consistent with that of the drift region, and the doping concentration is greater than that of the drift region, and the deep well doping region is adjacent to the second gate structure and the drift region respectively;

[0058] The body region and the deep well doping region have different doping types, and the body region covers the deep well doping region. The source region and the deep well doping region are spaced apart.

[0059] Optionally, the semiconductor structure further includes:

[0060] An extraction region, wherein the extraction region is located in the source region, a bottom surface of the extraction region covers the body region, a doping type of the extraction region is consistent with that of the body region, and a doping concentration is greater than that of the body region.

[0061] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0062] A plurality of first gate structures are formed on a substrate, a drift region and a body region are formed in the substrate, a source region is formed in the body region, and a drain region is formed in the drift region. By arranging a plurality of first gate structures at intervals and arranging a portion of the first gate structure in the body region, a conduction channel can be formed in the body region between adjacent first gate structures. By adjusting the depth of the portion of the first gate structure in the body region, the cross-sectional area of ​​the conduction channel can be increased, thereby reducing the on-resistance of the semiconductor structure.

[0063] Furthermore, a conductive channel of the semiconductor structure is formed in the substrate between adjacent first gate structures. The first gate body is arranged in the substrate, which can optimize the distribution of the conductive channel formed on the surface of the first gate structure when the first gate body is pressurized, and improve the uniformity of the thickness of the conductive channel on the surface of the first gate structure in a direction perpendicular to the substrate surface, thereby increasing the cross-sectional area of ​​the conductive channel and reducing the on-resistance of the semiconductor structure.

[0064] Furthermore, the distances between adjacent first gate dielectric extensions and the drain region are different, which can increase the distance between the ends of adjacent first gate dielectric extensions, thereby reducing the intensity of the superposition of electric field spikes at the ends of the first gate dielectric extensions, and further reducing the probability of breakdown at the ends of the first gate dielectric extensions.

[0065] Furthermore, the distances between adjacent first gate extensions and the drain region are different, which can increase the distance between the ends of adjacent first gate extensions, thereby reducing the intensity of the superposition of electric field spikes at the corresponding position of the drift region below the ends of the first gate extensions, and further reducing the probability of breakdown at the ends of the first gate dielectric extensions.

[0066] Furthermore, the source region is located between the first gate structure and the second gate structure, and is adjacent to the first gate structure and the second gate structure respectively, the depth of the bottom surface of the source region is less than the depth of the deep well doping region, and the source region and the deep well doping region are arranged at intervals. When a voltage is applied to the first gate structure, a conduction channel controlled by the first gate structure is formed in the region between adjacent first gate structures, and the conduction channel and the drift region are connected to the source region and the drain region; when a voltage is applied to the second gate structure, a conduction channel perpendicular to the substrate surface direction is formed on the surface of the body region adjacent to the second gate structure below the source region, and the conduction channel connects the source region and the deep well doping region, which means that the above arrangement can increase the number of conduction channels in the semiconductor structure, thereby further reducing the on-resistance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the drawings required for use in the embodiments of this specification or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0068] Figure 1 is a flow chart of a method for forming a semiconductor device in an embodiment of the present invention;

[0069] Figures 2 to 7 is a schematic cross-sectional structure diagram corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention;

[0070] Figure 8 yes Figure 7 A top view of a semiconductor structure is shown;

[0071] Fig. 9 is along Figure 8 A schematic diagram of the cross-sectional structure along the B1-B2 direction is shown.

[0072] Description of reference numerals:

[0073] Substrate 100, deep well doped region 110, drift region 120, body region 130, source region 140, drain region 150, extraction region 160;

[0074] A second trench 201, a second gate dielectric layer 210, and a second gate body 220;

[0075] A first trench 301 , a first gate dielectric layer 310 , a first gate body 320 , a first gate dielectric extension 330 , and a first gate extension 340 . DETAILED DESCRIPTION

[0076] As mentioned above, in the structural design of the voltage-controlled power device, it is necessary to reduce the on-resistance of the voltage-controlled power device.

[0077] In a specific application scenario, taking LDMOS as an example, LDMOS has a drift region, and the on-resistance of LDMOS can be reduced by increasing the doping concentration of the drift region.

[0078] In an embodiment of the present invention, a plurality of first gate structures are formed on a substrate, a drift region and a body region are formed in the substrate, a source region is formed in the body region, and a drain region is formed in the drift region. By arranging the plurality of first gate structures at intervals and arranging a portion of the first gate structure in the body region, a conduction channel can be formed in the body region between adjacent first gate structures. By adjusting the depth of the portion of the first gate structure in the body region, the cross-sectional area of ​​the conduction channel can be increased, thereby reducing the on-resistance of the semiconductor structure.

[0079] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0080] Reference Figure 1 , Figure 1 1 is a flow chart of a method for forming a semiconductor device in an embodiment of the present invention. The method for forming a semiconductor device may include steps S11 to S14:

[0081] Step S11: providing a substrate;

[0082] Step S12: forming a plurality of first gate structures, wherein the plurality of first gate structures are disposed on the substrate at intervals;

[0083] Step S13: forming a drift region and a body region in the substrate, wherein the drift region is adjacent to the body region, wherein a portion of the first gate structure is located in the body region;

[0084] Step S14: forming a source region and a drain region in the substrate, wherein the source region is located in the body region, and the drain region is located in the drift region, and the source region and the drain region are located on both sides of the first gate structure.

[0085] The following combination Figures 2 to 9 The above-mentioned formation method is explained.

[0086] Figures 2 to 7 is a schematic cross-sectional structure diagram corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention, Figure 8 yes Figure 7 A top view of the semiconductor structure shown in FIG. Fig. 9 is along Figure 8 A schematic diagram of the cross-sectional structure along the B1-B2 direction is shown.

[0087] Reference Figure 2 , providing a substrate 100.

[0088] The substrate 100 is used to provide a process platform for the subsequent formation of a semiconductor structure.

[0089] The substrate 100 may be a silicon substrate, or the material of the substrate 100 may also include germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate 100 may also be a silicon substrate on an insulator or a germanium substrate on an insulator, or a substrate on which an epitaxial layer (Epitaxylayer, Epilayer) is grown.

[0090] The doping type of the substrate 100 is P-type doping or N-type doping.

[0091] It should be noted that, in the following description, P-type doping may be used as an example for explanation, but it does not constitute a limitation on the specific doping type used for the substrate 100 .

[0092] Continue to refer to Figure 2 , a second groove 201 and a plurality of first grooves 301 are formed on the surface of the substrate 100 .

[0093] In some embodiments, the depth of the bottom surface of the second trench 201 is greater than the depth of the bottom surface of the first trench 301 .

[0094] Specifically, in this way, the depth of the structure located in the second trench 201 can be greater than the depth of the structure located in the first trench 301 .

[0095] It should be noted that the depth direction refers to a direction perpendicular to the surface of the substrate 100 .

[0096] In some embodiments, the first trench 301 is located on one side of the second trench 201 and is spaced apart from the second trench 201 .

[0097] In some embodiments, a plurality of first grooves 301 are arranged at intervals, and the area between adjacent first grooves 301 belongs to the substrate 100 .

[0098] Specifically, in this way, the structures located in different first grooves 301 can be arranged at intervals through the substrate 100 .

[0099] In some embodiments, the first trench 301 and the second trench 201 may be implemented in a variety of ways, for example, by using one or more processes such as dry etching and wet etching.

[0100] In some embodiments, the first trench 301 and the second trench 201 may be formed in various orders. For example, the second trench 201 may be formed before the first trench 301. For example, the second trench 201 may be formed after the first trench 301. For example, the first trench 301 is formed during the formation of the second trench 201.

[0101] Reference Figure 3 , forming a plurality of first gate structures, wherein the plurality of first gate structures are disposed on the substrate 100 at intervals.

[0102] Specifically, the first gate structure is located inside and on the surface of the substrate 100 .

[0103] Furthermore, forming the first gate structure may include: covering the first gate dielectric layer 310 of the first gate structure on the sidewall surface and the bottom surface of the first trench 301; filling the first trench 301 to form a first gate body 320 of the first gate structure; wherein the first gate dielectric layer 310 is located inside the substrate 100, the first gate body 320 is located inside the substrate 100, and one first gate structure corresponds to one first trench 301.

[0104] Specifically, a conductive channel of the semiconductor structure is formed in the substrate 100 between adjacent first gate structures. The first gate body 320 is disposed in the substrate 100. This can optimize the distribution of the conductive channel formed on the surface of the first gate structure when the first gate body 320 is pressurized, and improve the uniformity of the thickness of the conductive channel on the surface of the first gate structure in a direction perpendicular to the surface of the substrate 100, thereby increasing the cross-sectional area of ​​the conductive channel and reducing the on-resistance of the semiconductor structure.

[0105] Continue to refer to Figure 3 , forming a second gate structure.

[0106] Specifically, the second gate structure is located in the substrate 100 , and the bottom surface of the second gate structure has a depth greater than that of the bottom surface of the first gate structure.

[0107] Furthermore, forming the second gate structure may include: covering the second gate dielectric layer 210 of the second gate structure on the sidewall surface and the bottom surface of the second trench 201; and filling the second trench 201 to form the second gate body 220 of the second gate structure.

[0108] In some embodiments, the first gate dielectric layer 310 may be formed during the process of forming the second gate dielectric layer 210. Specifically, this can simplify the process steps.

[0109] In some embodiments, the first gate body 320 may be formed during the process of forming the second gate body 220. Specifically, this can simplify the process steps.

[0110] Reference Figure 4 , a first gate dielectric extension 330 of the first gate structure is formed in the substrate 100 .

[0111] The first gate dielectric extension 330 is adjacent to the first gate dielectric layer 310 and is located on a side of the first gate dielectric layer 310 away from the second gate structure.

[0112] Specifically, the first gate dielectric extension 330 is suitable for increasing the surface area of ​​the first gate dielectric layer 310 .

[0113] In some embodiments, there are various implementations of the first gate dielectric extension 330. For example, ion implantation is performed on the substrate 100 to form the first gate dielectric extension 330. The implanted ions may be oxygen ions.

[0114] In some embodiments, the first gate dielectric extension 330 is made of the same material as the first gate dielectric layer 310 .

[0115] In some embodiments, there are multiple first gate dielectric extensions 330 , one first gate dielectric extension 330 corresponds to one first gate dielectric layer 310 , and the multiple first gate dielectric extensions 330 are spaced apart in the substrate 100 .

[0116] Specifically, the conducting channel formed in the substrate 100 between adjacent first gate dielectric extensions 330 is controlled by the first gate structure.

[0117] Continue to refer to Figure 4 , annealing the semiconductor structure.

[0118] Specifically, the stress and defects inside and between the first gate dielectric layer 310 and the first gate dielectric extension 330 can be eliminated through the annealing process, thereby improving the density and uniformity of the first gate structure.

[0119] Reference Figure 5 , forming a first gate extension portion 340.

[0120] The first gate extension 340 covers the surface of the first gate body 320 and the surface of the first gate dielectric layer 310 .

[0121] In some embodiments, the first gate extension 340 further covers the surface of the first gate dielectric extension 330 , and one end of the first gate extension 340 away from the second gate structure is located above the drift region 120 .

[0122] Specifically, the end of the first gate extension 340 away from the second gate structure can introduce an electric field peak in the substrate 100 below the first gate dielectric extension 330 , further increasing the pressure-bearing ratio of the substrate 100 .

[0123] In some embodiments, the first gate extension 340 is made of the same material as the first gate body 320 .

[0124] Reference Figure 6 , a deep well doping region 110 is formed in the substrate 100 .

[0125] The doping type of the deep well doping region 110 is different from that of the substrate 100 .

[0126] In some embodiments, the deep well doping region 110 is spaced apart from the first gate structure, the depth of the deep well doping region 110 is greater than the depth of the first gate structure, and the deep well doping region 110 is adjacent to the second gate structure.

[0127] Specifically, the deep well doped region 110 is used to connect to the conduction channel controlled by the second gate structure.

[0128] Continue to refer to Figure 6 , a drift region 120 is formed in the substrate 100 .

[0129] In some embodiments, the drift region 120 has a different doping type than the substrate 100 .

[0130] In some embodiments, the second gate structure is spaced apart from the drift region 120 .

[0131] In some embodiments, the first gate dielectric extension 330 is located in the drift region 120 .

[0132] One end of the first gate dielectric extension 330 away from the first gate dielectric layer 310 is located in the drift region 120 .

[0133] Specifically, the end of the first gate dielectric extension 330 located in the drift region 120 can introduce an electric field peak in the drift region 120, optimize the electric field distribution of the drift region 120, and increase the pressure-bearing ratio of the drift region 120, thereby improving the breakdown voltage of the semiconductor structure.

[0134] Furthermore, one end of the first gate extension 340 away from the second gate structure covers the surface of the first gate dielectric extension 330 and is located above the drift region 120 .

[0135] Specifically, one end of the first gate extension 340 away from the second gate structure is located above the drift region 120 , which can introduce an electric field spike in the drift region 120 below the first gate dielectric extension 330 , further increasing the pressure-bearing ratio of the drift region 120 .

[0136] In some embodiments, the deep well doped region 110 is adjacent to the second gate structure and the drift region 120 , respectively, wherein the doping type of the deep well doped region 110 is consistent with that of the drift region 120 .

[0137] Specifically, the deep well doped region 110 can be connected to a conduction channel controlled by the second gate structure below the first gate structure by being adjacent to the second gate structure and the drift region 120 respectively.

[0138] Furthermore, the doping concentration of the deep well doping region 110 is higher than that of the drift region 120 .

[0139] Specifically, this can reduce the resistance of the conduction channel formed in the deep well doping region 110 , thereby further reducing the conduction resistance of the semiconductor structure.

[0140] Continue to refer to Figure 6 , a body region 130 is formed in the substrate 100 .

[0141] The body region 130 and the drift region 120 have different doping types and are suitable for forming a PN junction.

[0142] In some embodiments, the body region 130 is adjacent to the second gate structure and the drift region 120 , respectively. The body region 130 covers the deep well doping region 110 , and has a doping type different from that of the deep well doping region 110 .

[0143] Specifically, the body region 130 may separate the second gate structure and the drift region 120 , and the depth of the conduction channel controlled by the second gate structure is greater than the depth of the body region 130 .

[0144] In some embodiments, a portion of the first gate structure is located within the body region 130 .

[0145] Part of the first gate structure is a first gate dielectric layer 310 and a first gate body 320 . One end of the first gate dielectric layer 310 adjacent to the second gate structure is located in the body region 130 . One end of the first gate body 320 adjacent to the second gate structure is located in the body region 130 .

[0146] Specifically, a conducting channel of the semiconductor structure is formed in the body region 130 between adjacent first gate structures, and the conducting channel is controlled by the first gate structure.

[0147] In some embodiments, the drift region 120 and the body region 130 may be formed in various orders. For example, the drift region 120 may be formed before the body region 130 . For example, the drift region 120 may be formed after the body region 130 .

[0148] Reference Figure 7 , a source region 140 and a drain region 150 are formed in the substrate 100 .

[0149] Among them, the source region 140 is located in the body region 130, and the doping type is different from that of the body region 130; the drain region 150 is located in the drift region 120, the doping type of the drain region 150 is consistent with that of the drift region 120, and the doping concentration is greater than that of the drift region 120, and the source region 140 and the drain region 150 are located on both sides of the first gate structure.

[0150] In some embodiments, one end of the first gate body 320 away from the source region 140 is located in the drift region 120 .

[0151] In some embodiments, one end of the first gate body 320 away from the source region 140 is located in the body region 130 .

[0152] It should be noted that the end of the first gate dielectric extension 330 away from the first gate dielectric layer 310 is the end of the first gate dielectric extension 330 adjacent to the drain region 150; the side of the first gate dielectric layer 310 away from the second gate structure is the side of the first gate dielectric layer 310 adjacent to the drain region 150; and the end of the first gate extension 340 away from the second gate structure is the end of the first gate extension 340 adjacent to the drain region 150.

[0153] In some embodiments, the source region 140 and the drain region 150 may be formed in various orders. For example, the drain region 150 may be formed during the process of forming the source region 140. For example, the source region 140 may be formed after the drain region 150.

[0154] Continue to refer to Figure 7 , an extraction region 160 is formed in the source region 140 .

[0155] The bottom surface of the extraction region 160 covers the body region 130 , and the doping type of the extraction region 160 is consistent with that of the body region 130 , and the doping concentration of the extraction region 160 is greater than that of the body region 130 .

[0156] Specifically, when the semiconductor structure is working, there are accumulated charges in the body region 130. By setting the extraction region 160, the accumulated charge in the body region 130 can be reduced, thereby reducing the influence of the accumulated charge on the electrical performance of the semiconductor structure, for example, the influence on electrical performance parameters such as on-resistance and breakdown voltage.

[0157] In some embodiments, a source region 140 is provided between the extraction region 160 and the second gate structure, and a source region 140 is provided between the extraction region 160 and the first gate structure.

[0158] Reference Figure 8 , there is a distance d1 between each first gate dielectric extension 330 and the drain region 150 .

[0159] In some embodiments, the interval d1 corresponding to at least one first gate dielectric extension 330 is different from the interval d1 corresponding to other first gate dielectric extensions 330 .

[0160] Furthermore, the intervals d1 corresponding to adjacent first gate dielectric extensions 330 are different.

[0161] Specifically, this can increase the distance between the ends of adjacent first gate dielectric extensions 330 , thereby reducing the intensity of superposition of electric field spikes at the ends of the first gate dielectric extensions 330 , and further reducing the probability of breakdown at the ends of the first gate dielectric extensions 330 .

[0162] In some embodiments, the intervals d1 corresponding to the first gate dielectric extensions 330 are consistent.

[0163] In some embodiments, each first gate extension 340 has a distance d2 from the drain region 150 , and the distance d2 corresponding to at least one first gate extension 340 is different from the distance d2 corresponding to other first gate extensions 340 .

[0164] Furthermore, the intervals d2 corresponding to adjacent first gate extensions 340 are different.

[0165] Specifically, this can increase the spacing between the ends of adjacent first gate extensions 340 , thereby reducing the intensity of the superposition of electric field spikes at the corresponding position of the drift region 120 below the end of the first gate extension 340 , and further reducing the probability of breakdown at the end of the first gate dielectric extension 330 .

[0166] In some embodiments, the intervals d2 corresponding to the first gate extensions 340 are consistent.

[0167] In some embodiments, the intervals d3 between adjacent first gate structures are different.

[0168] The longer the length L1 of the current first gate structure is, the smaller the distance d3 between the current first gate structure and the adjacent first gate structure is; the shorter the length L1 of the current first gate structure is, the larger the distance d3 between the current first gate structure and the adjacent first gate structure is.

[0169] Specifically, when the same voltage is applied, the longer the length L1 of the first gate structure is, the smaller the thickness of the conductive channel formed on the surface of the first gate structure is, and the shorter the length L1 of the first gate structure is, the thicker the conductive channel formed on the surface of the first gate structure is. By adjusting the spacing d3 of adjacent first gate structures based on the length L1 of the first gate structure, the size of the semiconductor structure can be reduced while ensuring the thickness of the conductive channel.

[0170] Combined with reference Figure 7 , Figure 8 as well as Fig. 9 In a specific example, the source region 140 is located between the first gate structure and the second gate structure, and is adjacent to the first gate structure and the second gate structure respectively, the depth of the bottom surface of the source region 140 is less than the depth of the deep well doping region 110, and the source region 140 and the deep well doping region 110 are spaced apart.

[0171] Specifically, when a voltage is applied to the first gate structure, a conducting channel C1 controlled by the first gate structure is formed in the region between adjacent first gate structures, and the conducting channel C1 and the drift region 120 are connected to the source region 140 and the drain region 150. When a voltage is applied to the second gate structure, a conducting channel C2 perpendicular to the surface direction of the substrate 100 is formed on the surface of the body region 130 adjacent to the second gate structure below the source region 140, and the conducting channel C2 connects the source region 140 and the deep well doped region 110, which means that the above-mentioned arrangement can increase the number of conducting channels in the semiconductor structure, thereby further reducing the on-resistance of the semiconductor structure.

[0172] It should be noted that the cross-sectional area of ​​the conduction channel C1 formed between adjacent first gate structures is related to the depth of the conduction channel C1 formed, and the depth of the conduction channel depends on the depth h1 of the first gate structure in the substrate 100. Therefore, the cross-sectional area of ​​the conduction channel C1 between the first gate structures can be adjusted by adjusting the depth h1 of the first gate structure in the substrate 100. For example, increasing the depth h1 of the first gate structure in the substrate 100 can increase the cross-sectional area of ​​the conduction channel C1 between the first gate structures, thereby reducing the on-resistance of the semiconductor structure.

[0173] In an embodiment of the present invention, a semiconductor structure can also be provided, in combination with reference to Figures 2 to 9 The semiconductor structure may include: a substrate 100, a plurality of first gate structures, a drift region 120, a body region 130, a source region 140 and a drain region 150, wherein the plurality of first gate structures are arranged at intervals on the substrate 100; the drift region 120 is located in the substrate 100; the body region 130 is located in the drift region 120 and is adjacent to the drift region 120, and a portion of the first gate structure is located in the body region 130; the source region 140 is located in the body region 130; the drain region 150 is located in the drift region 120, and the source region 140 and the drain region 150 are located on both sides of the first gate structure.

[0174] In some embodiments, the surface of the substrate 100 has a first groove 301; the first gate structure includes: a first gate dielectric layer 310, the first gate dielectric layer 310 covers the side wall surface and the bottom surface of the first groove 301; a first gate body 320, the first gate body 320 is located in the first groove 301; a first gate extension 340, the first gate extension 340 covers the first gate body 320 and the surface of the first gate dielectric layer 310.

[0175] Furthermore, the first gate structure also includes: a first gate dielectric extension 330 , which is adjacent to the first gate dielectric layer 310 and located on a side of the first gate dielectric layer 310 adjacent to the drain region 150 , and one end of the first gate dielectric extension 330 adjacent to the drain region 150 is located in the drift region 120 .

[0176] In some embodiments, a distance d1 is provided between the first gate dielectric extension 330 of each first gate structure and the drain region 150 , wherein the distances d1 corresponding to adjacent first gate structures are different.

[0177] In some embodiments, the first gate extension 340 further covers the first gate dielectric extension 330 , and an end of the first gate extension 340 adjacent to the drain region 150 is located above the drift region 120 .

[0178] Furthermore, the distances d2 between the first gate extensions 340 and the drain regions 150 of adjacent first gate structures are different.

[0179] In some embodiments, a second trench 201 is provided on the surface of the substrate 100, the second trench 201 is located on a side of the source region 140 away from the drain region 150, and the depth of the bottom of the second trench 201 is greater than the depth of the bottom surface of the source region 140, and the second trench 201 is adjacent to the source region 140; the semiconductor structure also includes a second gate structure, the second gate structure includes: a second gate dielectric layer 210 and a second gate body 220, the second gate dielectric layer 210 is located on the sidewall and bottom surface of the second trench 201, and the second gate body 220 is located in the second trench 201.

[0180] In some embodiments, the semiconductor structure further includes: a deep well doping region 110, the deep well doping region 110 is located in the substrate 100; the doping type of the deep well doping region 110 is consistent with that of the drift region 120, and the doping concentration is greater than that of the drift region 120, and the deep well doping region 110 is adjacent to the second gate structure and the drift region 120 respectively; the body region 130 is different from the doping type of the deep well doping region 110, and the body region 130 covers the deep well doping region 110, and the source region 140 is spaced apart from the deep well doping region 110.

[0181] In some embodiments, the semiconductor structure further includes: an extraction region 160 , the extraction region 160 is located in the source region 140 , the bottom surface of the extraction region 160 covers the body region 130 , the doping type of the extraction region 160 is consistent with that of the body region 130 , and the doping concentration is greater than that of the body region 130 .

[0182] It should be noted that for the principle, specific implementation and beneficial effects of the semiconductor structure, please refer to the previous article and Figures 2 to 9 The description related to the method for forming the semiconductor structure shown is not repeated here.

[0183] It should be noted that the semiconductor structure in the embodiment of the present invention can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure in the embodiment of the present invention, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0184] It is understandable that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0185] It is understood that the "multiple" mentioned herein refers to two or more than two. The first, second, etc. descriptions in the embodiments of the present application are only used for illustration and distinction of the described objects, and have no order, nor do they represent any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0186] It can be understood that the above describes multiple implementation schemes provided by the embodiments of the present invention, and the various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as the implementation schemes disclosed and open to the public by the present invention.

[0187] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of first gate structures, wherein the plurality of first gate structures are disposed on the substrate at intervals; forming a drift region and a body region in the substrate, wherein the drift region is adjacent to the body region, and a portion of the first gate structure is located in the body region; forming a source region and a drain region in the substrate, wherein the source region is located in the body region, the drain region is located in the drift region, and the source region and the drain region are located on both sides of the first gate structure; Before forming a plurality of first gate structures, the method further includes: Etching a first groove on the surface of the substrate; A plurality of first gate structures are formed, including: A first gate dielectric layer covering the first gate structure on the sidewall surface and the bottom surface of the first trench; Filling the first trench to form a first gate body of the first gate structure; A first gate extension portion covering the first gate structure on the surface of the first gate body and the first gate dielectric layer; Before etching the substrate surface to form the first groove, the method further comprises: Etching a second groove on the surface of the substrate, the second groove is located on a side of the source region away from the drain region, the depth of the bottom of the second groove is greater than the depth of the bottom surface of the source region, and the second groove is adjacent to the source region; In the process of forming the first gate structure, the method further includes: A second gate dielectric layer covering the second gate structure on the sidewall surface and the bottom surface of the second trench; The second trench is filled to form a second gate body of the second gate structure to obtain the second gate structure.

2. The forming method according to claim 1, characterized in that: Before covering the first gate extension, the method further includes: Performing ion implantation on the substrate to form a first gate dielectric extension of the first gate structure; The first gate dielectric extension is adjacent to the first gate dielectric layer and is located on a side of the first gate dielectric layer adjacent to the drain region, and one end of the first gate dielectric extension adjacent to the drain region is located in the drift region.

3. The forming method according to claim 2, characterized in that: Before covering the first gate extension, the method further includes: The semiconductor structure is subjected to annealing treatment.

4. The forming method according to claim 2, characterized in that: There is a distance between the first gate dielectric extension portion of each first gate structure and the drain region, wherein the distances corresponding to adjacent first gate structures are different.

5. The forming method according to claim 2, characterized in that: The first gate extension also covers the first gate dielectric extension, and an end of the first gate extension adjacent to the drain region is located above the drift region.

6. The forming method according to claim 5, characterized in that: The distances between the first gate extensions of adjacent first gate structures and the drain region are different.

7. The forming method according to claim 6, characterized in that: Before forming the body region in the substrate, the method further comprises: forming a deep well doping region in the substrate, wherein the doping type of the deep well doping region is consistent with that of the drift region and the doping concentration is greater than that of the drift region, and the deep well doping region is adjacent to the second gate structure and the drift region respectively; The body region and the deep well doping region have different doping types, and the body region covers the deep well doping region, and the source region and the deep well doping region are spaced apart.

8. The forming method according to claim 1, characterized in that: Also includes: An extraction region is formed in the source region, the bottom surface of the extraction region covers the body region, the doping type of the extraction region is consistent with that of the body region, and the doping concentration of the extraction region is greater than that of the body region.

9. A semiconductor structure, characterized in that: include: substrate; A plurality of first gate structures, wherein the plurality of first gate structures are disposed on the substrate at intervals; a drift region, the drift region being located within the substrate; a body region, the body region being located in the drift region and adjacent to the drift region, wherein a portion of the first gate structure is located in the body region; a source region, the source region being located within the body region; a drain region, the drain region being located in the drift region, the source region and the drain region being located at two sides of the first gate structure; The substrate surface has a first groove; The first gate structure comprises: a first gate dielectric layer, the first gate dielectric layer covering the sidewall surface and the bottom surface of the first trench; a first gate body, the first gate body being located in the first trench; a first gate extension portion, wherein the first gate extension portion covers the first gate body and a surface of the first gate dielectric layer; The first gate structure further includes: a first gate dielectric extension portion, the first gate dielectric extension portion being adjacent to the first gate dielectric layer and being located at a side of the first gate dielectric layer adjacent to the drain region, and an end of the first gate dielectric extension portion adjacent to the drain region being located in the drift region; The substrate surface has a second groove, the second groove is located at a side of the source region away from the drain region, the depth of the second groove bottom is greater than the depth of the bottom surface of the source region, and the second groove is adjacent to the source region; The semiconductor structure further includes a second gate structure, wherein the second gate structure includes: A second gate dielectric layer, wherein the second gate dielectric layer is located on the sidewalls and bottom surface of the second trench; A second gate body is located in the second trench.

10. The semiconductor structure according to claim 9, characterized in that: There is a distance between the first gate dielectric extension portion of each first gate structure and the drain region, wherein the distances corresponding to adjacent first gate structures are different.

11. The semiconductor structure according to claim 9, characterized in that: The first gate extension also covers the first gate dielectric extension, and an end of the first gate extension adjacent to the drain region is located above the drift region.

12. The semiconductor structure according to claim 11, characterized in that: The distances between the first gate extensions of adjacent first gate structures and the drain region are different.

13. The semiconductor structure according to claim 9, characterized in that: Also includes: A deep well doped region, wherein the deep well doped region is located in the substrate; The doping type of the deep well doping region is consistent with that of the drift region, and the doping concentration is greater than that of the drift region, and the deep well doping region is adjacent to the second gate structure and the drift region respectively; The body region and the deep well doping region have different doping types, and the body region covers the deep well doping region. The source region and the deep well doping region are spaced apart.

14. The semiconductor structure according to claim 9, characterized in that: Also includes: An extraction region, wherein the extraction region is located in the source region, a bottom surface of the extraction region covers the body region, a doping type of the extraction region is consistent with that of the body region, and a doping concentration is greater than that of the body region.

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