MIM capacitors and their manufacturing methods

Abstract

This invention provides a MIM capacitor and its manufacturing method. Before etching the second intermetallic dielectric layer to form the first and second openings, a buffer dielectric layer is deposited on the second intermetallic dielectric layer and its top surface is planarized. This provides a safer process window and ensures a stable upper electrode metal line thickness after filling the first and second openings with metal and planarizing the top surface. This solves the problem of bridging between the lower electrode metal line and surrounding metal lines caused by metal residue due to process limitations, and also addresses the problem of inaccurate control of the upper electrode metal line resistance due to uncontrollable upper electrode metal line thickness (e.g., excessively thin thickness), ultimately improving device reliability. Furthermore, the upper electrode is led out through the upper electrode metal line, eliminating the need for corresponding through-holes, simplifying the process and reducing contact resistance.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a MIM capacitor and its manufacturing method. Background Technology

[0002] Capacitors have wide applications in integrated circuits. In current CMOS (Complementary Metal-Oxide Semiconductor) processes and eFRAM ferroelectric memory processes, the industry commonly uses MIM (Metal-Insulator-Metal) capacitor structures manufactured through BEOL (Backend of Line) processes.

[0003] Please refer to Figure 1 The MIM capacitor structure in this MIM capacitor typically includes a lower electrode 11, an upper electrode 13, and a dielectric layer 12 between them (the material of which is oxide, silicon nitride SiN, ferroelectric material, or high-k material, etc.). The upper electrode 13 is led out through the upper electrode lead-out structure above it (i.e., upper through-hole 14a and upper electrode metal line 15a), and the lower electrode 11 is led out through the lower electrode lead-out structure above it (i.e., through-hole 14b and metal line 15b).

[0004] However, current MIM capacitors suffer from problems such as bridging between the lower plate metal wire and the surrounding metal wire, and the inability to precisely control the resistance Rs of the upper plate metal wire, which affect the reliability of the device. Summary of the Invention

[0005] The purpose of this invention is to provide a MIM capacitor device and its manufacturing method, which can provide a safer process window, thereby solving problems such as bridging between the lower electrode metal line and the surrounding metal lines, and the inability to accurately control the resistance Rs of the upper electrode metal line, thus improving the reliability of the device.

[0006] To achieve the above objectives, the present invention provides a method for manufacturing a MIM capacitor, which includes, but is not limited to, the following steps:

[0007] A substrate is provided on which a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer are sequentially deposited.

[0008] The lower electrode layer is etched to stop the etching layer, and the upper electrode layer and capacitor dielectric layer are etched to form the upper electrode layer;

[0009] The lower electrode layer around the upper electrode is etched to form the lower electrode. The lower electrode, the upper electrode, and the capacitor dielectric layer sandwiched between them together constitute the MIM capacitor structure.

[0010] A second metal interlayer dielectric layer and a buffer dielectric layer are sequentially deposited conformally on the MIM capacitor structure and its surrounding substrate, and the top surface of the buffer dielectric layer is planarized.

[0011] A first opening and a second opening are formed respectively. The first opening penetrates the buffer medium layer and the second metal interlayer medium layer to expose a portion of the top surface of the lower electrode plate. The second opening penetrates the buffer medium layer and the second metal interlayer medium layer to expose a portion of the top surface of the upper electrode plate.

[0012] Metal is deposited and the top surface is planarized to form a lower electrode lead-out structure filling the first opening and an upper electrode lead-out structure filling the second opening.

[0013] Optionally, the buffer medium layer is made of a different material than the second metal interlayer medium layer, and both are removed after the deposited metal is planarized.

[0014] Optionally, the lower part of the first opening is a first through hole that aligns with and exposes a portion of the top surface of the lower electrode plate, and the upper part of the first opening is a first groove that connects to the first through hole. The lower electrode plate lead-out structure includes, but is not limited to, a plug filled in the first through hole and a lower electrode plate metal wire filled in the first groove. The second opening is a second groove that aligns with and exposes a portion of the top surface of the upper electrode plate, and the upper electrode plate lead-out structure includes, but is not limited to, an upper electrode plate metal wire filled in the second groove.

[0015] Optionally, the steps of forming the first opening and the second opening include, but are not limited to:

[0016] The buffer dielectric layer and the second metal interlayer dielectric layer around the upper electrode are etched sequentially to form the first through hole;

[0017] Using the upper electrode layer as the etching stop layer, the buffer dielectric layer and the second metal interlayer dielectric layer are etched sequentially to simultaneously form the first trench and the second trench.

[0018] Optionally, the combined thickness of the capacitor dielectric layer and the upper electrode plate matches the height of the first through hole below the first trench.

[0019] Optionally, the substrate further comprises a first intermetallic dielectric layer and a lower metal interconnect formed in the first intermetallic dielectric layer; while forming the first via, a second via is also formed, aligned with and exposing a portion of the top surface of the lower metal interconnect; while forming the first trench and the second trench, a third trench is also formed, aligned with and communicating with the second via; while forming the lower electrode lead-out structure and the upper electrode lead-out structure, an upper metal interconnect filled in the third trench and a plug located between the upper metal interconnect and the lower metal interconnect are also formed together.

[0020] Optionally, before depositing the lower electrode layer on the substrate, a first metal barrier layer is deposited on the first metal interlayer dielectric layer and the lower metal interconnect; before conformally depositing the second metal interlayer dielectric layer, a second metal barrier layer is conformally deposited on the surface of the MIM capacitor structure and the first metal barrier layer surrounding it.

[0021] Based on the same inventive concept, the present invention also provides a MIM capacitor device, which includes, but is not limited to:

[0022] A substrate, wherein a first metal interlayer dielectric layer and a lower metal interconnect formed therein are formed;

[0023] The MIM capacitor structure includes a lower electrode plate, a capacitor dielectric layer, and an upper electrode plate sequentially formed on a portion of the top surface of the first intermetallic dielectric layer.

[0024] A second intermetallic dielectric layer with a flat top surface is formed on the first intermetallic dielectric layer surrounding the MIM capacitor structure. The second intermetallic dielectric layer has a first through-hole, a second through-hole, a first trench, a second trench, and a third trench. The first through-hole is aligned with and exposes a portion of the top surface of the lower electrode plate. The second through-hole is aligned with and exposes a portion of the top surface of the lower metal interconnect. The first trench is aligned with and connects to the first through-hole. The second trench is aligned with and exposes a portion of the top surface of the upper electrode plate. The third trench is aligned with and connects to the second through-hole.

[0025] The lower electrode metal wire is filled in the first groove and electrically connected to the lower electrode through a plug filled in the first through hole;

[0026] The upper electrode metal wire is filled in the second trench and electrically connected to the upper electrode plate;

[0027] The upper metal interconnect is filled in the third trench and electrically connected to the lower metal interconnect through a plug filled in the second through hole.

[0028] Optionally, the first through-hole and the second through-hole are formed by the same through-hole etching process, and the lower electrode metal line, the upper electrode metal line and the upper metal interconnect line are formed by the same metal deposition process.

[0029] Optionally, the material of the first intermetallic dielectric layer or the second intermetallic dielectric layer includes, but is not limited to, a low-K dielectric with a dielectric constant K less than 3; the material of the capacitor dielectric layer includes, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric with a dielectric constant K greater than 7, and a ferroelectric dielectric material; the material of the upper electrode or the lower electrode includes, but is not limited to, at least one of Ti, TiN, Ta, TaN, Al, and W; and the material of the lower metal interconnect or the upper metal interconnect includes, but is not limited to, at least one of Cu, W, Al, and Au.

[0030] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0031] 1. Because a buffer dielectric layer is deposited on the second metal interlayer dielectric layer and its top surface is planarized before etching the second metal interlayer dielectric layer to form the first and second openings, a safer process window is provided to ensure the process effect of lithography and etching when manufacturing the first and second openings. On the other hand, it can ensure that after filling the first and second openings with metal and planarizing the top surface, a stable upper electrode metal line thickness can be maintained. This solves the problem of metal residue caused by directly depositing metal on the second metal interlayer dielectric layer due to process limitations, which leads to bridging between the lower electrode metal line and the surrounding metal lines. It also solves the problem of the resistance Rs of the upper electrode metal line being unable to be precisely controlled due to the uncontrollable thickness of the upper electrode metal line (e.g., too thin). Ultimately, this improves the reliability of MIM capacitors.

[0032] 2. The upper electrode is led out through the upper electrode metal wire, which eliminates the through hole between the upper electrode metal wire and the upper electrode in the prior art, making the process simpler and the resistance Rs of the upper electrode metal wire more stable and lower.

[0033] 3. The trenches used to form the upper and lower electrode metal lines are formed simultaneously with the corresponding trenches used to form the upper metal interconnects in the subsequent process, simplifying the process steps. Attached Figure Description

[0034] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0035] Figure 1 This is a cross-sectional structural diagram of an existing MIM capacitor device.

[0036] Figure 2 It is a kind of having Figure 1 The diagram shows a cross-sectional structure of the device in the manufacturing method of the MIM capacitor.

[0037] Figure 3A yes Figure 2 The manufacturing method of the MIM capacitor shown addresses the issue of the upper electrode being too thin after the filled copper is planarized.

[0038] Figure 3B yes Figure 2 The manufacturing method of the MIM capacitor shown addresses the issue of an excessively thick upper electrode plate after the copper filler is planarized.

[0039] Figure 4 This is a schematic diagram of the manufacturing process of a MIM capacitor device according to a specific embodiment of the present invention.

[0040] Figure 5 This is a schematic cross-sectional view of the device structure in the manufacturing method of the MIM capacitor device according to a specific embodiment of the present invention.

[0041] The reference numerals in each of the attached figures are as follows:

[0042] 10a, 20a, first intermetallic dielectric layer; 10b, 20b, lower metal interconnect; 10c, 20c, first metal barrier layer; 11, 21, lower electrode; 11a, 21a, lower electrode layer; 12, 22, capacitor dielectric layer; 13a, 23a, upper electrode layer; 14a, 14b, 14c, via; 15a, 15b, 15c, trench; 16, 26, second metal barrier layer; 17, 27a, second intermetallic dielectric layer; 18a, 28a, upper electrode metal line; 18b, 28b, lower electrode metal line; 18c, 28c, upper metal interconnect; 24b, first via; 24c, second via; 25a, second trench; 25b, first trench; 25c, third trench; 27b, buffer dielectric layer. Detailed Implementation

[0043] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0044] As described in the background section, current MIM capacitors suffer from problems such as bridging between the lower plate metal wire and surrounding metal wires, and the inability to precisely control the resistance Rs of the upper plate metal wire, affecting device reliability. The following, in conjunction with the appendix... Figures 1 to 3B The shortcomings of the prior art are further explained in detail by the existing manufacturing methods of MIM capacitors.

[0045] Specifically, an existing type has such Figure 1 The manufacturing method of the MIM capacitor shown generally includes, but is not limited to, the following steps:

[0046] S1.1, please refer to Figure 2 In (A), a first metal interlayer dielectric layer 10a (which may be a low dielectric constant material) and a lower metal interconnect 10b (which may be a material such as copper Cu) are formed through the fabrication process of a certain layer (e.g., Mn layer) of the back-end process BEOL. The lower metal interconnect 10b is specifically formed by filling the trench of the first metal interlayer dielectric layer 10a with a metal material such as copper Cu and then performing chemical mechanical polishing (CMP).

[0047] S1.2, please continue to refer to it. Figure 2In (A), a first metal barrier layer 10c, a lower electrode layer 11a, a capacitor dielectric layer 12, and an upper electrode layer 13a are sequentially deposited on the first metal interlayer dielectric layer 10a and the lower metal interconnect 10b using any suitable deposition process.

[0048] S1.3, please continue to refer to it. Figure 2 In step (B), a photoresist layer (not shown) is coated on the upper electrode layer 13a, and the photoresist layer is exposed and developed to define the layout of the upper electrode 13 of the MIM capacitor structure. Using the developed photoresist layer as a mask and the lower electrode layer 11 as an etch stop layer, the upper electrode layer 13a and the capacitor dielectric layer 12 are etched. The etching stops at the surface or corresponding depth of the lower electrode layer 11a, thereby transferring the layout of the upper electrode to the upper electrode layer 13a and the capacitor dielectric layer 12 to form the upper electrode 13 of the MIM capacitor structure.

[0049] S1.4, please continue to refer to it. Figure 2 In step (C), the aforementioned photoresist layer is removed, and a new photoresist layer is applied. This new photoresist layer is then exposed and developed to define the layout of the lower electrode 11 of the MIM capacitor structure. Using the developed photoresist layer as a mask and the first metal barrier layer 10c as an etch stop layer, the lower electrode layer 11a surrounding the upper electrode 13 is etched. The etching stops at the surface or a corresponding depth of the first metal barrier layer 10c, thereby transferring the layout of the lower electrode 11 to the lower electrode layer 11a. The remaining lower electrode layer 11a serves as the lower electrode 11 of the MIM capacitor structure, having a portion extending beyond the edge of the remaining upper electrode 13 for subsequent external lower electrode lead-out structures. At this point, a MIM capacitor structure is formed, consisting of the upper electrode 13, the lower electrode 11, and the capacitor dielectric layer 12 sandwiched between them. The first metal barrier layer 10c, the lower electrode 11, and the upper electrode 13 form continuous steps.

[0050] S1.5, please refer to Figure 2 In (D), a second metal barrier layer 16 and a second metal interlayer dielectric layer 17 are deposited sequentially. The second metal barrier layer 16 conformally covers the surface of the first metal barrier layer 10c, the lower electrode 11, the capacitor dielectric layer 12 and the upper electrode 13, and the second metal interlayer dielectric layer 17 conformally covers the surface of the second metal barrier layer 16.

[0051] S1.6, please continue to refer to it. Figure 2In step (D), through the fabrication process (including photolithography and etching) of the via of another layer (e.g., Mn+1 layer) of the metal interconnect structure in the back-end process BEOL, the second metal interlayer dielectric layer 17 is etched, and the etching stops in the second metal barrier layer 16, so as to form via 14a for leading out the upper electrode 13, via 14b for leading out the lower electrode 11, and via 14c for leading out the lower metal interconnect line 10b in the second metal interlayer dielectric layer 17.

[0052] S1.7, please refer to Figure 2 In step (E), through the fabrication process (including photolithography and etching) of the metal interconnect structure of another layer (e.g., Mn+1 layer) of the back-end process BEOL, the second metal interlayer dielectric layer 17 is etched to form a trench 15a for leading out the upper electrode 13, a trench 15b for leading out the lower electrode 11, and a trench 15c for leading out the lower metal interconnect line 10b in one pass on the top of the second metal interlayer dielectric layer 17.

[0053] S1.8, please continue to refer to it. Figure 2 (F) and Figures 3A-3B Through the fabrication process of another layer (e.g., Mn+1 layer) of the metal interconnect structure in the back-end process BEOL, a barrier seed layer (not shown) is deposited, and copper or other metal materials are filled into the vias 14a-14c and trenches 15a-15c by processes such as electroplating. The filled metal materials are then chemically and mechanically polished on top, thereby forming the upper electrode metal line 18a for leading out the upper electrode 13, the lower electrode metal line 18b for leading out the lower electrode 11, and the upper metal interconnect line 18c. The upper metal interconnect line 18c is electrically connected to the lower metal interconnect line 10b of the lower layer through the plug in the via 14c. The upper electrode metal line 18a and the plug in the via 14a constitute the upper electrode lead-out structure, and the lower electrode metal line 18b and the plug in the via 14b constitute the lower electrode lead-out structure.

[0054] The inventors discovered that the existing manufacturing method described above has the following drawbacks:

[0055] 1. After the second metal interlayer dielectric layer 17 is deposited conformally, its upper surface is uneven. After the photoresist is coated on the second metal interlayer dielectric layer 17 in step S1.6, the thickness of the photoresist will be uneven. As a result, when the photoresist is exposed to define the formation position of the vias 14a to 14c, it will seriously affect the process window of the photolithography exposure. It may cause the photoresist at some vias 14a to 14c to not be fully exposed, resulting in some vias not being formed, which may eventually cause device failure.

[0056] 2. The chemical mechanical polishing process on the top of the filled metal material in step S1.8 lacks sufficient process window. On the one hand, it can easily lead to the upper electrode metal line 18a being ground too thin or even completely worn away. Figure 3A As shown, this leads to the inability to precisely control the resistance Rs of the upper plate metal line 18a of the MIM capacitor; on the other hand, in order to retain a sufficiently thick upper plate metal line 18a, it is easy to generate metal material residue (e.g., Cu residue) at point P of the second metal interlayer dielectric layer 17, resulting in a bridge between the lower plate metal line 18b and the surrounding upper metal interconnect line 18c.

[0057] Based on this, the present invention provides a method for manufacturing a MIM capacitor. After forming the MIM capacitor structure, by optimizing the film stack covering the MIM capacitor structure, the upper plate metal interconnect of the MIM capacitor structure is defined by the metal trench process of the upper metal interconnect. After filling with metal (e.g., Cu) and CMP, a stable height of the upper plate metal line can be maintained in the MIM capacitor structure, thereby ensuring that the upper plate metal line has a stable resistance. At the same time, it solves the problem of inaccurate resistance control caused by preventing the metal line from being too thin. It also solves the problem of metal line bridging risk caused by the uneven steps on the top surface of the dielectric layer between metal layers after CMP and the metal residue at these steps.

[0058] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0059] Please refer to Figure 4 One embodiment of the present invention provides a method for manufacturing a MIM capacitor, which includes, but is not limited to, the following steps:

[0060] S2.1, A substrate is provided, on which a lower electrode layer, a capacitor dielectric layer and an upper electrode layer are sequentially deposited;

[0061] S2.2, etch the stop layer of the lower electrode layer, etch the upper electrode layer and the capacitor dielectric layer to form the upper electrode layer;

[0062] S2.3, Etch the lower electrode layer around the upper electrode to form a lower electrode. The lower electrode, the upper electrode, and the capacitor dielectric layer sandwiched between them together constitute a MIM capacitor structure.

[0063] S2.4, sequentially deposit the second metal interlayer dielectric layer and the buffer dielectric layer on the substrate surrounding the MIM capacitor structure, and planarize the top surface of the buffer dielectric layer;

[0064] S2.5, forming a first opening and a second opening respectively, the first opening penetrating the buffer medium layer and the second metal interlayer medium layer to expose a portion of the top surface of the lower electrode plate, and the second opening penetrating the buffer medium layer and the second metal interlayer medium layer to expose a portion of the top surface of the upper electrode plate;

[0065] S2.6, deposit metal and planarize the top surface to form a lower electrode lead-out structure filling the first opening and an upper electrode lead-out structure filling the second opening.

[0066] Please refer to Figure 5 In step S2.1 of (A), a substrate can be provided first. This substrate can be a substrate with a multilayer metal interconnect structure fabricated in the back-end process of integrated circuit manufacturing (BEOL). A certain metal interconnect Mn and a first inter-metal dielectric layer 20a have been fabricated. Hereinafter, the certain metal interconnect Mn is defined as the lower metal interconnect 20b. At least one trench (not marked) for filling the lower metal interconnect 20b is formed in the first inter-metal dielectric layer 20a. The material of the first inter-metal dielectric layer 20a can be a low-k dielectric with a dielectric constant lower than 3. Specifically, the lower metal interconnect 20b can be formed by filling the trenches of the first inter-metal dielectric layer 20a with a metal interconnect material such as copper (Cu) and then performing top surface planarization. The top surface planarization process is, for example, a chemical mechanical polishing (CMP) process.

[0067] Please continue to refer to this. Figure 5 In step S2.1, following any suitable deposition process, a first metal barrier layer 20c, a lower electrode layer 21a, a capacitor dielectric layer 22, and an upper electrode layer 23a are sequentially deposited on the first metal interlayer dielectric layer 20a and the lower metal interconnect 20b. The material of the lower metal interconnect 20b includes, but is not limited to, at least one of copper (Cu), tungsten (W), and gold (Au). The material of the capacitor dielectric layer 22 includes, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material with a dielectric constant K greater than 7, and a ferroelectric dielectric material; it can be a single layer or a multilayer stack of different materials. The high-K dielectric material includes, but is not limited to, at least one of hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, thallium oxide, and BaTiO3. The combined thickness of the capacitor dielectric layer 22 and the upper electrode layer needs to match the height of the first via formed for the lower electrode layer, thereby ensuring the first trench (used to fill the lower electrode metal line) in the subsequent step S2.5. Figure 5As shown in (F), 25b), the second trench (used to fill the upper electrode metal wire), Figure 5 As shown in (F), 25a) and the third trench (used to fill the upper metal interconnects, Figure 5 As shown in (F), 25c) is formed simultaneously. As an example, the thickness of the capacitor dielectric layer 22 is 10 nm to 100 nm. The upper electrode layer 23a and the lower electrode layer 21a can be formed using the same material, including but not limited to at least one material selected from Ti, TiN, Ta, TaN, Al, and W, or a stacked combination of multiple materials. The thicknesses of the upper electrode layer 23a and the lower electrode layer 21a can be 10 nm to 100 nm, and can be formed using deposition processes such as physical vapor deposition (PVD) or atomic layer deposition (ALD). The first metal barrier layer 20c and the capacitor dielectric layer 22 can be formed using deposition processes such as chemical vapor deposition (CVD). The first metal barrier layer 20c prevents metals such as copper in the lower metal interconnect 20b from moving or diffusing into the upper electrode layer 23a, lower electrode layer 21a, capacitor dielectric layer 22, and the subsequently formed second metal interlayer dielectric layer 27a during the formation of the MIM capacitor, thereby avoiding adverse effects on the performance of the MIM capacitor such as increased leakage current and reduced breakdown voltage. The material of the first metal barrier layer 20c can be an amorphous metal, including but not limited to TiN or TaN.

[0068] Please refer to Figure 5 In step (B), in step S2.2, firstly, a photoresist layer (not shown) is coated on the upper electrode layer 23a, and the photoresist layer is exposed and developed to define the layout of the upper electrode 23 of the MIM capacitor structure; then, the developed photoresist layer is used as a mask, and the lower electrode layer 21a is used as an etch stop layer to etch the upper electrode layer 23a and the capacitor dielectric layer 22. The etching stops at the surface or corresponding depth of the lower electrode layer 21a, thereby transferring the layout of the upper electrode 23 (i.e., the pattern in the developed photoresist layer) to the upper electrode layer 23a and the capacitor dielectric layer 22, thus forming the upper electrode 23.

[0069] Please continue to refer to this. Figure 5In step (B), in step S2.3, firstly, the photoresist layer is removed and a new photoresist layer is applied. The reapplied photoresist layer is then exposed and developed to define the layout of the lower electrode 21 of the MIM capacitor structure. Next, using the developed photoresist layer as a mask and the first metal barrier layer 20c as an etching stop layer, the lower electrode layer 21a surrounding the upper electrode 23 is etched. The etching stops at the surface or corresponding depth of the first metal barrier layer 20c, thereby transferring the layout of the lower electrode 21 to the lower electrode layer 21a. The remaining lower electrode layer 21a serves as the lower electrode 21 of the MIM capacitor structure. The lower electrode 21 has a portion extending relative to the edge of the upper electrode 23 for subsequent external lower electrode lead-out structures. At this point, the first metal barrier layer 20c, the lower electrode 21, and the upper electrode 23 form a continuous step, and the lower electrode 21, the upper electrode 23, and the remaining capacitor dielectric layer 22 sandwiched between them constitute the MIM capacitor structure.

[0070] Please refer to Figure 5In step (C), S2.4, firstly, a second metal barrier layer 26, a second metal interlayer dielectric layer 27a, and a buffer dielectric layer 27b are sequentially deposited using a suitable deposition process such as chemical vapor deposition (CVD). The second metal barrier layer 26 is relatively thin and conformally covers the exposed surfaces of the first metal barrier layer 20c, the lower electrode 21, the capacitor dielectric layer 22, and the upper electrode 23. The second metal barrier layer 26 increases the adhesion between the second metal interlayer dielectric layer 27a and the underlying structure. Furthermore, it prevents metals such as copper in the lower metal interconnects 20b, the upper electrode 23, the lower electrode 21, and subsequently formed metal wires and plugs from moving or diffusing between the corresponding dielectric or metal layers during the formation of the MIM capacitor, thereby avoiding adverse effects on the performance of the MIM capacitor, such as increased leakage current and reduced breakdown voltage. The material of the second metal barrier layer 26 can be an amorphous metal, including but not limited to TiN or TaN. The second intermetallic dielectric layer 27a conformally covers the exposed surface of the second metal barrier layer 26 and has a relatively thick thickness, sufficient to meet the requirements of the sum of the height of the vias and the corresponding trench depths to be formed subsequently. A buffer dielectric layer 27b conformally covers the exposed surface of the second intermetallic dielectric layer 27a, with a thickness sufficient to compensate for the height difference of the top surface of the corresponding region of the second intermetallic dielectric layer 27a, thus providing a flat top surface in subsequent fabrication. As an example, the buffer dielectric layer 27b is preferably made of a material with a large etching selectivity ratio to the second intermetallic dielectric layer 27a. For example, when the second intermetallic dielectric layer 27a is a low-K dielectric with a dielectric constant less than 3, the material of the buffer dielectric layer 27b can be a material with a dielectric constant K greater than 3.0 (e.g., silicon oxide or silicon oxynitride), with a thickness of approximately 30 nm to 300 nm. During the subsequent planarization of the metal layers used to fabricate the upper electrode metal lines, the buffer dielectric layer 27b is removed and does not remain in the final device structure.

[0071] It should be understood that the three-layer film, namely the second metal barrier layer 26, the second metal interlayer dielectric layer 27a, and the buffer dielectric layer 27b, can be made of any suitable material, and the deposition process of these three layers can be completed in the same deposition chamber or in different deposition chambers.

[0072] Please continue to refer to this. Figure 5In step S2.4, the top surface of the buffer dielectric layer 27b can be planarized using a chemical mechanical polishing (CMP) process. This planarization process needs to ensure that the dielectric layer on the top surface of the upper electrode plate 23 is thick enough (i.e., the stacking thickness of the second metal interlayer dielectric layer 27a and other films on the top surface of the upper electrode plate 23 is thick enough) to meet the required thickness of the upper electrode plate metal line formed in the subsequent step S2.6 for leading out the upper electrode plate 23. On the other hand, it makes the remaining buffer dielectric layer 27b as thin as possible on the top surface of the upper electrode plate 23, and makes the dielectric layer thickness on the lower electrode plate 21 and other areas as thin as possible (i.e., the stacking thickness of the buffer dielectric layer 27b and the second metal interlayer dielectric layer 27a and other films on the top surface of the lower electrode plate 21 is thin enough), thereby reducing the difficulty of the subsequent etching process of the vias on the lower electrode plate 21. Optionally, the top surface of the buffer dielectric layer 27b is planarized to expose the top surface of the second metal interlayer dielectric layer 27a above the top surface of the upper electrode plate 23.

[0073] Please refer to Figure 5 In step S2.5, firstly, through the fabrication process (including photolithography and etching) of the via of another layer (e.g., Mn+1 layer) of the metal interconnect structure in the back-end process BEOL, the buffer dielectric layer 27b and the second metal interlayer dielectric layer 27a above the lower metal interconnect line 20b in the corresponding area of ​​the lower electrode 21 and its periphery are etched. The etching stops in the second metal barrier layer 26, thereby forming the first via 24b for leading out the lower electrode 21 and the third via 24c for leading out the lower metal interconnect line 20b in one process. This process only defines the via of the metal interconnect structure of this layer (e.g., Mn+1 layer) and the via of the lower electrode 21 leading out the MIM capacitor structure, and does not define the via of the upper electrode 23 leading out the MIM capacitor structure. Furthermore, since the top surface of the buffer dielectric layer 27b is planarized in step S2.4, the top surface formed by the remaining buffer dielectric layer 27b and the second metal interlayer dielectric layer 27a is sufficiently flat. Therefore, the thickness of the photoresist coated in this step is uniform, and the photoresist at each via location can be fully exposed, thereby ensuring the reliable quality of each via formed.

[0074] Please refer to Figure 5In step S2.5, following the fabrication process (including photolithography and etching) of the metal interconnect structure of another layer (e.g., Mn+1 layer) of the back-end process BEOL, using the upper electrode 23 as the etching stop layer, the buffer dielectric layer 27b, the second metal interlayer dielectric layer 27b, the second metal barrier layer 26, and the second metal barrier layer 26 and the first metal barrier layer 20c at the bottom of the first via 24b and the second via 24c are etched, and the etching stops at the upper electrode 23. On the top surface of the upper electrode plate 23 or at a certain depth therein, a second trench 25a for leading out the upper electrode plate 23, a first trench 25b for leading out the lower electrode plate 21, and a third trench 25c for leading out the lower metal interconnect 20b are formed, such that the bottom of the first through hole 24b exposes the corresponding top surface of the lower electrode plate 21, the bottom of the second through hole 24c exposes the corresponding top surface of the lower metal interconnect 20b, and the second trench 25a exposes the corresponding top surface of the upper electrode plate 23. The first trench 25b is aligned with and connects to the first through hole 24b below it, thereby forming a first opening (unmarked); the second trench 25a is aligned with a portion of the top surface of the upper electrode plate 23, serving as a second opening (unmarked).

[0075] Obviously, in the manufacturing method of this embodiment, the first through hole 24b of the lower electrode plate 21 connecting the MIM capacitor structure is formed together with the through hole process of the upper interconnect metal structure in the multilayer metal interconnect structure, and the trenches required for the upper electrode plate 23 and the lower electrode plate 21 of the MIM capacitor structure are formed together with the trench process for manufacturing the metal interconnect lines of the upper interconnect metal structure.

[0076] Please refer to Figure 5 In step S2.6, (G) firstly, through the fabrication process of the metal interconnect structure of another layer (e.g., Mn+1 layer) of the back-end process BEOL, a barrier seed layer (not shown) is deposited, and then a metal material such as copper is deposited through processes such as electroplating. The deposited metal material not only fills the second trench 25a, but also fills the first through hole 24b and the first trench 25b connected to it, and at the same time fills the second through hole 24c and the third trench 25c connected to it.

[0077] Please refer to Figure 5In step S2.6, the deposited metal material is then planarized using processes such as chemical mechanical polishing. This forms a lower electrode metal line 28b for leading out the lower electrode 21 in the first trench 25b, an upper electrode metal line 28a for leading out the upper electrode 23 in the second trench 25a, and an upper metal interconnect line 28c for leading out the lower metal interconnect line 20b in the third trench 25c. The upper metal interconnect line 28c is electrically connected to the lower metal interconnect line 20b through a plug in the second through-hole 24c. The lower electrode metal line 28b is electrically connected to the lower electrode 21 through a plug in the first through-hole 24b, and the upper electrode metal line 28a is directly electrically connected to the upper electrode 23 without a plug. At this point, the lower electrode metal line 28b and the plug in the first through-hole 24b form a lower electrode lead-out structure filling the first opening (not marked in...). Figure 5 (in the middle), the upper electrode metal wire 28a serves as the upper electrode lead-out structure filled in the second opening (not marked in the middle). Figure 5 middle).

[0078] In the process of planarizing the top surface of the deposited metal material through chemical mechanical polishing (CMP), the remaining buffer dielectric layer 27b can be used to monitor the stopping point of the CMP process. Thus, while removing all the buffer dielectric layer 27b, the steps on the top of the second metal interlayer dielectric layer 27a are also removed. This ensures that the thickness of the remaining upper electrode metal wire above the top surface of the upper electrode 23 meets the requirements, thereby avoiding the problem of bridging between the lower electrode metal wire and other surrounding metal wires due to metal residue at the steps on the upper surface of the second metal interlayer dielectric layer 27a. It also avoids the problem of some metal wires bridging due to the upper electrode metal wire being too thick or the resistance of the upper electrode metal wire being unable to be accurately controlled due to the upper electrode metal wire being too thin.

[0079] It should also be understood that the orientation of the second trench 25a above the upper electrode plate 23 can be designed in conjunction with... Figure 2 It is consistent with 15a in (E), but since there is no plug between the upper electrode metal line 28a and the upper electrode 23 in the second trench 25a, the contact area between the two is greatly increased and the contact resistance between the two is reduced.

[0080] In summary, the manufacturing method of this embodiment firstly, by utilizing the deposition of a buffer dielectric layer and top surface planarization, a flat process window is provided for subsequent steps. This allows the trenches required for the upper electrode to be formed simultaneously with those required for the lower electrode and other locations, simplifying the process steps and avoiding the problem of excessively deep through-holes making metal filling difficult. Secondly, after the metal fills each trench and the top surface is planarized, the remaining buffer dielectric layer and the steps on the top of the second metal interlayer dielectric layer can be removed. This solves the problem of excessively thick upper electrode metal lines caused by process limitations, which hinders the second... The presence of metal residue at the steps on the upper surface of the dielectric layer between metal layers can cause problems such as metal wire bridging. This can also solve the problem that the resistance Rs of the upper electrode metal wire cannot be precisely controlled due to the excessive thinness of the upper electrode metal wire caused by process limitations. Furthermore, the upper electrode is led out only through the upper electrode metal wire, which simplifies the process and makes the resistance more stable. Moreover, for the capacitor plate, the contact resistance between the upper electrode metal wire and the upper electrode is much lower than that between the existing upper electrode and the plug in the through hole. Therefore, the contact resistance can be reduced, the parasitic effect of the MIM capacitor can be improved, and the performance of the MIM capacitor can be enhanced.

[0081] Based on the same inventive concept, one embodiment of the present invention also provides a MIM capacitor, which can be formed using any suitable manufacturing method, and is preferably formed using the manufacturing method of the MIM capacitor of the present invention. Please refer to... Figure 5 In (E) to (F) and (H), the MIM capacitor specifically includes, but is not limited to, the following structures:

[0082] A substrate in which a first metal interlayer dielectric layer 20a and a lower metal interconnect 20b formed in the first metal interlayer dielectric layer 20a are formed;

[0083] The MIM capacitor structure includes a lower electrode 21, a capacitor dielectric layer 22 and an upper electrode 23 sequentially formed on a portion of the top surface of the first metal interlayer dielectric layer 20a.

[0084] A second intermetallic dielectric layer 27a with a flat top surface is formed on the first intermetallic dielectric layer 20a surrounding the MIM capacitor structure. The second intermetallic dielectric layer 27a has a first through-hole 24b, a second through-hole 24c, a first trench 25b, a second trench 25a, and a third trench 25c. The first through-hole 24b is aligned with and exposes a portion of the top surface of the lower electrode plate 21. The second through-hole 24c is aligned with and exposes a portion of the top surface of the lower metal interconnect 20b. The first trench 25b is aligned with and connects to the first through-hole 24b. The second trench 25a is aligned with and exposes a portion of the top surface of the upper electrode plate 23. The third trench 25c is aligned with and connects to the second through-hole 24c.

[0085] The lower electrode metal wire 28b is filled in the first trench 25b and electrically connected to the lower electrode 21 through a plug (not marked) filled in the first through hole 24b. Optionally, the lower electrode metal wire 28b and the plug of the first through hole 24b are formed by the same metal deposition process, and the lower electrode metal wire 28b and the plug of the first through hole 24b constitute the lower electrode lead-out structure.

[0086] The upper electrode metal wire 28a is filled in the second trench 25a and electrically connected to the upper electrode 23, wherein the upper electrode metal wire 28a serves as an upper electrode lead-out structure for leading out the upper electrode 23.

[0087] The upper metal interconnect 28c is filled in the third trench 25c and electrically connected to the lower metal interconnect 20b through a plug filled in the second through hole 24c. The upper metal interconnect 28c, the lower metal interconnect 20b and the plug filled in the second through hole 24c constitute part of a multilayer metal interconnect structure.

[0088] Optionally, the first through-hole 24b and the second through-hole 24c are formed by the same through-hole etching process, the trenches containing the lower electrode metal line 28b, the upper electrode metal line 28a and the upper metal interconnect line 28c are formed by the same trench etching process, and the lower electrode metal line 28b, the upper electrode metal line 28a and the upper metal interconnect line 28c are formed by the same metal deposition process and CMP process.

[0089] Optionally, the material of the first intermetallic dielectric layer 20a or the second intermetallic dielectric layer 27a includes, but is not limited to, a low-K dielectric with a dielectric constant K less than 3; the material of the capacitor dielectric layer 22 includes, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric with a dielectric constant K greater than 7, and a ferroelectric dielectric material; the material of the upper electrode 232 or the lower electrode 21 includes, but is not limited to, at least one of Ti, TiN, Ta, TaN, Al, and W; and the material of the lower metal interconnect 20b or the upper metal interconnect 28c includes, but is not limited to, at least one of Cu, W, Al, and Au.

[0090] Optionally, a first metal barrier layer 20c may be sandwiched between the lower electrode 21 and the first intermetallic dielectric layer 20a, and a second metal barrier layer 26 may be sandwiched between the upper electrode 23 and the second intermetallic dielectric layer 27a. The first metal barrier layer 20c and the second metal barrier layer 26 may be made of the same material, for example, including but not limited to TiN or TaN. The first metal barrier layer 20c and the second metal barrier layer 26 can prevent the corresponding metals from moving and diffusing between the film layers, thus preventing adverse effects on the device performance.

[0091] In this embodiment of the MIM capacitor, the upper electrode lead-out structure omits through-holes, thus improving device performance through lower contact resistance between the upper electrode metal wire and the upper electrode. Furthermore, the thickness of the upper electrode metal wire is controllable, which avoids bridging issues between the lower electrode metal wire and surrounding metal wires caused by an excessively thick upper electrode metal wire, and also avoids uncontrollable resistance issues caused by an excessively thin upper electrode metal wire, thereby improving device reliability.

[0092] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a MIM capacitor, characterized in that, include: A substrate is provided on which a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer are sequentially deposited. Using the lower electrode layer as the etching stop layer, the upper electrode layer and the capacitor dielectric layer are etched to form the upper electrode layer; The lower electrode layer around the upper electrode is etched to form the lower electrode. The lower electrode, the upper electrode, and the capacitor dielectric layer sandwiched between them together constitute the MIM capacitor structure. A second metal barrier layer, a second metal interlayer dielectric layer, and a buffer dielectric layer are sequentially deposited on the MIM capacitor structure and its surrounding substrate. The material of the buffer dielectric layer is different from that of the second metal interlayer dielectric layer. The deposition thickness of the second metal interlayer dielectric layer is at least sufficient to meet the sum of the height of the vias to be formed and the corresponding trench depth. The deposition thickness of the buffer dielectric layer is at least sufficient to compensate for the height difference of the top surface of the corresponding region of the second metal interlayer dielectric layer. The top surface of the buffer medium layer is planarized; A first opening and a second opening are formed respectively. The first opening penetrates the buffer medium layer and the second metal interlayer medium layer to expose a portion of the top surface of the lower electrode plate. The second opening penetrates the buffer medium layer and the second metal interlayer medium layer to expose a portion of the top surface of the upper electrode plate. Metal is deposited and the top surface is planarized to remove the buffer medium layer and form a lower electrode lead-out structure filling the first opening and an upper electrode lead-out structure filling the second opening.

2. The manufacturing method as described in claim 1, characterized in that, The lower part of the first opening is a first through hole that aligns with and exposes a portion of the top surface of the lower electrode plate, and the upper part of the first opening is a first groove that connects to the first through hole. The lower electrode plate lead-out structure includes a plug filled in the first through hole and a lower electrode plate metal wire filled in the first groove. The second opening is a second groove that aligns with and exposes a portion of the top surface of the upper electrode plate, and the upper electrode plate lead-out structure includes an upper electrode plate metal wire filled in the second groove.

3. The manufacturing method as described in claim 2, characterized in that, The steps of forming the first opening and the second opening include: The buffer dielectric layer and the second metal interlayer dielectric layer around the upper electrode are etched sequentially to form the first through hole; Using the upper electrode layer as the etching stop layer, the buffer dielectric layer and the second metal interlayer dielectric layer are etched sequentially to simultaneously form the first trench and the second trench.

4. The manufacturing method as described in claim 2 or 3, characterized in that, The combined thickness of the capacitor dielectric layer and the upper electrode plate matches the height of the first through hole below the first trench.

5. The manufacturing method as described in claim 2 or 3, characterized in that, The substrate further comprises a first intermetallic dielectric layer and a lower metal interconnect formed in the first intermetallic dielectric layer; while forming the first via, a second via is also formed, aligned with and exposing a portion of the top surface of the lower metal interconnect; while forming the first trench and the second trench, a third trench is also formed, aligned with and communicating with the second via; while forming the lower electrode lead-out structure and the upper electrode lead-out structure, an upper metal interconnect filled in the third trench and a plug located between the upper metal interconnect and the lower metal interconnect are also formed.

6. The manufacturing method as described in claim 5, characterized in that, Before depositing the lower electrode layer on the substrate, a first metal barrier layer is also deposited on the first metal interlayer dielectric layer and the lower metal interconnect.

7. A MIM capacitor device, characterized in that, It is formed using the manufacturing method of any one of claims 1-6 for a MIM capacitor, and includes: A substrate, wherein a first metal interlayer dielectric layer and a lower metal interconnect formed therein are formed; The MIM capacitor structure includes a lower electrode plate, a capacitor dielectric layer, and an upper electrode plate sequentially formed on a portion of the top surface of the first intermetallic dielectric layer. A second intermetallic dielectric layer with a flat top surface is formed on the first intermetallic dielectric layer surrounding the MIM capacitor structure. The second intermetallic dielectric layer has a first through-hole, a second through-hole, a first trench, a second trench, and a third trench. The first through-hole is aligned with and exposes a portion of the top surface of the lower electrode plate. The second through-hole is aligned with and exposes a portion of the top surface of the lower metal interconnect. The first trench is aligned with and connects to the first through-hole. The second trench is aligned with and exposes a portion of the top surface of the upper electrode plate. The third trench is aligned with and connects to the second through-hole. The lower electrode metal wire is filled in the first groove and electrically connected to the lower electrode through a plug filled in the first through hole; The upper electrode metal wire is filled in the second trench and electrically connected to the upper electrode plate; The upper metal interconnect is filled in the third trench and electrically connected to the lower metal interconnect through a plug filled in the second through hole.

8. The MIM capacitor device as claimed in claim 7, characterized in that, The first through-hole and the second through-hole are formed by the same through-hole etching process, and the lower electrode metal line, the upper electrode metal line and the upper metal interconnect line are formed by the same metal deposition process.

9. The MIM capacitor device as claimed in claim 7, characterized in that, The material of the first or second intermetallic dielectric layer includes a low-K dielectric with a dielectric constant K less than 3; the material of the capacitor dielectric layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric with a dielectric constant K greater than 7, and a ferroelectric dielectric material; the material of the upper or lower electrode includes at least one of Ti, TiN, Ta, TaN, Al, and W; and the material of the lower or upper metal interconnect includes at least one of Cu, W, Al, and Au.

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